* config/iq2000/iq2000.h (IRA_COVER_CLASSES): Define.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@139720 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e84cdf1..d5236ed 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,7 @@
 2008-08-28  Nick Clifton  <nickc@redhat.com>
 
+       * config/iq2000/iq2000.h (IRA_COVER_CLASSES): Define.
+
        * config/fr30/fr30.h (IRA_COVER_CLASSES): Define.
 
        * config/m32r/m32r.h (IRA_COVER_CLASSES): Define.

diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h
index f99a85d..f09a9f7 100644 (file)
--- a/gcc/config/iq2000/iq2000.h
+++ b/gcc/config/iq2000/iq2000.h
@@ -1,6 +1,7 @@
 /* Definitions of target machine for GNU compiler.  
    Vitesse IQ2000 processors
-   Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008
+   Free Software Foundation, Inc.
 
    This file is part of GCC.
 
@@ -201,6 +202,11 @@ enum reg_class
 
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 
+#define IRA_COVER_CLASSES      \
+{                              \
+  GR_REGS, LIM_REG_CLASSES     \
+}
+
 #define REG_CLASS_NAMES                                                \
 {                                                              \
   "NO_REGS",                                                   \