&& ix86_match_ccmode (insn, CCNOmode)
&& (GET_MODE (operands[0]) == HImode
|| (GET_MODE (operands[0]) == QImode
- /* Ensure that the operand will remain sign extended immedaite. */
+ /* Ensure that the operand will remain sign extended immediate. */
&& INTVAL (operands[2]) >= 0
&& (TARGET_PROMOTE_QImode || optimize_size)))"
[(parallel [(set (reg:CCNO 17)
(match_operand:SI 2 "nonimmediate_operand" "rm")))
(const_int 2)))]
"TARGET_SSE2"
- "cvtsd2si\t{%2, %0|%0, %2}"
+ "cvtsi2sd\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
(set_attr "mode" "TI")])
(define_insn "sse2_umulv2siv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=y")
+ [(set (match_operand:V2DI 0 "register_operand" "=x")
(mult:V2DI (zero_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 1 "register_operand" "0")
(parallel [(const_int 0) (const_int 2)])))
(zero_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "ym")
+ (match_operand:V4SI 2 "nonimmediate_operand" "xm")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE2"
"pmuludq\t{%2, %0|%0, %2}"
(ashiftrt:V16QI
(plus:V16QI (plus:V16QI
(match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "ym"))
+ (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
(const_vector:V16QI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(ashiftrt:V8HI
(plus:V8HI (plus:V8HI
(match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "ym"))
+ (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
(const_vector:V8HI [(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(const_int 1) (const_int 1)
(define_insn "sse2_psadbw"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "ym")]
+ (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
UNSPEC_PSADBW))]
"TARGET_SSE2"
"psadbw\t{%2, %0|%0, %2}"
(define_insn "ashrv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "ri")))]
+ (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psraw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(define_insn "ashrv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "ri")))]
+ (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrad\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(define_insn "lshrv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "ri")))]
+ (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrlw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(define_insn "lshrv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "ri")))]
+ (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrld\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(define_insn "lshrv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "ri")))]
+ (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrlq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(define_insn "ashlv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
(ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "ri")))]
+ (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psllw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(define_insn "ashlv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "ri")))]
+ (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"pslld\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(define_insn "ashlv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "ri")))]
+ (match_operand:SI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psllq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(mult:SI (match_operand:SI 2 "immediate_operand" "i")
(const_int 8)))] UNSPEC_NOP))]
"TARGET_SSE2"
- "pslrdq\t{%2, %0|%0, %2}"
+ "psrldq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])