2004-04-30 Andrew Pinski <pinskia@physics.uc.edu>

        * rs6000-power2-1.c: Change to compile only.
        * rs6000-power2-2.c: Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@81337 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2214658..6ffc75a 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2004-04-30  Andrew Pinski  <pinskia@physics.uc.edu>
+
+       * rs6000-power2-1.c: Change to compile only.
+       * rs6000-power2-2.c: Likewise.
+
 2004-04-29  Andrew Pinski  <pinskia@physics.uc.edu>
 
        * gcc.dg/rs6000-power2-1.c: Change the options to be more correct.

diff --git a/gcc/testsuite/gcc.dg/rs6000-power2-1.c b/gcc/testsuite/gcc.dg/rs6000-power2-1.c
index 0e9b5aa..7d344a9 100644 (file)
--- a/gcc/testsuite/gcc.dg/rs6000-power2-1.c
+++ b/gcc/testsuite/gcc.dg/rs6000-power2-1.c
@@ -1,4 +1,4 @@
-/* { dg-do assemble { target powerpc-*-* rs6000-*-* }  } */
+/* { dg-do compile { target powerpc-*-* rs6000-*-* }  } */
 /* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */
 /* This used to ICE as the peephole was not checking to see
    if the register is a floating point one (I think this cannot

diff --git a/gcc/testsuite/gcc.dg/rs6000-power2-2.c b/gcc/testsuite/gcc.dg/rs6000-power2-2.c
index 74cc0ec..2fefbcb 100644 (file)
--- a/gcc/testsuite/gcc.dg/rs6000-power2-2.c
+++ b/gcc/testsuite/gcc.dg/rs6000-power2-2.c
@@ -1,4 +1,4 @@
-/* { dg-do assemble { target powerpc-*-* rs6000-*-* }  } */
+/* { dg-do compile { target powerpc-*-* rs6000-*-* }  } */
 /* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */
 /* { dg-final { scan-assembler-not "lfd" } } */
 /* { dg-final { scan-assembler-not "sfd" } } */