+2008-09-18 Nick Clifton <nickc@redhat.com>
+
+ * config/frv/frv.h (IRA_COVER_CLASSES): Define.
+ (SECONDARY_INPUT_RELOAD_CLASS): Omit unused argument in call
+ to frv_secondary_reload_class.
+ (SECONDARY_OUTPUT_RELOAD_CLASS): Likewise.
+ * config/frv/frv.c (TARGET_SECONDARY_RELOAD): Define.
+ (frv_secondary_reload_class): Omit unused parameter.
+ (frv_secondary_reload): New function. Handle the case when
+ secondary_reload_class() is called before the reload_(in|out)
+ _optabs have been initialised.
+ * config/frv/frv-protos.h (frv_secondary_reload_class): Omit
+ unused parameter.
+ * config/frv/frv.md: Define an exclusion set between fr550_m0
+ and fr550_f0.
+
2008-09-18 Richard Guenther <rguenther@suse.de>
PR tree-optimization/37456
extern int frv_trampoline_size (void);
extern void frv_initialize_trampoline (rtx, rtx, rtx);
extern enum reg_class frv_secondary_reload_class
- (enum reg_class rclass,
- enum machine_mode mode,
- rtx x, int);
+ (enum reg_class,
+ enum machine_mode, rtx);
extern int frv_class_likely_spilled_p (enum reg_class rclass);
extern int frv_hard_regno_mode_ok (int, enum machine_mode);
extern int frv_hard_regno_nregs (int, enum machine_mode);
tree, bool);
static void frv_output_dwarf_dtprel (FILE *, int, rtx)
ATTRIBUTE_UNUSED;
+static bool frv_secondary_reload (bool, rtx, enum reg_class,
+ enum machine_mode,
+ secondary_reload_info *);
\f
/* Allow us to easily change the default for -malloc-cc. */
#ifndef DEFAULT_NO_ALLOC_CC
#define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
#endif
+#undef TARGET_SECONDARY_RELOAD
+#define TARGET_SECONDARY_RELOAD frv_secondary_reload
+
struct gcc_target targetm = TARGET_INITIALIZER;
#define FRV_SYMBOL_REF_TLS_P(RTX) \
enum reg_class
frv_secondary_reload_class (enum reg_class rclass,
enum machine_mode mode ATTRIBUTE_UNUSED,
- rtx x,
- int in_p ATTRIBUTE_UNUSED)
+ rtx x)
{
enum reg_class ret;
ret = GPR_REGS;
break;
- /* The accumulators need fpr registers */
+ /* The accumulators need fpr registers. */
case ACC_REGS:
case EVEN_ACC_REGS:
case QUAD_ACC_REGS:
return ret;
}
+/* This hook exists to catch the case where secondary_reload_class() is
+ called from init_reg_autoinc() in regclass.c - before the reload optabs
+ have been initialised. */
+
+static bool
+frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
+ enum machine_mode reload_mode,
+ secondary_reload_info * sri)
+{
+ enum reg_class rclass = NO_REGS;
+
+ if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
+ {
+ sri->icode = sri->prev_sri->t_icode;
+ return NO_REGS;
+ }
+
+ rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
+
+ if (rclass != NO_REGS)
+ {
+ enum insn_code icode = (in_p ? reload_in_optab[(int) reload_mode]
+ : reload_out_optab[(int) reload_mode]);
+ if (icode == 0)
+ {
+ /* This happens when then the reload_[in|out]_optabs have
+ not been initialised. */
+ sri->t_icode = CODE_FOR_nothing;
+ return rclass;
+ }
+ }
+
+ /* Fall back to the default secondary reload handler. */
+ return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
+
+}
\f
/* A C expression whose value is nonzero if pseudos that have been assigned to
registers of class RCLASS would likely be spilled because registers of RCLASS
/* Target macros for the FRV port of GCC.
- Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
+ Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
Free Software Foundation, Inc.
Contributed by Red Hat Inc.
{ 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /* ALL_REGS */\
}
+/* The following macro defines cover classes for Integrated Register
+ Allocator. Cover classes is a set of non-intersected register
+ classes covering all hard registers used for register allocation
+ purpose. Any move between two registers of a cover class should be
+ cheaper than load or store of the registers. The macro value is
+ array of register classes with LIM_REG_CLASSES used as the end
+ marker. */
+
+#define IRA_COVER_CLASSES \
+{ \
+ GPR_REGS, FPR_REGS, ACC_REGS, ICR_REGS, FCR_REGS, ICC_REGS, FCC_REGS, \
+ ACCG_REGS, SPR_REGS, \
+ LIM_REG_CLASSES \
+}
+
/* A C expression whose value is a register class containing hard register
REGNO. In general there is more than one such class; choose a class which
is "minimal", meaning that no smaller class also contains the register. */
#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
- frv_secondary_reload_class (CLASS, MODE, X, TRUE)
+ frv_secondary_reload_class (CLASS, MODE, X)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
- frv_secondary_reload_class (CLASS, MODE, X, FALSE)
+ frv_secondary_reload_class (CLASS, MODE, X)
/* A C expression whose value is nonzero if pseudos that have been assigned to
registers of class CLASS would likely be spilled because registers of CLASS
;; Frv Machine Description
-;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005, 2007
+;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005, 2007, 2008
;; Free Software Foundation, Inc.
;; Contributed by Red Hat, Inc.
(define_cpu_unit "fr550_f0,fr550_f1,fr550_f2,fr550_f3" "fr550_float_media")
(define_cpu_unit "fr550_m0,fr550_m1,fr550_m2,fr550_m3" "fr550_float_media")
(exclusion_set "fr550_f1,fr550_f2,fr550_f3" "fr550_m1,fr550_m2,fr550_m3")
+(exclusion_set "fr550_m0" "fr550_f1,fr550_f2,fr550_f3")
+;; FIXME: This next exclusion set should be defined as well, so that we do
+;; not get a packet containing multiple media instructions plus a single
+;; floating point instruction. At the moment we can get away with not
+;; defining it because gcc does not seem to generate such packets.
+;;
+;; If we do enable the exclusion however the insertion of fnop insns into
+;; a packet containing media instructions will stop working, because the
+;; fnop insn counts as a floating point instruction. The correct solution
+;; is to fix the reservation for the fnop insn so that it does not have the
+;; same restrictions as ordinary floating point insns.
+;;(exclusion_set "fr550_f0" "fr550_m1,fr550_m2,fr550_m3")
(define_reservation "fr550_float" "fr550_f0|fr550_f1|fr550_f2|fr550_f3")
(define_reservation "fr550_media" "fr550_m0|fr550_m1|fr550_m2|fr550_m3")
}
else
{
- operands[4] = GEN_INT ((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16)
- >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31)
+ operands[4] = GEN_INT (((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16)
+ >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31))
- ((unsigned HOST_WIDE_INT)1 << 31));
operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode));
}
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