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2007-09-09 Uros Bizjak <ubizjak@gmail.com>
authoruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Sun, 9 Sep 2007 09:04:59 +0000 (09:04 +0000)
committeruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Sun, 9 Sep 2007 09:04:59 +0000 (09:04 +0000)
        * config/i386/i386.md (X87MODEF12, SSEMODEF): Remove mode iterators.
        Substitute all uses with ...
        (MODEF): New mode iterator.

        (*cmpfp_<mode>_cc): Remove operand constraints from pre-regalloc
        define_insn_and_split splitter pattern.
        (fix_trunc<mode>_fisttp_i387_1): Ditto.
        (*fix_trunc<mode>_i387_1): Ditto.
        (*fistdi2_1): Ditto.
        (*fist<mode>2_1): Ditto.
        (frndintxf2_floor): Ditto.
        (*fist<mode>2_floor_1): Ditto.
        (frndintxf2_ceil): Ditto.
        (*fist<mode>2_ceil_1): Ditto.
        (frndintxf2_trunc): Ditto.
        (frndintxf2_mask_pm): Ditto.

        (prologue): Use (const_int 0) as never generated filler insn.
        (epilogue): Ditto.
        (sibcall_epilogue): Ditto.
        (eh_return_si): Ditto.
        (eh_return_di): Ditto.

        (add<mode>3): Rename from adddf3 and addsf3.  Macroize expander
        using MODEF mode iterator.
        (sub<mode>3): Rename from subdf3 and subsf3.  Macroize expander
        using MODEF mode iterator.
        (mul<mode>3): Rename from muldf3 and mulsf3.  Macroize expander
        using MODEF mode iterator.
        (nearbyint<mode>2): Rename from nearbyintdf2 and nearbyintsf2.
        Macroize expander using MODEF mode iterator.

        (zero_extendsidi2): Remove operand constraints from expander.
        (smuldi3_highpart): Ditto.
        (indirect_jump): Ditto.
        (tablejump): Ditto.
        (rsqrtsf2): Ditto.
        * config/i386/sse.md (storentv4sf): Ditto.
        (storentv2df): Ditto.
        (storentv2di): Ditto.
        (storentsi): Ditto.
        (sse2_cvtpd2ps): Ditto.
        (vec_interleave_highv16qi): Ditto.
        (vec_interleave_lowv16qi): Ditto.
        (vec_interleave_highv8hi): Ditto.
        (vec_interleave_lowv8hi): Ditto.
        (vec_interleave_highv4si): Ditto.
        (vec_interleave_lowv4si): Ditto.
        (vec_interleave_highv2di): Ditto.
        (vec_interleave_lowv2di): Ditto.
        (sse2_maskmovdqu): Ditto.
        * config/i386/mmx.md (mmx_maskmovq): Ditto.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@128290 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog patch | blob | history
gcc/config/i386/i386.md patch | blob | history
gcc/config/i386/mmx.md patch | blob | history
gcc/config/i386/sse.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index de8ecc2..c934e2f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,58 @@
+2007-09-09  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (X87MODEF12, SSEMODEF): Remove mode iterators.
+       Substitute all uses with ...
+       (MODEF): New mode iterator.
+
+       (*cmpfp_<mode>_cc): Remove operand constraints from pre-regalloc
+       define_insn_and_split splitter pattern.
+       (fix_trunc<mode>_fisttp_i387_1): Ditto.
+       (*fix_trunc<mode>_i387_1): Ditto.
+       (*fistdi2_1): Ditto.
+       (*fist<mode>2_1): Ditto.
+       (frndintxf2_floor): Ditto.
+       (*fist<mode>2_floor_1): Ditto.
+       (frndintxf2_ceil): Ditto.
+       (*fist<mode>2_ceil_1): Ditto.
+       (frndintxf2_trunc): Ditto.
+       (frndintxf2_mask_pm): Ditto.
+
+       (prologue): Use (const_int 0) as never generated filler insn.
+       (epilogue): Ditto.
+       (sibcall_epilogue): Ditto.
+       (eh_return_si): Ditto.
+       (eh_return_di): Ditto.
+
+       (add<mode>3): Rename from adddf3 and addsf3.  Macroize expander
+       using MODEF mode iterator.
+       (sub<mode>3): Rename from subdf3 and subsf3.  Macroize expander
+       using MODEF mode iterator.
+       (mul<mode>3): Rename from muldf3 and mulsf3.  Macroize expander
+       using MODEF mode iterator.
+       (nearbyint<mode>2): Rename from nearbyintdf2 and nearbyintsf2.
+       Macroize expander using MODEF mode iterator.
+
+       (zero_extendsidi2): Remove operand constraints from expander.
+       (smuldi3_highpart): Ditto.
+       (indirect_jump): Ditto.
+       (tablejump): Ditto.
+       (rsqrtsf2): Ditto.
+       * config/i386/sse.md (storentv4sf): Ditto.
+       (storentv2df): Ditto.
+       (storentv2di): Ditto.
+       (storentsi): Ditto.
+       (sse2_cvtpd2ps): Ditto.
+       (vec_interleave_highv16qi): Ditto.
+       (vec_interleave_lowv16qi): Ditto.
+       (vec_interleave_highv8hi): Ditto.
+       (vec_interleave_lowv8hi): Ditto.
+       (vec_interleave_highv4si): Ditto.
+       (vec_interleave_lowv4si): Ditto.
+       (vec_interleave_highv2di): Ditto.
+       (vec_interleave_lowv2di): Ditto.
+       (sse2_maskmovdqu): Ditto.
+       * config/i386/mmx.md (mmx_maskmovq): Ditto.
+
 2007-09-09  Ira Rosen  <irar@il.ibm.com>
 
        * tree-vectorizer.h (enum vect_def_type): Start enumeration from 1.
@@ -197,12 +252,12 @@
 2007-09-08  Uros Bizjak  <ubizjak@gmail.com>
 
        PR target/33329
-       PR target/26449
+       PR rtl-optimization/26449
        * config/i386/sse.md (mulv4si3): Do not expand sse2 sequence.
        (*sse2_mulv4si3): New define_insn_and_split pattern. Split insn in
        split1 pass.
        (mulv16qi3): Implement as define_insn_and_split pattern instead of
-       define_expand, to split insn in split1 pass.
+       define_expand.  Split insn in split1 pass.
        (mulv2di3): Ditto.
 
 2007-09-08  Dorit Nuzman  <dorit@il.ibm.com>
@@ -320,8 +375,8 @@
 2007-09-07  Dorit Nuzman  <dorit@il.ibm.com>
 
        PR tree-optimization/33299
-       * tree-vect-transform.c (vect_create_epilog_for_reduction): Update uses 
-       for all relevant loop-exit phis, not just the first.
+       * tree-vect-transform.c (vect_create_epilog_for_reduction): Update
+       uses for all relevant loop-exit phis, not just the first.
 
 2007-09-07  Richard Guenther  <rguenther@suse.de>
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a518aae..42b3bab 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -515,21 +515,18 @@
         (SI "general_operand")
         (DI "x86_64_general_operand")])
 
+;; SSE and x87 SFmode and DFmode floating point modes
+(define_mode_iterator MODEF [SF DF])
+
 ;; All x87 floating point modes
 (define_mode_iterator X87MODEF [SF DF XF])
 
-;; x87 SFmode and DFMode floating point modes
-(define_mode_iterator X87MODEF12 [SF DF])
-
 ;; All integer modes handled by x87 fisttp operator.
 (define_mode_iterator X87MODEI [HI SI DI])
 
 ;; All integer modes handled by integer x87 operators.
 (define_mode_iterator X87MODEI12 [HI SI])
 
-;; All SSE floating point modes
-(define_mode_iterator SSEMODEF [SF DF])
-
 ;; All integer modes handled by SSE cvtts?2si* operators.
 (define_mode_iterator SSEMODEI24 [SI DI])
 
@@ -689,8 +686,8 @@
 
 (define_expand "cmpsi_1"
   [(set (reg:CC FLAGS_REG)
-       (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
-                   (match_operand:SI 1 "general_operand" "ri,mr")))]
+       (compare:CC (match_operand:SI 0 "nonimmediate_operand" "")
+                   (match_operand:SI 1 "general_operand" "")))]
   ""
   "")
 
@@ -887,8 +884,8 @@
 
 (define_expand "cmp<mode>"
   [(set (reg:CC FLAGS_REG)
-       (compare:CC (match_operand:SSEMODEF 0 "cmp_fp_expander_operand" "")
-                   (match_operand:SSEMODEF 1 "cmp_fp_expander_operand" "")))]
+       (compare:CC (match_operand:MODEF 0 "cmp_fp_expander_operand" "")
+                   (match_operand:MODEF 1 "cmp_fp_expander_operand" "")))]
   "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
 {
   ix86_compare_op0 = operands[0];
@@ -991,8 +988,8 @@
   [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI
          [(compare:CCFP
-            (match_operand:X87MODEF12 1 "register_operand" "f")
-            (match_operand:X87MODEF12 2 "nonimmediate_operand" "fm"))]
+            (match_operand:MODEF 1 "register_operand" "f")
+            (match_operand:MODEF 2 "nonimmediate_operand" "fm"))]
          UNSPEC_FNSTSW))]
   "TARGET_80387"
   "* return output_fp_compare (insn, operands, 0, 0);"
@@ -1003,8 +1000,8 @@
 (define_insn_and_split "*cmpfp_<mode>_cc"
   [(set (reg:CCFP FLAGS_REG)
        (compare:CCFP
-         (match_operand:X87MODEF12 1 "register_operand" "f")
-         (match_operand:X87MODEF12 2 "nonimmediate_operand" "fm")))
+         (match_operand:MODEF 1 "register_operand" "f")
+         (match_operand:MODEF 2 "nonimmediate_operand" "fm")))
    (clobber (match_operand:HI 0 "register_operand" "=a"))]
   "TARGET_80387
    && TARGET_SAHF && !TARGET_CMOVE"
@@ -1185,7 +1182,7 @@
                      (match_operand 1 "register_operand" "f")))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[0]))
    && TARGET_CMOVE
-   && (!TARGET_SSE_MATH || !SSE_FLOAT_MODE_P (GET_MODE (operands[0])))
+   && !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
    && GET_MODE (operands[0]) == GET_MODE (operands[1])"
   "* return output_fp_compare (insn, operands, 1, 0);"
   [(set_attr "type" "fcmp")
@@ -1237,7 +1234,7 @@
                       (match_operand 1 "register_operand" "f")))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[0]))
    && TARGET_CMOVE
-   && (!TARGET_SSE_MATH || !SSE_FLOAT_MODE_P (GET_MODE (operands[0])))
+   && !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
    && GET_MODE (operands[0]) == GET_MODE (operands[1])"
   "* return output_fp_compare (insn, operands, 1, 1);"
   [(set_attr "type" "fcmp")
@@ -3527,8 +3524,8 @@
 
 ;; %%% Kill me once multi-word ops are sane.
 (define_expand "zero_extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-     (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
+  [(set (match_operand:DI 0 "register_operand" "")
+     (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
   ""
 {
   if (!TARGET_64BIT)
@@ -3959,7 +3956,7 @@
 
 (define_expand "extend<mode>xf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
-        (float_extend:XF (match_operand:X87MODEF12 1 "general_operand" "")))]
+        (float_extend:XF (match_operand:MODEF 1 "general_operand" "")))]
   "TARGET_80387"
 {
   /* ??? Needed for compress_float_constant since all fp constants
@@ -3980,7 +3977,7 @@
 (define_insn "*extend<mode>xf2_i387"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
         (float_extend:XF
-         (match_operand:X87MODEF12 1 "nonimmediate_operand" "fm,f")))]
+         (match_operand:MODEF 1 "nonimmediate_operand" "fm,f")))]
   "TARGET_80387"
   "* return output_387_reg_move (insn, operands);"
   [(set_attr "type" "fmov")
@@ -4130,8 +4127,8 @@
 ;; Conversion from XFmode to {SF,DF}mode
 
 (define_expand "truncxf<mode>2"
-  [(parallel [(set (match_operand:X87MODEF12 0 "nonimmediate_operand" "")
-                  (float_truncate:X87MODEF12
+  [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand" "")
+                  (float_truncate:MODEF
                     (match_operand:XF 1 "register_operand" "")))
              (clobber (match_dup 2))])]
   "TARGET_80387"
@@ -4177,8 +4174,8 @@
    (set_attr "mode" "DF")])
 
 (define_insn "truncxf<mode>2_i387_noop"
-  [(set (match_operand:X87MODEF12 0 "register_operand" "=f")
-       (float_truncate:X87MODEF12
+  [(set (match_operand:MODEF 0 "register_operand" "=f")
+       (float_truncate:MODEF
          (match_operand:XF 1 "register_operand" "f")))]
   "TARGET_80387 && flag_unsafe_math_optimizations"
   "* return output_387_reg_move (insn, operands);"
@@ -4186,8 +4183,8 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*truncxf<mode>2_i387"
-  [(set (match_operand:X87MODEF12 0 "memory_operand" "=m")
-       (float_truncate:X87MODEF12
+  [(set (match_operand:MODEF 0 "memory_operand" "=m")
+       (float_truncate:MODEF
          (match_operand:XF 1 "register_operand" "f")))]
   "TARGET_80387"
   "* return output_387_reg_move (insn, operands);"
@@ -4195,22 +4192,22 @@
    (set_attr "mode" "<MODE>")])
 
 (define_split
-  [(set (match_operand:X87MODEF12 0 "register_operand" "")
-       (float_truncate:X87MODEF12
+  [(set (match_operand:MODEF 0 "register_operand" "")
+       (float_truncate:MODEF
          (match_operand:XF 1 "register_operand" "")))
-   (clobber (match_operand:X87MODEF12 2 "memory_operand" ""))]
+   (clobber (match_operand:MODEF 2 "memory_operand" ""))]
   "TARGET_80387 && reload_completed"
-  [(set (match_dup 2) (float_truncate:X87MODEF12 (match_dup 1)))
+  [(set (match_dup 2) (float_truncate:MODEF (match_dup 1)))
    (set (match_dup 0) (match_dup 2))]
   "")
 
 (define_split
-  [(set (match_operand:X87MODEF12 0 "memory_operand" "")
-       (float_truncate:X87MODEF12
+  [(set (match_operand:MODEF 0 "memory_operand" "")
+       (float_truncate:MODEF
          (match_operand:XF 1 "register_operand" "")))
-   (clobber (match_operand:X87MODEF12 2 "memory_operand" ""))]
+   (clobber (match_operand:MODEF 2 "memory_operand" ""))]
   "TARGET_80387"
-  [(set (match_dup 0) (float_truncate:X87MODEF12 (match_dup 1)))]
+  [(set (match_dup 0) (float_truncate:MODEF (match_dup 1)))]
   "")
 \f
 ;; Signed conversion to DImode.
@@ -4230,7 +4227,7 @@
 
 (define_expand "fix_trunc<mode>di2"
   [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
-                   (fix:DI (match_operand:SSEMODEF 1 "register_operand" "")))
+                   (fix:DI (match_operand:MODEF 1 "register_operand" "")))
               (clobber (reg:CC FLAGS_REG))])]
   "TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))"
 {
@@ -4267,7 +4264,7 @@
 
 (define_expand "fix_trunc<mode>si2"
   [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
-                  (fix:SI (match_operand:SSEMODEF 1 "register_operand" "")))
+                  (fix:SI (match_operand:MODEF 1 "register_operand" "")))
              (clobber (reg:CC FLAGS_REG))])]
   "TARGET_80387 || SSE_FLOAT_MODE_P (<MODE>mode)"
 {
@@ -4309,7 +4306,7 @@
   [(parallel
     [(set (match_operand:SI 0 "register_operand" "")
          (unsigned_fix:SI
-           (match_operand:SSEMODEF 1 "nonimmediate_operand" "")))
+           (match_operand:MODEF 1 "nonimmediate_operand" "")))
      (use (match_dup 2))
      (clobber (match_scratch:<ssevecmode> 3 ""))
      (clobber (match_scratch:<ssevecmode> 4 ""))])]
@@ -4329,7 +4326,7 @@
 (define_insn_and_split "*fixuns_trunc<mode>_1"
   [(set (match_operand:SI 0 "register_operand" "=&x,&x")
        (unsigned_fix:SI
-         (match_operand:SSEMODEF 3 "nonimmediate_operand" "xm,xm")))
+         (match_operand:MODEF 3 "nonimmediate_operand" "xm,xm")))
    (use (match_operand:<ssevecmode> 4  "nonimmediate_operand" "m,x"))
    (clobber (match_scratch:<ssevecmode> 1 "=x,&x"))
    (clobber (match_scratch:<ssevecmode> 2 "=x,x"))]
@@ -4348,7 +4345,7 @@
 
 (define_expand "fixuns_trunc<mode>hi2"
   [(set (match_dup 2)
-       (fix:SI (match_operand:SSEMODEF 1 "nonimmediate_operand" "")))
+       (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "")))
    (set (match_operand:HI 0 "nonimmediate_operand" "")
        (subreg:HI (match_dup 2) 0))]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
@@ -4357,7 +4354,7 @@
 ;; When SSE is available, it is always faster to use it!
 (define_insn "fix_trunc<mode>di_sse"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
-       (fix:DI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,m")))]
+       (fix:DI (match_operand:MODEF 1 "nonimmediate_operand" "x,m")))]
   "TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode)
    && (!TARGET_FISTTP || TARGET_SSE_MATH)"
   "cvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
@@ -4368,7 +4365,7 @@
 
 (define_insn "fix_trunc<mode>si_sse"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
-       (fix:SI (match_operand:SSEMODEF 1 "nonimmediate_operand" "x,m")))]
+       (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "x,m")))]
   "SSE_FLOAT_MODE_P (<MODE>mode)
    && (!TARGET_FISTTP || TARGET_SSE_MATH)"
   "cvtts<ssemodefsuffix>2si\t{%1, %0|%0, %1}"
@@ -4379,8 +4376,8 @@
 
 ;; Shorten x87->SSE reload sequences of fix_trunc?f?i_sse patterns.
 (define_peephole2
-  [(set (match_operand:SSEMODEF 0 "register_operand" "")
-       (match_operand:SSEMODEF 1 "memory_operand" ""))
+  [(set (match_operand:MODEF 0 "register_operand" "")
+       (match_operand:MODEF 1 "memory_operand" ""))
    (set (match_operand:SSEMODEI24 2 "register_operand" "")
        (fix:SSEMODEI24 (match_dup 0)))]
   "TARGET_SHORTEN_X87_SSE
@@ -4408,8 +4405,8 @@
   "")
 
 (define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
-  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
-       (fix:X87MODEI (match_operand 1 "register_operand" "f,f")))]
+  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
+       (fix:X87MODEI (match_operand 1 "register_operand" "")))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && TARGET_FISTTP
    && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
@@ -4488,8 +4485,8 @@
 ;; clobbering insns can be used. Look at emit_i387_cw_initialization ()
 ;; function in i386.c.
 (define_insn_and_split "*fix_trunc<mode>_i387_1"
-  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
-       (fix:X87MODEI (match_operand 1 "register_operand" "f,f")))
+  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
+       (fix:X87MODEI (match_operand 1 "register_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
   "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
    && !TARGET_FISTTP
@@ -4656,8 +4653,8 @@
 ;; wants to be able to do this between registers.
 
 (define_expand "floathi<mode>2"
-  [(set (match_operand:SSEMODEF 0 "register_operand" "")
-       (float:SSEMODEF (match_operand:HI 1 "nonimmediate_operand" "")))]
+  [(set (match_operand:MODEF 0 "register_operand" "")
+       (float:MODEF (match_operand:HI 1 "nonimmediate_operand" "")))]
   "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
 {
   if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
@@ -4670,8 +4667,8 @@
 })
 
 (define_insn "*floathi<mode>2_i387"
-  [(set (match_operand:X87MODEF12 0 "register_operand" "=f,f")
-       (float:X87MODEF12
+  [(set (match_operand:MODEF 0 "register_operand" "=f,f")
+       (float:MODEF
          (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
   "TARGET_80387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
@@ -4685,8 +4682,8 @@
    (set_attr "fp_int_src" "true")])
 
 (define_expand "floatsi<mode>2"
-  [(set (match_operand:SSEMODEF 0 "register_operand" "")
-       (float:SSEMODEF (match_operand:SI 1 "nonimmediate_operand" "")))]
+  [(set (match_operand:MODEF 0 "register_operand" "")
+       (float:MODEF (match_operand:SI 1 "nonimmediate_operand" "")))]
   "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
   "")
 
@@ -4745,8 +4742,8 @@
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatsi<mode>2_i387"
-  [(set (match_operand:X87MODEF12 0 "register_operand" "=f,f")
-       (float:X87MODEF12
+  [(set (match_operand:MODEF 0 "register_operand" "=f,f")
+       (float:MODEF
          (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
   "TARGET_80387"
   "@
@@ -4830,8 +4827,8 @@
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatdi<mode>2_i387"
-  [(set (match_operand:X87MODEF12 0 "register_operand" "=f,f")
-       (float:X87MODEF12
+  [(set (match_operand:MODEF 0 "register_operand" "=f,f")
+       (float:MODEF
          (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
   "TARGET_80387"
   "@
@@ -6676,18 +6673,11 @@
   "TARGET_80387"
   "")
 
-(define_expand "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "")
-       (plus:DF (match_operand:DF 1 "register_operand" "")
-                (match_operand:DF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
-  "")
-
-(define_expand "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "")
-       (plus:SF (match_operand:SF 1 "register_operand" "")
-                (match_operand:SF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387 || TARGET_SSE_MATH"
+(define_expand "add<mode>3"
+  [(set (match_operand:MODEF 0 "register_operand" "")
+       (plus:MODEF (match_operand:MODEF 1 "register_operand" "")
+                   (match_operand:MODEF 2 "nonimmediate_operand" "")))]
+  "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
   "")
 \f
 ;; Subtract instructions
@@ -7052,18 +7042,11 @@
   "TARGET_80387"
   "")
 
-(define_expand "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "")
-       (minus:DF (match_operand:DF 1 "register_operand" "")
-                 (match_operand:DF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
-  "")
-
-(define_expand "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "")
-       (minus:SF (match_operand:SF 1 "register_operand" "")
-                 (match_operand:SF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387 || TARGET_SSE_MATH"
+(define_expand "sub<mode>3"
+  [(set (match_operand:MODEF 0 "register_operand" "")
+       (minus:MODEF (match_operand:MODEF 1 "register_operand" "")
+                    (match_operand:MODEF 2 "nonimmediate_operand" "")))]
+  "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
   "")
 \f
 ;; Multiply instructions
@@ -7513,7 +7496,7 @@
    (set_attr "mode" "SI")])
 
 (define_expand "smuldi3_highpart"
-  [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
+  [(parallel [(set (match_operand:DI 0 "register_operand" "")
                   (truncate:DI
                     (lshiftrt:TI
                       (mult:TI (sign_extend:TI
@@ -7614,18 +7597,11 @@
   "TARGET_80387"
   "")
 
-(define_expand "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "")
-       (mult:DF (match_operand:DF 1 "register_operand" "")
-                (match_operand:DF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
-  "")
-
-(define_expand "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "")
-       (mult:SF (match_operand:SF 1 "register_operand" "")
-                (match_operand:SF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387 || TARGET_SSE_MATH"
+(define_expand "mul<mode>3"
+  [(set (match_operand:MODEF 0 "register_operand" "")
+       (mult:MODEF (match_operand:MODEF 1 "register_operand" "")
+                   (match_operand:MODEF 2 "nonimmediate_operand" "")))]
+  "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
   "")
 \f
 ;; Divide instructions
@@ -14234,7 +14210,7 @@
    (set_attr "modrm" "0")])
 
 (define_expand "indirect_jump"
-  [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
+  [(set (pc) (match_operand 0 "nonimmediate_operand" ""))]
   ""
   "")
 
@@ -14253,7 +14229,7 @@
    (set_attr "length_immediate" "0")])
 
 (define_expand "tablejump"
-  [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
+  [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" ""))
              (use (label_ref (match_operand 1 "" "")))])]
   ""
 {
@@ -14670,7 +14646,7 @@
   [(set_attr "length" "16")])
 
 (define_expand "prologue"
-  [(const_int 1)]
+  [(const_int 0)]
   ""
   "ix86_expand_prologue (); DONE;")
 
@@ -14718,12 +14694,12 @@
    (set_attr "length" "11")])
 
 (define_expand "epilogue"
-  [(const_int 1)]
+  [(const_int 0)]
   ""
   "ix86_expand_epilogue (1); DONE;")
 
 (define_expand "sibcall_epilogue"
-  [(const_int 1)]
+  [(const_int 0)]
   ""
   "ix86_expand_epilogue (0); DONE;")
 
@@ -14756,7 +14732,7 @@
   "!TARGET_64BIT"
   "#"
   "reload_completed"
-  [(const_int 1)]
+  [(const_int 0)]
   "ix86_expand_epilogue (2); DONE;")
 
 (define_insn_and_split "eh_return_di"
@@ -14766,7 +14742,7 @@
   "TARGET_64BIT"
   "#"
   "reload_completed"
-  [(const_int 1)]
+  [(const_int 0)]
   "ix86_expand_epilogue (2); DONE;")
 
 (define_insn "leave"
@@ -16071,7 +16047,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (match_operator:XF 3 "binary_fp_operator"
           [(float_extend:XF
-             (match_operand:X87MODEF12 1 "nonimmediate_operand" "fm,0"))
+             (match_operand:MODEF 1 "nonimmediate_operand" "fm,0"))
            (match_operand:XF 2 "register_operand" "0,f")]))]
   "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
@@ -16089,7 +16065,7 @@
        (match_operator:XF 3 "binary_fp_operator"
          [(match_operand:XF 1 "register_operand" "0,f")
           (float_extend:XF
-            (match_operand:X87MODEF12 2 "nonimmediate_operand" "fm,0"))]))]
+            (match_operand:MODEF 2 "nonimmediate_operand" "fm,0"))]))]
   "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type")
@@ -16105,9 +16081,9 @@
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (match_operator:XF 3 "binary_fp_operator"
          [(float_extend:XF
-            (match_operand:X87MODEF12 1 "register_operand" "0,f"))
+            (match_operand:MODEF 1 "register_operand" "0,f"))
           (float_extend:XF
-            (match_operand:X87MODEF12 2 "nonimmediate_operand" "fm,0"))]))]
+            (match_operand:MODEF 2 "nonimmediate_operand" "fm,0"))]))]
   "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type")
@@ -16165,8 +16141,8 @@
 ;; all fancy i386 XFmode math functions.
 
 (define_insn "truncxf<mode>2_i387_noop_unspec"
-  [(set (match_operand:X87MODEF12 0 "register_operand" "=f")
-       (unspec:X87MODEF12 [(match_operand:XF 1 "register_operand" "f")]
+  [(set (match_operand:MODEF 0 "register_operand" "=f")
+       (unspec:MODEF [(match_operand:XF 1 "register_operand" "f")]
        UNSPEC_TRUNC_NOOP))]
   "TARGET_USE_FANCY_MATH_387"
   "* return output_387_reg_move (insn, operands);"
@@ -16187,7 +16163,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
        (sqrt:XF
          (float_extend:XF
-           (match_operand:X87MODEF12 1 "register_operand" "0"))))]
+           (match_operand:MODEF 1 "register_operand" "0"))))]
   "TARGET_USE_FANCY_MATH_387"
   "fsqrt"
   [(set_attr "type" "fpspc")
@@ -16205,8 +16181,8 @@
    (set_attr "mode" "SF")])
 
 (define_expand "rsqrtsf2"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-       (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
+  [(set (match_operand:SF 0 "register_operand" "")
+       (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "")]
                   UNSPEC_RSQRT))]
   "TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
    && flag_finite_math_only && !flag_trapping_math
@@ -16217,9 +16193,9 @@
 })
 
 (define_insn "*sqrt<mode>2_sse"
-  [(set (match_operand:SSEMODEF 0 "register_operand" "=x")
-       (sqrt:SSEMODEF
-         (match_operand:SSEMODEF 1 "nonimmediate_operand" "xm")))]
+  [(set (match_operand:MODEF 0 "register_operand" "=x")
+       (sqrt:MODEF
+         (match_operand:MODEF 1 "nonimmediate_operand" "xm")))]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
   "sqrts<ssemodefsuffix>\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")
@@ -16228,9 +16204,9 @@
    (set_attr "amdfam10_decode" "*")])
 
 (define_expand "sqrt<mode>2"
-  [(set (match_operand:X87MODEF12 0 "register_operand" "")
-       (sqrt:X87MODEF12
-         (match_operand:X87MODEF12 1 "nonimmediate_operand" "")))]
+  [(set (match_operand:MODEF 0 "register_operand" "")
+       (sqrt:MODEF
+         (match_operand:MODEF 1 "nonimmediate_operand" "")))]
   "TARGET_USE_FANCY_MATH_387
    || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
 {
@@ -16290,9 +16266,9 @@
 })
 
 (define_expand "fmod<mode>3"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "general_operand" ""))
-   (use (match_operand:X87MODEF12 2 "general_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "general_operand" ""))
+   (use (match_operand:MODEF 2 "general_operand" ""))]
   "TARGET_USE_FANCY_MATH_387"
 {
   rtx label = gen_label_rtx ();
@@ -16354,9 +16330,9 @@
 })
 
 (define_expand "remainder<mode>3"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "general_operand" ""))
-   (use (match_operand:X87MODEF12 2 "general_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "general_operand" ""))
+   (use (match_operand:MODEF 2 "general_operand" ""))]
   "TARGET_USE_FANCY_MATH_387"
 {
   rtx label = gen_label_rtx ();
@@ -16395,7 +16371,7 @@
 (define_insn "*sin_extend<mode>xf2_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (unspec:XF [(float_extend:XF
-                     (match_operand:X87MODEF12 1 "register_operand" "0"))]
+                     (match_operand:MODEF 1 "register_operand" "0"))]
                   UNSPEC_SIN))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
@@ -16417,7 +16393,7 @@
 (define_insn "*cos_extend<mode>xf2_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (unspec:XF [(float_extend:XF
-                     (match_operand:X87MODEF12 1 "register_operand" "0"))]
+                     (match_operand:MODEF 1 "register_operand" "0"))]
                   UNSPEC_COS))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
@@ -16452,7 +16428,7 @@
    (set (match_operand:XF 1 "register_operand" "")
        (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
   "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
-   && !reload_completed && !reload_in_progress"
+   && !(reload_completed || reload_in_progress)"
   [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]
   "")
 
@@ -16463,14 +16439,14 @@
    (set (match_operand:XF 1 "register_operand" "")
        (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
   "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
-   && !reload_completed && !reload_in_progress"
+   && !(reload_completed || reload_in_progress)"
   [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]
   "")
 
 (define_insn "sincos_extend<mode>xf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (unspec:XF [(float_extend:XF
-                     (match_operand:X87MODEF12 2 "register_operand" "0"))]
+                     (match_operand:MODEF 2 "register_operand" "0"))]
                   UNSPEC_SINCOS_COS))
    (set (match_operand:XF 1 "register_operand" "=u")
         (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
@@ -16485,31 +16461,31 @@
 (define_split
   [(set (match_operand:XF 0 "register_operand" "")
        (unspec:XF [(float_extend:XF
-                     (match_operand:X87MODEF12 2 "register_operand" ""))]
+                     (match_operand:MODEF 2 "register_operand" ""))]
                   UNSPEC_SINCOS_COS))
    (set (match_operand:XF 1 "register_operand" "")
        (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
   "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
-   && !reload_completed && !reload_in_progress"
+   && !(reload_completed || reload_in_progress)"
   [(set (match_dup 1) (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))]
   "")
 
 (define_split
   [(set (match_operand:XF 0 "register_operand" "")
        (unspec:XF [(float_extend:XF
-                     (match_operand:X87MODEF12 2 "register_operand" ""))]
+                     (match_operand:MODEF 2 "register_operand" ""))]
                   UNSPEC_SINCOS_COS))
    (set (match_operand:XF 1 "register_operand" "")
        (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
   "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
-   && !reload_completed && !reload_in_progress"
+   && !(reload_completed || reload_in_progress)"
   [(set (match_dup 0) (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))]
   "")
 
 (define_expand "sincos<mode>3"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "register_operand" ""))
-   (use (match_operand:X87MODEF12 2 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))
+   (use (match_operand:MODEF 2 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16538,11 +16514,11 @@
    (set_attr "mode" "XF")])
 
 (define_insn "fptan_extend<mode>xf4_i387"
-  [(set (match_operand:X87MODEF12 0 "register_operand" "=f")
-       (match_operand:X87MODEF12 3 "const_double_operand" "F"))
+  [(set (match_operand:MODEF 0 "register_operand" "=f")
+       (match_operand:MODEF 3 "const_double_operand" "F"))
    (set (match_operand:XF 1 "register_operand" "=u")
         (unspec:XF [(float_extend:XF
-                     (match_operand:X87MODEF12 2 "register_operand" "0"))]
+                     (match_operand:MODEF 2 "register_operand" "0"))]
                   UNSPEC_TAN))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
@@ -16567,8 +16543,8 @@
 })
 
 (define_expand "tan<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16600,9 +16576,9 @@
 (define_insn "fpatan_extend<mode>xf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
         (unspec:XF [(float_extend:XF
-                     (match_operand:X87MODEF12 1 "register_operand" "0"))
+                     (match_operand:MODEF 1 "register_operand" "0"))
                    (float_extend:XF
-                     (match_operand:X87MODEF12 2 "register_operand" "u"))]
+                     (match_operand:MODEF 2 "register_operand" "u"))]
                   UNSPEC_FPATAN))
    (clobber (match_scratch:XF 3 "=2"))]
   "TARGET_USE_FANCY_MATH_387
@@ -16624,9 +16600,9 @@
   "")
 
 (define_expand "atan2<mode>3"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "register_operand" ""))
-   (use (match_operand:X87MODEF12 2 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))
+   (use (match_operand:MODEF 2 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16653,8 +16629,8 @@
 })
 
 (define_expand "atan<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16692,8 +16668,8 @@
 })
 
 (define_expand "asin<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "general_operand" ""))]
  "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16730,8 +16706,8 @@
 })
 
 (define_expand "acos<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "general_operand" ""))]
  "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16761,7 +16737,7 @@
 (define_insn "fyl2x_extend<mode>xf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
         (unspec:XF [(float_extend:XF
-                     (match_operand:X87MODEF12 1 "register_operand" "0"))
+                     (match_operand:MODEF 1 "register_operand" "0"))
                    (match_operand:XF 2 "register_operand" "u")]
                   UNSPEC_FYL2X))
    (clobber (match_scratch:XF 3 "=2"))]
@@ -16786,8 +16762,8 @@
 })
 
 (define_expand "log<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16816,8 +16792,8 @@
 })
 
 (define_expand "log10<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16846,8 +16822,8 @@
 })
 
 (define_expand "log2<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16878,7 +16854,7 @@
 (define_insn "fyl2xp1_extend<mode>xf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
         (unspec:XF [(float_extend:XF
-                     (match_operand:X87MODEF12 1 "register_operand" "0"))
+                     (match_operand:MODEF 1 "register_operand" "0"))
                    (match_operand:XF 2 "register_operand" "u")]
                   UNSPEC_FYL2XP1))
    (clobber (match_scratch:XF 3 "=2"))]
@@ -16901,8 +16877,8 @@
 })
 
 (define_expand "log1p<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16932,7 +16908,7 @@
 (define_insn "fxtract_extend<mode>xf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (unspec:XF [(float_extend:XF
-                     (match_operand:X87MODEF12 2 "register_operand" "0"))]
+                     (match_operand:MODEF 2 "register_operand" "0"))]
                   UNSPEC_XTRACT_FRACT))
    (set (match_operand:XF 1 "register_operand" "=u")
         (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_XTRACT_EXP))]
@@ -16957,8 +16933,8 @@
 })
 
 (define_expand "logb<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -16988,7 +16964,7 @@
 
 (define_expand "ilogb<mode>2"
   [(use (match_operand:SI 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -17064,8 +17040,8 @@
 })
 
 (define_expand "exp<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "general_operand" ""))]
  "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -17094,8 +17070,8 @@
 })
 
 (define_expand "exp10<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "general_operand" ""))]
  "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -17124,8 +17100,8 @@
 })
 
 (define_expand "exp2<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "general_operand" ""))]
  "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -17178,8 +17154,8 @@
 })
 
 (define_expand "expm1<mode>2"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "general_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "general_operand" ""))]
  "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -17212,8 +17188,8 @@
 })
 
 (define_expand "ldexp<mode>3"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "general_operand" ""))
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "general_operand" ""))
    (use (match_operand:SI 2 "register_operand" ""))]
  "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
@@ -17244,9 +17220,9 @@
 })
 
 (define_expand "scalb<mode>3"
-  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
-   (use (match_operand:X87MODEF12 1 "general_operand" ""))
-   (use (match_operand:X87MODEF12 2 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "general_operand" ""))
+   (use (match_operand:MODEF 2 "register_operand" ""))]
  "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -17265,10 +17241,10 @@
 \f
 
 (define_insn "sse4_1_round<mode>2"
-  [(set (match_operand:SSEMODEF 0 "register_operand" "=x")
-       (unspec:SSEMODEF [(match_operand:SSEMODEF 1 "register_operand" "x")
-                         (match_operand:SI 2 "const_0_to_15_operand" "n")]
-                        UNSPEC_ROUND))]
+  [(set (match_operand:MODEF 0 "register_operand" "=x")
+       (unspec:MODEF [(match_operand:MODEF 1 "register_operand" "x")
+                      (match_operand:SI 2 "const_0_to_15_operand" "n")]
+                     UNSPEC_ROUND))]
   "TARGET_SSE4_1"
   "rounds<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ssecvt")
@@ -17286,8 +17262,8 @@
    (set_attr "mode" "XF")])
 
 (define_expand "rint<mode>2"
-  [(use (match_operand:SSEMODEF 0 "register_operand" ""))
-   (use (match_operand:SSEMODEF 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "(TARGET_USE_FANCY_MATH_387
     && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -17320,8 +17296,8 @@
 })
 
 (define_expand "round<mode>2"
-  [(match_operand:SSEMODEF 0 "register_operand" "")
-   (match_operand:SSEMODEF 1 "nonimmediate_operand" "")]
+  [(match_operand:MODEF 0 "register_operand" "")
+   (match_operand:MODEF 1 "nonimmediate_operand" "")]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
    && !flag_trapping_math && !flag_rounding_math
    && !optimize_size"
@@ -17334,8 +17310,8 @@
 })
 
 (define_insn_and_split "*fistdi2_1"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
-       (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "")
+       (unspec:DI [(match_operand:XF 1 "register_operand" "")]
                   UNSPEC_FIST))]
   "TARGET_USE_FANCY_MATH_387
    && !(reload_completed || reload_in_progress)"
@@ -17401,8 +17377,8 @@
   "")
 
 (define_insn_and_split "*fist<mode>2_1"
-  [(set (match_operand:X87MODEI12 0 "register_operand" "=r")
-       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
+  [(set (match_operand:X87MODEI12 0 "register_operand" "")
+       (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
                           UNSPEC_FIST))]
   "TARGET_USE_FANCY_MATH_387
    && !(reload_completed || reload_in_progress)"
@@ -17463,18 +17439,18 @@
   "TARGET_USE_FANCY_MATH_387"
   "")
 
-(define_expand "lrint<SSEMODEF:mode><SSEMODEI24:mode>2"
+(define_expand "lrint<MODEF:mode><SSEMODEI24:mode>2"
   [(set (match_operand:SSEMODEI24 0 "nonimmediate_operand" "")
-     (unspec:SSEMODEI24 [(match_operand:SSEMODEF 1 "register_operand" "")]
+     (unspec:SSEMODEI24 [(match_operand:MODEF 1 "register_operand" "")]
                        UNSPEC_FIX_NOTRUNC))]
-  "SSE_FLOAT_MODE_P (<SSEMODEF:MODE>mode) && TARGET_SSE_MATH
+  "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)"
   "")
 
-(define_expand "lround<SSEMODEF:mode><SSEMODEI24:mode>2"
+(define_expand "lround<MODEF:mode><SSEMODEI24:mode>2"
   [(match_operand:SSEMODEI24 0 "nonimmediate_operand" "")
-   (match_operand:SSEMODEF 1 "register_operand" "")]
-  "SSE_FLOAT_MODE_P (<SSEMODEF:MODE>mode) && TARGET_SSE_MATH
+   (match_operand:MODEF 1 "register_operand" "")]
+  "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)
    && !flag_trapping_math && !flag_rounding_math
    && !optimize_size"
@@ -17485,8 +17461,8 @@
 
 ;; Rounding mode control word calculation could clobber FLAGS_REG.
 (define_insn_and_split "frndintxf2_floor"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-       (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+  [(set (match_operand:XF 0 "register_operand" "")
+       (unspec:XF [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FRNDINT_FLOOR))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_USE_FANCY_MATH_387
@@ -17533,8 +17509,8 @@
 })
 
 (define_expand "floor<mode>2"
-  [(use (match_operand:SSEMODEF 0 "register_operand" ""))
-   (use (match_operand:SSEMODEF 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "(TARGET_USE_FANCY_MATH_387
     && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -17569,8 +17545,8 @@
 })
 
 (define_insn_and_split "*fist<mode>2_floor_1"
-  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
-       (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "f,f")]
+  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
+       (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST_FLOOR))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_USE_FANCY_MATH_387
@@ -17728,7 +17704,7 @@
 
 (define_expand "lfloor<mode>di2"
   [(match_operand:DI 0 "nonimmediate_operand" "")
-   (match_operand:SSEMODEF 1 "register_operand" "")]
+   (match_operand:MODEF 1 "register_operand" "")]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT
    && !flag_trapping_math
    && !optimize_size"
@@ -17739,7 +17715,7 @@
 
 (define_expand "lfloor<mode>si2"
   [(match_operand:SI 0 "nonimmediate_operand" "")
-   (match_operand:SSEMODEF 1 "register_operand" "")]
+   (match_operand:MODEF 1 "register_operand" "")]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
    && !flag_trapping_math
    && (!optimize_size || !TARGET_64BIT)"
@@ -17750,8 +17726,8 @@
 
 ;; Rounding mode control word calculation could clobber FLAGS_REG.
 (define_insn_and_split "frndintxf2_ceil"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-       (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+  [(set (match_operand:XF 0 "register_operand" "")
+       (unspec:XF [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FRNDINT_CEIL))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_USE_FANCY_MATH_387
@@ -17798,8 +17774,8 @@
 })
 
 (define_expand "ceil<mode>2"
-  [(use (match_operand:SSEMODEF 0 "register_operand" ""))
-   (use (match_operand:SSEMODEF 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "(TARGET_USE_FANCY_MATH_387
     && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -17834,8 +17810,8 @@
 })
 
 (define_insn_and_split "*fist<mode>2_ceil_1"
-  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
-       (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "f,f")]
+  [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
+       (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST_CEIL))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_USE_FANCY_MATH_387
@@ -17993,7 +17969,7 @@
 
 (define_expand "lceil<mode>di2"
   [(match_operand:DI 0 "nonimmediate_operand" "")
-   (match_operand:SSEMODEF 1 "register_operand" "")]
+   (match_operand:MODEF 1 "register_operand" "")]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT
    && !flag_trapping_math"
 {
@@ -18003,7 +17979,7 @@
 
 (define_expand "lceil<mode>si2"
   [(match_operand:SI 0 "nonimmediate_operand" "")
-   (match_operand:SSEMODEF 1 "register_operand" "")]
+   (match_operand:MODEF 1 "register_operand" "")]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
    && !flag_trapping_math"
 {
@@ -18013,8 +17989,8 @@
 
 ;; Rounding mode control word calculation could clobber FLAGS_REG.
 (define_insn_and_split "frndintxf2_trunc"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-       (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+  [(set (match_operand:XF 0 "register_operand" "")
+       (unspec:XF [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FRNDINT_TRUNC))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_USE_FANCY_MATH_387
@@ -18061,8 +18037,8 @@
 })
 
 (define_expand "btrunc<mode>2"
-  [(use (match_operand:SSEMODEF 0 "register_operand" ""))
-   (use (match_operand:SSEMODEF 1 "register_operand" ""))]
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "(TARGET_USE_FANCY_MATH_387
     && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
@@ -18098,8 +18074,8 @@
 
 ;; Rounding mode control word calculation could clobber FLAGS_REG.
 (define_insn_and_split "frndintxf2_mask_pm"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-       (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+  [(set (match_operand:XF 0 "register_operand" "")
+       (unspec:XF [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FRNDINT_MASK_PM))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_USE_FANCY_MATH_387
@@ -18146,37 +18122,21 @@
   DONE;
 })
 
-(define_expand "nearbyintdf2"
-  [(use (match_operand:DF 0 "register_operand" ""))
-   (use (match_operand:DF 1 "register_operand" ""))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-{
-  rtx op0 = gen_reg_rtx (XFmode);
-  rtx op1 = gen_reg_rtx (XFmode);
-
-  emit_insn (gen_extenddfxf2 (op1, operands[1]));
-  emit_insn (gen_frndintxf2_mask_pm (op0, op1));
-
-  emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
-  DONE;
-})
-
-(define_expand "nearbyintsf2"
-  [(use (match_operand:SF 0 "register_operand" ""))
-   (use (match_operand:SF 1 "register_operand" ""))]
+(define_expand "nearbyint<mode>2"
+  [(use (match_operand:MODEF 0 "register_operand" ""))
+   (use (match_operand:MODEF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
-   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
+   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+       || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
   rtx op1 = gen_reg_rtx (XFmode);
 
-  emit_insn (gen_extendsfxf2 (op1, operands[1]));
+  emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
   emit_insn (gen_frndintxf2_mask_pm (op0, op1));
 
-  emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
+  emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
   DONE;
 })
 
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 70073de..4123bc3 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1354,8 +1354,8 @@
 
 (define_expand "mmx_maskmovq"
   [(set (match_operand:V8QI 0 "memory_operand" "")
-       (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
-                     (match_operand:V8QI 2 "register_operand" "y")
+       (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "")
+                     (match_operand:V8QI 2 "register_operand" "")
                      (match_dup 0)]
                     UNSPEC_MASKMOV))]
   "TARGET_SSE || TARGET_3DNOW_A"
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 02964d7..cb63ab9 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -315,29 +315,29 @@
 ; define patterns for other modes that would expand to several insns.
 
 (define_expand "storentv4sf"
-  [(set (match_operand:V4SF 0 "memory_operand" "=m")
-       (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
+  [(set (match_operand:V4SF 0 "memory_operand" "")
+       (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")]
                     UNSPEC_MOVNT))]
   "TARGET_SSE"
   "")
 
 (define_expand "storentv2df"
-  [(set (match_operand:V2DF 0 "memory_operand" "=m")
-       (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
+  [(set (match_operand:V2DF 0 "memory_operand" "")
+       (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "")]
                     UNSPEC_MOVNT))]
   "TARGET_SSE2"
   "")
 
 (define_expand "storentv2di"
-  [(set (match_operand:V2DI 0 "memory_operand" "=m")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
+  [(set (match_operand:V2DI 0 "memory_operand" "")
+       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "")]
                     UNSPEC_MOVNT))]
   "TARGET_SSE2"
   "")
 
 (define_expand "storentsi"
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-       (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+  [(set (match_operand:SI 0 "memory_operand" "")
+       (unspec:SI [(match_operand:SI 1 "register_operand" "")]
                   UNSPEC_MOVNT))]
   "TARGET_SSE2"
   "")
@@ -2282,7 +2282,7 @@
   [(set (match_operand:V4SF 0 "register_operand" "")
        (vec_concat:V4SF
          (float_truncate:V2SF
-           (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
+           (match_operand:V2DF 1 "nonimmediate_operand" ""))
          (match_dup 2)))]
   "TARGET_SSE2"
   "operands[2] = CONST0_RTX (V2SFmode);")
@@ -4075,11 +4075,11 @@
 })
 
 (define_expand "vec_interleave_highv16qi"
-  [(set (match_operand:V16QI 0 "register_operand" "=x")
+  [(set (match_operand:V16QI 0 "register_operand" "")
         (vec_select:V16QI
           (vec_concat:V32QI
-            (match_operand:V16QI 1 "register_operand" "0")
-            (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
+            (match_operand:V16QI 1 "register_operand" "")
+            (match_operand:V16QI 2 "nonimmediate_operand" ""))
           (parallel [(const_int 8)  (const_int 24)
                      (const_int 9)  (const_int 25)
                      (const_int 10) (const_int 26)
@@ -4095,11 +4095,11 @@
 })
 
 (define_expand "vec_interleave_lowv16qi"
-  [(set (match_operand:V16QI 0 "register_operand" "=x")
+  [(set (match_operand:V16QI 0 "register_operand" "")
         (vec_select:V16QI
           (vec_concat:V32QI
-            (match_operand:V16QI 1 "register_operand" "0")
-            (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
+            (match_operand:V16QI 1 "register_operand" "")
+            (match_operand:V16QI 2 "nonimmediate_operand" ""))
           (parallel [(const_int 0) (const_int 16)
                      (const_int 1) (const_int 17)
                      (const_int 2) (const_int 18)
@@ -4115,11 +4115,11 @@
 })
 
 (define_expand "vec_interleave_highv8hi"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
+  [(set (match_operand:V8HI 0 "register_operand" "=")
         (vec_select:V8HI
           (vec_concat:V16HI
-            (match_operand:V8HI 1 "register_operand" "0")
-            (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
+            (match_operand:V8HI 1 "register_operand" "")
+            (match_operand:V8HI 2 "nonimmediate_operand" ""))
           (parallel [(const_int 4) (const_int 12)
                      (const_int 5) (const_int 13)
                      (const_int 6) (const_int 14)
@@ -4131,11 +4131,11 @@
 })
 
 (define_expand "vec_interleave_lowv8hi"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
+  [(set (match_operand:V8HI 0 "register_operand" "")
         (vec_select:V8HI
           (vec_concat:V16HI
-            (match_operand:V8HI 1 "register_operand" "0")
-            (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
+            (match_operand:V8HI 1 "register_operand" "")
+            (match_operand:V8HI 2 "nonimmediate_operand" ""))
           (parallel [(const_int 0) (const_int 8)
                      (const_int 1) (const_int 9)
                      (const_int 2) (const_int 10)
@@ -4147,11 +4147,11 @@
 })
 
 (define_expand "vec_interleave_highv4si"
-  [(set (match_operand:V4SI 0 "register_operand" "=x")
+  [(set (match_operand:V4SI 0 "register_operand" "")
         (vec_select:V4SI
           (vec_concat:V8SI
-            (match_operand:V4SI 1 "register_operand" "0")
-            (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
+            (match_operand:V4SI 1 "register_operand" "")
+            (match_operand:V4SI 2 "nonimmediate_operand" ""))
           (parallel [(const_int 2) (const_int 6)
                      (const_int 3) (const_int 7)])))]
   "TARGET_SSE2"
@@ -4161,11 +4161,11 @@
 })
 
 (define_expand "vec_interleave_lowv4si"
-  [(set (match_operand:V4SI 0 "register_operand" "=x")
+  [(set (match_operand:V4SI 0 "register_operand" "")
         (vec_select:V4SI
           (vec_concat:V8SI
-            (match_operand:V4SI 1 "register_operand" "0")
-            (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
+            (match_operand:V4SI 1 "register_operand" "")
+            (match_operand:V4SI 2 "nonimmediate_operand" ""))
           (parallel [(const_int 0) (const_int 4)
                      (const_int 1) (const_int 5)])))]
   "TARGET_SSE2"
@@ -4175,11 +4175,11 @@
 })
 
 (define_expand "vec_interleave_highv2di"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
+  [(set (match_operand:V2DI 0 "register_operand" "")
         (vec_select:V2DI
           (vec_concat:V4DI
-            (match_operand:V2DI 1 "register_operand" "0")
-            (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
+            (match_operand:V2DI 1 "register_operand" "")
+            (match_operand:V2DI 2 "nonimmediate_operand" ""))
           (parallel [(const_int 1)
                      (const_int 3)])))]
   "TARGET_SSE2"
@@ -4189,11 +4189,11 @@
 })
 
 (define_expand "vec_interleave_lowv2di"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
+  [(set (match_operand:V2DI 0 "register_operand" "")
         (vec_select:V2DI
           (vec_concat:V4DI
-            (match_operand:V2DI 1 "register_operand" "0")
-            (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
+            (match_operand:V2DI 1 "register_operand" "")
+            (match_operand:V2DI 2 "nonimmediate_operand" ""))
           (parallel [(const_int 0)
                      (const_int 2)])))]
   "TARGET_SSE2"
@@ -5234,8 +5234,8 @@
 
 (define_expand "sse2_maskmovdqu"
   [(set (match_operand:V16QI 0 "memory_operand" "")
-       (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
-                      (match_operand:V16QI 2 "register_operand" "x")
+       (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
+                      (match_operand:V16QI 2 "register_operand" "")
                       (match_dup 0)]
                      UNSPEC_MASKMOV))]
   "TARGET_SSE2"
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