(set_attr "type" "fpu")])
;;; multiply-add
-(define_insn "maddsf4"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
- (match_operand:SF 2 "register_operand" "r"))
- (match_operand:SF 3 "register_operand" "r")))]
+(define_insn "fmasf4"
+ [(set (match_operand:SF 0 "register_operand" "=r")
+ (fma:SF (match_operand:SF 1 "register_operand" "r")
+ (match_operand:SF 2 "register_operand" "r")
+ (match_operand:SF 3 "register_operand" "r")))]
"TARGET_V850E2V3"
"maddf.s %2,%1,%3,%0"
[(set_attr "length" "4")
(set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
-
;;; multiply-subtract
-(define_insn "msubsf4"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
- (match_operand:SF 2 "register_operand" "r"))
- (match_operand:SF 3 "register_operand" "r")))]
+(define_insn "fmssf4"
+ [(set (match_operand:SF 0 "register_operand" "=r")
+ (fma:SF (match_operand:SF 1 "register_operand" "r")
+ (match_operand:SF 2 "register_operand" "r")
+ (neg:SF (match_operand:SF 3 "register_operand" "r"))))]
"TARGET_V850E2V3"
"msubf.s %2,%1,%3,%0"
[(set_attr "length" "4")
(set_attr "type" "fpu")])
;;; negative-multiply-add
-(define_insn "nmaddsf4"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
- (match_operand:SF 2 "register_operand" "r"))
- (match_operand:SF 3 "register_operand" "r"))))]
+(define_insn "fnmasf4"
+ [(set (match_operand:SF 0 "register_operand" "=r")
+ (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
+ (match_operand:SF 2 "register_operand" "r")
+ (match_operand:SF 3 "register_operand" "r")))]
"TARGET_V850E2V3"
"nmaddf.s %2,%1,%3,%0"
[(set_attr "length" "4")
(set_attr "type" "fpu")])
;; negative-multiply-subtract
-(define_insn "nmsubsf4"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
- (match_operand:SF 2 "register_operand" "r"))
- (match_operand:SF 3 "register_operand" "r"))))]
+(define_insn "fnmssf4"
+ [(set (match_operand:SF 0 "register_operand" "=r")
+ (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
+ (match_operand:SF 2 "register_operand" "r")
+ (neg:SF (match_operand:SF 3 "register_operand" "r"))))]
"TARGET_V850E2V3"
"nmsubf.s %2,%1,%3,%0"
[(set_attr "length" "4")