OSDN Git Service

(root) / pf3gnuchains / gcc-fork.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 625a3a6)
PR target/50945
authorebotcazou <ebotcazou@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 2 Nov 2011 20:07:26 +0000 (20:07 +0000)
committerebotcazou <ebotcazou@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 2 Nov 2011 20:07:26 +0000 (20:07 +0000)
* config/sparc/sparc.md (movsf_insn): Reindent constraints.
(movsf_insn_no_fpu): Likewise.
(movdf_insn_sp32): Likewise.
(movdf_insn_sp32_no_fpu): Likewise.
(movdf_insn_sp32_v9): Likewise.  Remove redundant GY constraint.
(movdf_insn_sp32_v9_no_fpu): Likewise.
(movdf_insn_sp64): Likewise.
(movdf_insn_sp64_no_fpu): Likewise.
(movtf_insn_sp32): Likewise.
(movtf_insn_sp32_no_fpu): Likewise.
(movtf_insn_sp64): Likewise.
(movtf_insn_sp64_hq): Likewise.
(movtf_insn_sp64_no_fpu): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_6-branch@180792 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog patch | blob | history
gcc/config/sparc/sparc.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2afead1..b76c103 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2011-11-02  Eric Botcazou  <ebotcazou@adacore.com>
+
+       PR target/50945
+       * config/sparc/sparc.md (movsf_insn): Reindent constraints.
+       (movsf_insn_no_fpu): Likewise.
+       (movdf_insn_sp32): Likewise.
+       (movdf_insn_sp32_no_fpu): Likewise.
+       (movdf_insn_sp32_v9): Likewise.  Remove redundant GY constraint.
+       (movdf_insn_sp32_v9_no_fpu): Likewise.
+       (movdf_insn_sp64): Likewise.
+       (movdf_insn_sp64_no_fpu): Likewise.
+       (movtf_insn_sp32): Likewise.
+       (movtf_insn_sp32_no_fpu): Likewise.
+       (movtf_insn_sp64): Likewise.
+       (movtf_insn_sp64_hq): Likewise.
+       (movtf_insn_sp64_no_fpu): Likewise.
+
 2011-11-02  Bernd Schmidt  <bernds@codesourcery.com>
 
        * cfgcleanup.c (try_head_merge_bb): If get_condition returns
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 6926f9e..bf37c37 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1813,8 +1813,8 @@
 })
 
 (define_insn "*movsf_insn"
-  [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f,*r,*r,*r,f,*r,m,m")
-       (match_operand:V32 1 "input_operand"        "GY,f,*rRY,Q,S,m,m,f,*rGY"))]
+  [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f,  *r,*r,*r,f,*r,m,   m")
+       (match_operand:V32 1 "input_operand"        "GY,f,*rRY, Q, S,m, m,f,*rGY"))]
   "TARGET_FPU
    && (register_operand (operands[0], <V32:MODE>mode)
        || register_or_zero_operand (operands[1], <V32:MODE>mode))"
@@ -1861,8 +1861,8 @@
 ;; when -mno-fpu.
 
 (define_insn "*movsf_insn_no_fpu"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,m")
-       (match_operand:SF 1 "input_operand"    "rR,Q,S,m,rG"))]
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r, m")
+       (match_operand:SF 1 "input_operand"        "rR,Q,S,m,rG"))]
   "! TARGET_FPU
    && (register_operand (operands[0], SFmode)
        || register_or_zero_operand (operands[1], SFmode))"
@@ -1948,8 +1948,8 @@
 
 ;; Be careful, fmovd does not exist when !v9.
 (define_insn "*movdf_insn_sp32"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,W,U,T,o,e,*r,o,e,o")
-       (match_operand:DF 1 "input_operand"    "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "= e,W,U,T,o,e,  *r, o,  e,o")
+       (match_operand:DF 1 "input_operand"        "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
   "TARGET_FPU
    && ! TARGET_V9
    && (register_operand (operands[0], DFmode)
@@ -1969,8 +1969,8 @@
   (set_attr "length" "*,*,*,*,2,2,2,2,2,2")])
 
 (define_insn "*movdf_insn_sp32_no_fpu"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
-       (match_operand:DF 1 "input_operand"    "T,U,G,ro,r"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o, r,o")
+       (match_operand:DF 1 "input_operand"        " T,U,G,ro,r"))]
   "! TARGET_FPU
    && ! TARGET_V9
    && (register_operand (operands[0], DFmode)
@@ -1986,8 +1986,8 @@
 
 ;; We have available v9 double floats but not 64-bit integer registers.
 (define_insn "*movdf_insn_sp32_v9"
-  [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,T,W,U,T,f,*r,o")
-        (match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roGYDF,*rGYf"))]
+  [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,  e, T,W,U,T,  f,   *r,    o")
+       (match_operand:V64 1 "input_operand"        "GY,e,W#F,GY,e,T,U,o#F,*roFD,*rGYf"))]
   "TARGET_FPU
    && TARGET_V9
    && ! TARGET_ARCH64
@@ -2009,8 +2009,8 @@
    (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
 
 (define_insn "*movdf_insn_sp32_v9_no_fpu"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
-       (match_operand:DF 1 "input_operand"    "T,U,G,ro,rG"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T, r, o")
+       (match_operand:DF 1 "input_operand"        " T,U,G,ro,rG"))]
   "! TARGET_FPU
    && TARGET_V9
    && ! TARGET_ARCH64
@@ -2027,8 +2027,8 @@
 
 ;; We have available both v9 double floats and 64-bit integer registers.
 (define_insn "*movdf_insn_sp64"
-  [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,W,*r,*r,m,*r")
-        (match_operand:V64 1 "input_operand"    "GY,e,W#F,e,*rGY,m,*rGY,DF"))]
+  [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,  e,W,  *r,*r,   m,*r")
+       (match_operand:V64 1 "input_operand"        "GY,e,W#F,e,*rGY, m,*rGY,FD"))]
   "TARGET_FPU
    && TARGET_ARCH64
    && (register_operand (operands[0], <V64:MODE>mode)
@@ -2047,8 +2047,8 @@
    (set_attr "fptype" "double,double,*,*,*,*,*,*")])
 
 (define_insn "*movdf_insn_sp64_no_fpu"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
-        (match_operand:DF 1 "input_operand"    "r,m,rG"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r, m")
+       (match_operand:DF 1 "input_operand"         "r,m,rG"))]
   "! TARGET_FPU
    && TARGET_ARCH64
    && (register_operand (operands[0], DFmode)
@@ -2288,8 +2288,8 @@
 })
 
 (define_insn "*movtf_insn_sp32"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,U,r")
-       (match_operand:TF 1 "input_operand"    "G,oe,GeUr,o,roG"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,   o,U,  r")
+       (match_operand:TF 1 "input_operand"        " G,oe,GeUr,o,roG"))]
   "TARGET_FPU
    && ! TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
@@ -2302,8 +2302,8 @@
 ;; when -mno-fpu.
 
 (define_insn "*movtf_insn_sp32_no_fpu"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
-       (match_operand:TF 1 "input_operand"    "G,o,U,roG,r"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,  r,o")
+       (match_operand:TF 1 "input_operand"        " G,o,U,roG,r"))]
   "! TARGET_FPU
    && ! TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
@@ -2312,8 +2312,8 @@
   [(set_attr "length" "4")])
 
 (define_insn "*movtf_insn_sp64"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,r")
-        (match_operand:TF 1 "input_operand"    "G,oe,Ger,roG"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,  o,  r")
+       (match_operand:TF 1 "input_operand"         "G,oe,Ger,roG"))]
   "TARGET_FPU
    && TARGET_ARCH64
    && ! TARGET_HARD_QUAD
@@ -2323,8 +2323,8 @@
   [(set_attr "length" "2")])
 
 (define_insn "*movtf_insn_sp64_hq"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m,o,r")
-        (match_operand:TF 1 "input_operand"    "G,e,m,e,rG,roG"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m, o,  r")
+       (match_operand:TF 1 "input_operand"         "G,e,m,e,rG,roG"))]
   "TARGET_FPU
    && TARGET_ARCH64
    && TARGET_HARD_QUAD
@@ -2341,8 +2341,8 @@
    (set_attr "length" "2,*,*,*,2,2")])
 
 (define_insn "*movtf_insn_sp64_no_fpu"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
-        (match_operand:TF 1 "input_operand"    "orG,rG"))]
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=  r, o")
+       (match_operand:TF 1 "input_operand"         "orG,rG"))]
   "! TARGET_FPU
    && TARGET_ARCH64
    && (register_operand (operands[0], TFmode)
About OSDN
Find Software
Develop Software
Help