+2004-06-15 Jerry Quinn <jlquinn@optonline.net>
+
+ * alias.c (record_set, record_base_value, canon_rtx, get_addr,
+ nonlocal_mentioned_p_1, init_alias_analysis): Use REG_P.
+ * bt-load.c (find_btr_reference, insn_sets_btr_p, note_btr_set):
+ Likewise.
+ * builtins.c (expand_builtin_setjmp, expand_builtin_apply,
+ expand_builtin_mathfn, expand_builtin_strlen, expand_builtin_memcmp,
+ expand_builtin_strcmp, expand_builtin_strncmp,
+ expand_builtin_frame_address): Likewise.
+ * caller-save.c (mark_set_regs, add_stored_regs, mark_referenced_regs,
+ insert_one_insn): Likewise.
+ * calls.c (prepare_call_address, precompute_register_parameters,
+ precompute_arguments, expand_call, emit_library_call_value_1): Likewise.
+ * cfganal.c (flow_active_insn_p): Likewise.
+ * combine.c (set_nonzero_bits_and_sign_copies, can_combine_p,
+ combinable_i3pat, try_combine, find_split_point, COMBINE_RTX_EQUAL_P,
+ subst, combine_simplify_rtx, simplify_if_then_else, simplify_set,
+ make_extraction, recog_for_combine, gen_lowpart_for_combine,
+ simplify_comparison, record_dead_and_set_regs_1,
+ record_dead_and_set_regs, record_promoted_value,
+ check_promoted_subreg, get_last_value_validate, get_last_value,
+ reg_dead_at_p_1, reg_bitfield_target_p, distribute_notes,
+ unmentioned_reg_p_1): Likewise.
+ * conflict.c (mark_reg): Likewise.
+ * cse.c (HASH, COST, COST_IN, approx_reg_cost_1, notreg_cost,
+ mention_regs, insert_regs, lookup, lookup_for_remove, insert,
+ merge_equiv_classes, flush_hash_table, invalidate,
+ remove_invalid_refs, remove_invalid_subreg_refs, rehash_using_reg,
+ invalidate_for_call, use_related_value, canon_hash, exp_equiv_p,
+ cse_rtx_varies_p, canon_reg, find_best_addr, fold_rtx, equiv_constant,
+ record_jump_cond, cse_insn, addr_affects_sp_p,
+ invalidate_from_clobbers, cse_process_notes, cse_around_loop,
+ cse_set_around_loop, count_reg_usage, set_live_p, cse_change_cc_mode,
+ cse_cc_succs, cse_condition_code_reg): Likewise.
+ * cselib.c (cselib_reg_set_mode, rtx_equal_for_cselib_p,
+ cselib_lookup, cselib_invalidate_regno, cselib_invalidate_rtx,
+ cselib_record_set, cselib_record_sets): Likewise.
+ * dbxout.c (dbxout_symbol_location, dbxout_parms, dbxout_reg_parms,
+ dbxout_block): Likewise.
+ * df.c (df_ref_record, df_def_record_1, df_uses_record): Likewise.
+ * dojump.c (do_jump): Likewise.
+ * dwarf2out.c (dwarf2out_frame_debug_expr, is_pseudo_reg,
+ is_based_loc, rtl_for_decl_location): Likewise.
+ * emit-rtl.c (set_reg_attrs_for_parm, set_decl_rtl,
+ set_decl_incoming_rtl, mark_user_reg): Likewise.
+ * explow.c (copy_all_regs, copy_all_regs, memory_address, force_reg,
+ copy_to_suggested_reg, allocate_dynamic_stack_space,
+ probe_stack_range, hard_function_value): Likewise.
+ * expmed.c (store_bit_field, store_fixed_bit_field,
+ store_split_bit_field, extract_bit_field, extract_fixed_bit_field,
+ extract_split_bit_field, expand_divmod, emit_store_flag_force):
+ Likewise.
+ * expr.c (convert_move, convert_modes,
+ block_move_libcall_safe_for_call_parm, emit_group_load, use_reg,
+ use_group_regs, emit_move_insn, emit_move_insn_1,
+ compress_float_constant, push_block, emit_single_push_insn,
+ emit_push_insn, get_subtarget, expand_assignment, store_expr,
+ store_constructor, store_field, force_operand, safe_from_p,
+ expand_expr_real_1, expand_increment, do_store_flag, do_tablejump):
+ Likewise.
+ * final.c (profile_function, final_scan_insn, alter_subreg,
+ get_mem_expr_from_op, output_asm_operand_names, output_operand,
+ only_leaf_regs_used, leaf_renumber_regs_insn): Likewise.
+ * flow.c (verify_wide_reg_1, mark_regs_live_at_end,
+ find_regno_partial, propagate_one_insn, init_propagate_block_info,
+ insn_dead_p, libcall_dead_p, mark_set_1, not_reg_cond,
+ attempt_auto_inc, find_auto_inc, mark_used_regs,
+ count_or_remove_death_notes_bb): Likewise.
+ * function.c (find_temp_slot_from_address, update_temp_slot_address,
+ preserve_temp_slots, put_var_into_stack, fixup_var_refs_insn,
+ fixup_var_refs_1, fixup_stack_1, optimize_bit_field, flush_addressof,
+ put_addressof_into_stack, purge_addressof_1, insns_for_mem_walk,
+ purge_single_hard_subreg_set, instantiate_decl,
+ instantiate_virtual_regs_1, aggregate_value_p, assign_parms,
+ promoted_input_arg, setjmp_vars_warning, setjmp_args_warning,
+ setjmp_protect, setjmp_protect_args, fix_lexical_addr,
+ expand_function_start, diddle_return_value, clobber_return_register,
+ expand_function_end, keep_stack_depressed, handle_epilogue_set,
+ update_epilogue_consts): Likewise.
+ * genemit.c (gen_exp, gen_insn): Likewise.
+ * genrecog.c (make_insn_sequence): Likewise.
+ * global.c (global_conflicts, expand_preferences, mark_reg_store,
+ mark_reg_conflicts, set_preference, reg_becomes_live,
+ build_insn_chain, mark_reg_change): Likewise.
+ * haifa_sched.c (CONST_BASED_ADDRESS_P, find_set_reg_weight):
+ Likewise.
+ * ifcvt.c (noce_try_abs, noce_get_condition, noce_process_if_block):
+ Likewise.
+ * integrate.c (copy_rtx_and_substitute, try_constants,
+ subst_constants, mark_stores, allocate_initial_values): Likewise.
+ * jump.c (reversed_comparison_code_parts, delete_prior_computation,
+ delete_computation, rtx_renumbered_equal_p, true_regnum,
+ reg_or_subregno): Likewise.
+ * lcm.c (reg_dies, reg_becomes_live): Likewise.
+ * local-alloc.c (validate_equiv_mem_from_store, validate_equiv_mem,
+ update_equiv_regs, no_equiv, block_alloc, combine_regs, reg_is_set,
+ wipe_dead_reg, no_conflict_p): Likewise.
+ * loop-iv.c (simple_reg_p, simple_set_p, kill_sets,
+ iv_get_reaching_def, iv_analyze_biv, altered_reg_used, mark_altered,
+ simple_rhs_p, simplify_using_assignment, implies_p): Likewise.
+ * loop.c (scan_loop, combine_movables, rtx_equal_for_loop_p,
+ move_movables, note_set_pseudo_multiple_uses, consec_sets_invariant_p,
+ find_single_use_in_loop, count_one_set, loop_bivs_init_find,
+ loop_givs_rescan, check_insn_for_bivs, check_insn_for_givs,
+ valid_initial_value_p, simplify_giv_expr, consec_sets_giv,
+ loop_regs_update, check_dbra_loop, maybe_eliminate_biv,
+ maybe_eliminate_biv_1, record_initial, update_reg_last_use,
+ canonicalize_condition, loop_regs_scan, load_mems, try_copy_prop,
+ try_swap_copy_prop): Likewise.
+ * optabs.c (expand_binop, expand_vector_binop, expand_vector_unop,
+ expand_abs, emit_no_conflict_block, emit_libcall_block, expand_float):
+ Likewise.
+ * postreload.c (reload_cse_simplify, reload_cse_simplify_set,
+ reload_cse_simplify_operands, reload_combine,
+ reload_combine_note_store, reload_combine_note_use,
+ reload_cse_move2add, move2add_note_store): Likewise.
+ * print-rtl.c (print_rtx): Likewise.
+ * ra-build.c (copy_insn_p, remember_move, init_one_web_common,
+ contains_pseudo, handle_asm_insn): Likewise.
+ * ra-debug.c (ra_print_rtx_object, dump_constraints,
+ dump_static_insn_cost): Likewise.
+ * ra-rewrite.c (slots_overlap_p, emit_colors,
+ remove_suspicious_death_notes): Likewise.
+ * recog.c (validate_replace_rtx_1, find_single_use_1, find_single_use,
+ register_operand, scratch_operand, nonmemory_operand,
+ constrain_operands): Likewise.
+ * reg-stack (check_asm_stack_operands, remove_regno_note,
+ emit_swap_insn, swap_rtx_condition, subst_stack_regs_pat,
+ subst_asm_stack_regs): Likewise.
+ * regclass.c (scan_one_insn, record_reg_classes, copy_cost,
+ record_address_regs, reg_scan_mark_refs): Likewise.
+ * regmove.c (discover_flags_reg, replacement_quality,
+ copy_src_to_dest, reg_is_remote_constant_p, regmove_optimize,
+ fixup_match_1): Likewise.
+ * regrename.c (note_sets, clear_dead_regs, build_def_use, kill_value,
+ kill_set_value, copyprop_hardreg_forward_1): Likewise.
+ * reload.c (MATCHES, push_secondary_reload, find_reusable_reload,
+ reload_inner_reg_of_subreg, can_reload_into, push_reload,
+ combine_reloads, find_dummy_reload, hard_reg_set_here_p,
+ operands_match_p, decompose, find_reloads, find_reloads_toplev,
+ find_reloads_address, subst_indexed_address, find_reloads_address_1,
+ find_reloads_subreg_address, find_replacement,
+ refers_to_regno_for_reload_p, reg_overlap_mentioned_for_reload_p,
+ refers_to_mem_for_reload_p, find_equiv_reg, regno_clobbered_p): Likewise.
+ * reload1.c (replace_pseudos_in, reload, calculate_needs_all_insns,
+ find_reg, delete_dead_insn, alter_reg, eliminate_regs,
+ elimination_effects, eliminate_regs_in_insn, scan_paradoxical_subregs,
+ forget_old_reloads_1, reload_reg_free_for_value_p, choose_reload_regs,
+ emit_input_reload_insns, emit_output_reload_insns, do_input_reload,
+ do_output_reload, emit_reload_insns, gen_reload,
+ delete_address_reloads_1, inc_for_reload): Likewise.
+ * reorg.c (update_reg_dead_notes, fix_reg_dead_note,
+ update_reg_unused_notes, fill_slots_from_thread): Likewise.
+ * resource.c (update_live_status, mark_referenced_resources,
+ mark_set_resources, mark_target_live_regs): Likewise.
+ * rtlanal.c (nonzero_address_p, get_jump_table_offset,
+ global_reg_mentioned_p_1, reg_mentioned_p, reg_referenced_p,
+ reg_set_p, set_noop_p, find_last_value, refers_to_regno_p,
+ note_stores, dead_or_set_p, dead_or_set_regno_p, find_regno_note,
+ find_reg_fusage, find_regno_fusage, replace_regs, regno_use_in,
+ parms_set, find_first_parameter_load, keep_with_call_p,
+ hoist_test_store, hoist_update_store, address_cost, nonzero_bits1,
+ num_sign_bit_copies1): Likewise.
+ * rtlhooks.c (gen_lowpart_general): Likewise.
+ * sched-deps.c (deps_may_trap_p, sched_analyze_1, sched_analyze_insn,
+ sched_analyze): Likewise.
+ * sched-rgn.c (check_live_1, update_live_1, sets_likely_spilled_1):
+ Likewise.
+ * sdbout.c (sdbout_symbol, sdbout_parms, sdbout_reg_parms): Likewise.
+ * simplify-rtx.c (simplify_replace_rtx, simplify_unary_operation,
+ simplify_binary_operation, simplify_const_relational_operation,
+ simplify_subreg): Likewise.
+ * stmt.c (decl_conflicts_with_clobbers_p, expand_asm_operands,
+ expand_end_stmt_expr, expand_return, expand_decl,
+ expand_anon_union_decl): Likewise.
+ * unroll.c (precondition_loop_p, calculate_giv_inc, copy_loop_body,
+ find_splittable_regs, find_splittable_givs, find_common_reg_term,
+ loop_iterations): Likewise.
+ * var-tracking.c (variable_union, variable_part_different_p,
+ variable_different_p, count_uses, add_uses, add_stores,
+ compute_bb_dataflow, set_variable_part, delete_variable_part,
+ emit_notes_in_bb, vt_get_decl_and_offset, vt_add_function_parameters):
+ Likewise.
+ * varasm.c (assemble_variable): Likewise.
+
2004-06-15 Chris Demetriou <cgd@broadcom.com>
* config/mips/linux.h (ASM_PREFERRED_EH_DATA_FORMAT): Remove
rtx src;
int n;
- if (GET_CODE (dest) != REG)
+ if (!REG_P (dest))
return;
regno = REGNO (dest);
if (regno >= VARRAY_SIZE (reg_base_value))
VARRAY_GROW (reg_base_value, max_reg_num ());
- if (GET_CODE (val) == REG)
+ if (REG_P (val))
{
VARRAY_RTX (reg_base_value, regno)
= REG_BASE_VALUE (val);
canon_rtx (rtx x)
{
/* Recursively look for equivalences. */
- if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
+ if (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
{
rtx t = get_reg_known_value (REGNO (x));
if (t == x)
if (CONSTANT_P (l->loc))
return l->loc;
for (l = v->locs; l; l = l->next)
- if (GET_CODE (l->loc) != REG && GET_CODE (l->loc) != MEM)
+ if (!REG_P (l->loc) && GET_CODE (l->loc) != MEM)
return l->loc;
if (v->locs)
return v->locs->loc;
switch (GET_CODE (x))
{
case SUBREG:
- if (GET_CODE (SUBREG_REG (x)) == REG)
+ if (REG_P (SUBREG_REG (x)))
{
/* Global registers are not local. */
if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
mentioned in the destination. */
if (GET_CODE (SET_DEST (x)) != CC0
&& GET_CODE (SET_DEST (x)) != PC
- && GET_CODE (SET_DEST (x)) != REG
+ && !REG_P (SET_DEST (x))
&& ! (GET_CODE (SET_DEST (x)) == SUBREG
- && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
+ && REG_P (SUBREG_REG (SET_DEST (x)))
&& (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
+ (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
== ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
set = single_set (insn);
if (set != 0
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER)
{
unsigned int regno = REGNO (SET_DEST (set));
}
else if (REG_N_SETS (regno) == 1
&& GET_CODE (src) == PLUS
- && GET_CODE (XEXP (src, 0)) == REG
+ && REG_P (XEXP (src, 0))
&& (t = get_reg_known_value (REGNO (XEXP (src, 0))))
&& GET_CODE (XEXP (src, 1)) == CONST_INT)
{
for (ui = 0; ui < maxreg; ui++)
{
rtx base = VARRAY_RTX (reg_base_value, ui);
- if (base && GET_CODE (base) == REG)
+ if (base && REG_P (base))
{
unsigned int base_regno = REGNO (base);
if (base_regno == ui) /* register set from itself */
if (px == preg)
return -1;
x = *px;
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
return 0;
regno = REGNO (x);
for (i = hard_regno_nregs[regno][GET_MODE (x)] - 1; i >= 0; i--)
if (GET_CODE (dest) == SUBREG)
dest = XEXP (dest, 0);
- if (GET_CODE (dest) == REG
+ if (REG_P (dest)
&& TEST_HARD_REG_BIT (all_btrs, REGNO (dest)))
{
if (btr_referenced_p (src, NULL))
defs_uses_info *info = data;
int regno, end_regno;
- if (GET_CODE (dest) != REG)
+ if (!REG_P (dest))
return;
regno = REGNO (dest);
end_regno = regno + hard_regno_nregs[regno][GET_MODE (dest)];
if (!validate_arglist (arglist, POINTER_TYPE, VOID_TYPE))
return NULL_RTX;
- if (target == 0 || GET_CODE (target) != REG
+ if (target == 0 || !REG_P (target)
|| REGNO (target) < FIRST_PSEUDO_REGISTER)
target = gen_reg_rtx (TYPE_MODE (integer_type_node));
rtx value = gen_reg_rtx (Pmode);
emit_move_insn (value, adjust_address (arguments, Pmode, size));
emit_move_insn (struct_value, value);
- if (GET_CODE (struct_value) == REG)
+ if (REG_P (struct_value))
use_reg (&call_fusage, struct_value);
size += GET_MODE_SIZE (Pmode);
}
rtx operand = XEXP (XEXP (XEXP (note, 0), 1), 0);
/* Check operand is a register with expected mode. */
if (operand
- && GET_CODE (operand) == REG
+ && REG_P (operand)
&& GET_MODE (operand) == mode)
{
/* Replace the REG_EQUAL note with a SQRT rtx. */
/* Make a place to write the result of the instruction. */
result = target;
if (! (result != 0
- && GET_CODE (result) == REG
+ && REG_P (result)
&& GET_MODE (result) == insn_mode
&& REGNO (result) >= FIRST_PSEUDO_REGISTER))
result = gen_reg_rtx (insn_mode);
/* Make a place to write the result of the instruction. */
result = target;
if (! (result != 0
- && GET_CODE (result) == REG && GET_MODE (result) == insn_mode
+ && REG_P (result) && GET_MODE (result) == insn_mode
&& REGNO (result) >= FIRST_PSEUDO_REGISTER))
result = gen_reg_rtx (insn_mode);
/* Make a place to write the result of the instruction. */
result = target;
if (! (result != 0
- && GET_CODE (result) == REG && GET_MODE (result) == insn_mode
+ && REG_P (result) && GET_MODE (result) == insn_mode
&& REGNO (result) >= FIRST_PSEUDO_REGISTER))
result = gen_reg_rtx (insn_mode);
/* Make a place to write the result of the instruction. */
result = target;
if (! (result != 0
- && GET_CODE (result) == REG && GET_MODE (result) == insn_mode
+ && REG_P (result) && GET_MODE (result) == insn_mode
&& REGNO (result) >= FIRST_PSEUDO_REGISTER))
result = gen_reg_rtx (insn_mode);
if (DECL_FUNCTION_CODE (fndecl) == BUILT_IN_FRAME_ADDRESS)
return tem;
- if (GET_CODE (tem) != REG
+ if (!REG_P (tem)
&& ! CONSTANT_P (tem))
tem = copy_to_mode_reg (Pmode, tem);
return tem;
if (GET_CODE (reg) == SUBREG)
{
rtx inner = SUBREG_REG (reg);
- if (GET_CODE (inner) != REG || REGNO (inner) >= FIRST_PSEUDO_REGISTER)
+ if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER)
return;
regno = subreg_hard_regno (reg, 1);
}
- else if (GET_CODE (reg) == REG
+ else if (REG_P (reg)
&& REGNO (reg) < FIRST_PSEUDO_REGISTER)
regno = REGNO (reg);
else
if (GET_CODE (setter) == CLOBBER)
return;
- if (GET_CODE (reg) == SUBREG && GET_CODE (SUBREG_REG (reg)) == REG)
+ if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
{
offset = subreg_regno_offset (REGNO (SUBREG_REG (reg)),
GET_MODE (SUBREG_REG (reg)),
reg = SUBREG_REG (reg);
}
- if (GET_CODE (reg) != REG || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
+ if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
return;
regno = REGNO (reg) + offset;
code = GET_CODE (x);
if ((code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
|| code == PC || code == CC0
- || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG
+ || (code == SUBREG && REG_P (SUBREG_REG (x))
&& REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
/* If we're setting only part of a multi-word register,
we shall mark it as referenced, because the words
rtx reg = XEXP (link, 0);
int regno, i;
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
abort ();
regno = REGNO (reg);
{
emit_move_insn (static_chain_rtx, static_chain_value);
- if (GET_CODE (static_chain_rtx) == REG)
+ if (REG_P (static_chain_rtx))
use_reg (call_fusage, static_chain_rtx);
}
register parameters. This is to avoid reload conflicts while
loading the parameters registers. */
- if ((! (GET_CODE (args[i].value) == REG
+ if ((! (REG_P (args[i].value)
|| (GET_CODE (args[i].value) == SUBREG
- && GET_CODE (SUBREG_REG (args[i].value)) == REG)))
+ && REG_P (SUBREG_REG (args[i].value)))))
&& args[i].mode != BLKmode
&& rtx_cost (args[i].value, SET) > COSTS_N_INSNS (1)
&& ((SMALL_REGISTER_CLASSES && *reg_parm_seen)
/* CSE will replace this only if it contains args[i].value
pseudo, so convert it down to the declared mode using
a SUBREG. */
- if (GET_CODE (args[i].value) == REG
+ if (REG_P (args[i].value)
&& GET_MODE_CLASS (args[i].mode) == MODE_INT)
{
args[i].initial_value
is not a REG, we must always copy it into a register.
If it is virtual_outgoing_args_rtx, we must copy it to another
register in some cases. */
- rtx temp = (GET_CODE (structure_value_addr) != REG
+ rtx temp = (!REG_P (structure_value_addr)
|| (ACCUMULATE_OUTGOING_ARGS
&& stack_arg_under_construction
&& structure_value_addr == virtual_outgoing_args_rtx)
force_operand (structure_value_addr,
NULL_RTX)));
- if (GET_CODE (struct_value) == REG)
+ if (REG_P (struct_value))
use_reg (&call_fusage, struct_value);
}
{
/* If we promoted this return value, make the proper SUBREG. TARGET
might be const0_rtx here, so be careful. */
- if (GET_CODE (target) == REG
+ if (REG_P (target)
&& TYPE_MODE (TREE_TYPE (exp)) != BLKmode
&& GET_MODE (target) != TYPE_MODE (TREE_TYPE (exp)))
{
nargs++;
/* Make sure it is a reasonable operand for a move or push insn. */
- if (GET_CODE (addr) != REG && GET_CODE (addr) != MEM
+ if (!REG_P (addr) && GET_CODE (addr) != MEM
&& ! (CONSTANT_P (addr) && LEGITIMATE_CONSTANT_P (addr)))
addr = force_operand (addr, NULL_RTX);
either emit_move_insn or emit_push_insn will do that. */
/* Make sure it is a reasonable operand for a move or push insn. */
- if (GET_CODE (val) != REG && GET_CODE (val) != MEM
+ if (!REG_P (val) && GET_CODE (val) != MEM
&& ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val)))
val = force_operand (val, NULL_RTX);
force_reg (Pmode,
force_operand (XEXP (mem_value, 0),
NULL_RTX)));
- if (GET_CODE (struct_value) == REG)
+ if (REG_P (struct_value))
use_reg (&call_fusage, struct_value);
}
function. If we allow it to be skipped, we introduce the
possibility for register livetime aborts. */
if (GET_CODE (PATTERN (insn)) == CLOBBER
- && GET_CODE (XEXP (PATTERN (insn), 0)) == REG
+ && REG_P (XEXP (PATTERN (insn), 0))
&& REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))
return true;
{
unsigned int num;
- if (GET_CODE (x) == REG
+ if (REG_P (x)
&& REGNO (x) >= FIRST_PSEUDO_REGISTER
/* If this register is undefined at the start of the file, we can't
say what its contents were. */
something to tell them apart, e.g. different modes. For
now, we forgo such complicated tests and simply disallow
combining of USES of pseudo registers with any other USE. */
- if (GET_CODE (XEXP (elt, 0)) == REG
+ if (REG_P (XEXP (elt, 0))
&& GET_CODE (PATTERN (i3)) == PARALLEL)
{
rtx i3pat = PATTERN (i3);
rtx i3elt = XVECEXP (i3pat, 0, i);
if (GET_CODE (i3elt) == USE
- && GET_CODE (XEXP (i3elt, 0)) == REG
+ && REG_P (XEXP (i3elt, 0))
&& (REGNO (XEXP (i3elt, 0)) == regno
? reg_set_between_p (XEXP (elt, 0),
PREV_INSN (insn), i3)
/* Don't eliminate a function call argument. */
|| (GET_CODE (i3) == CALL_INSN
&& (find_reg_fusage (i3, USE, dest)
- || (GET_CODE (dest) == REG
+ || (REG_P (dest)
&& REGNO (dest) < FIRST_PSEUDO_REGISTER
&& global_regs[REGNO (dest)])))
/* Don't substitute into an incremented register. */
return 0;
/* DEST must either be a REG or CC0. */
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
/* If register alignment is being enforced for multi-word items in all
cases except for parameters, it is possible to have a register copy
Also, on some machines we don't want to extend the life of a hard
register. */
- if (GET_CODE (src) == REG
+ if (REG_P (src)
&& ((REGNO (dest) < FIRST_PSEUDO_REGISTER
&& ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
/* Don't extend the life of a hard register unless it is
to be an explicit register variable, and was chosen for a reason. */
if (GET_CODE (src) == ASM_OPERANDS
- && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
+ && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
return 0;
/* If there are any volatile insns between INSN and I3, reject, because
function argument; the all_adjacent test in can_combine_p also
checks this; here, we do a more specific test for this case. */
- || (GET_CODE (inner_dest) == REG
+ || (REG_P (inner_dest)
&& REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
&& (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
GET_MODE (inner_dest))))
Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
STACK_POINTER_REGNUM, since these are always considered to be
live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
- if (pi3dest_killed && GET_CODE (dest) == REG
+ if (pi3dest_killed && REG_P (dest)
&& reg_referenced_p (dest, PATTERN (i3))
&& REGNO (dest) != FRAME_POINTER_REGNUM
#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
usage tests. */
if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
- && GET_CODE (SET_SRC (PATTERN (i3))) == REG
+ && REG_P (SET_SRC (PATTERN (i3)))
&& REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
&& find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
&& GET_CODE (PATTERN (i2)) == PARALLEL
&& (temp = single_set (i2)) != 0
&& (GET_CODE (SET_SRC (temp)) == CONST_INT
|| GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
- && GET_CODE (SET_DEST (temp)) == REG
+ && REG_P (SET_DEST (temp))
&& GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
&& GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
&& GET_CODE (PATTERN (i3)) == SET
&& GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
&& XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
&& GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
- && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
+ && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
&& rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
{
#if 0
if (!(GET_CODE (PATTERN (i3)) == SET
- && GET_CODE (SET_SRC (PATTERN (i3))) == REG
+ && REG_P (SET_SRC (PATTERN (i3)))
&& GET_CODE (SET_DEST (PATTERN (i3))) == MEM
&& (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
|| GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
rtx set1 = XVECEXP (newpat, 0, 1);
rtx note;
- if (((GET_CODE (SET_DEST (set1)) == REG
+ if (((REG_P (SET_DEST (set1))
&& find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
|| (GET_CODE (SET_DEST (set1)) == SUBREG
&& find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
}
- else if (((GET_CODE (SET_DEST (set0)) == REG
+ else if (((REG_P (SET_DEST (set0))
&& find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
|| (GET_CODE (SET_DEST (set0)) == SUBREG
&& find_reg_note (i3, REG_UNUSED,
we can change its mode. */
if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
&& GET_MODE (SET_DEST (newpat)) != VOIDmode
- && GET_CODE (i2dest) == REG
+ && REG_P (i2dest)
&& (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
|| (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
&& ! REG_USERVAR_P (i2dest))))
|| GET_CODE (new_i2_dest) == SUBREG)
new_i2_dest = XEXP (new_i2_dest, 0);
- if (GET_CODE (new_i3_dest) == REG
- && GET_CODE (new_i2_dest) == REG
+ if (REG_P (new_i3_dest)
+ && REG_P (new_i2_dest)
&& REGNO (new_i3_dest) == REGNO (new_i2_dest))
REG_N_SETS (REGNO (new_i2_dest))++;
}
are set between I2 and I3. */
if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
#ifdef HAVE_cc0
- && GET_CODE (i2dest) == REG
+ && REG_P (i2dest)
#endif
/* We need I2DEST in the proper mode. If it is a hard register
or the only use of a pseudo, we can change its mode. */
&& GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
&& GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
&& ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
- (GET_CODE (temp) == REG
+ (REG_P (temp)
&& reg_stat[REGNO (temp)].nonzero_bits != 0
&& GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
&& GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
!= GET_MODE_MASK (word_mode))))
&& ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
&& (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
- (GET_CODE (temp) == REG
+ (REG_P (temp)
&& reg_stat[REGNO (temp)].nonzero_bits != 0
&& GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
&& GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
if (REG_NOTE_KIND (note) == REG_UNUSED
&& ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
{
- if (GET_CODE (XEXP (note, 0)) == REG)
+ if (REG_P (XEXP (note, 0)))
REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
remove_note (undobuf.other_insn, note);
}
for (note = new_other_notes; note; note = XEXP (note, 1))
- if (GET_CODE (XEXP (note, 0)) == REG)
+ if (REG_P (XEXP (note, 0)))
REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
distribute_notes (new_other_notes, undobuf.other_insn,
{
for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
- && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
+ && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
&& SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
&& ! find_reg_note (i2, REG_UNUSED,
SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
if (newi2pat && new_i2_notes)
{
for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
- if (GET_CODE (XEXP (temp, 0)) == REG)
+ if (REG_P (XEXP (temp, 0)))
REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
if (new_i3_notes)
{
for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
- if (GET_CODE (XEXP (temp, 0)) == REG)
+ if (REG_P (XEXP (temp, 0)))
REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
if (i3dest_killed)
{
- if (GET_CODE (i3dest_killed) == REG)
+ if (REG_P (i3dest_killed))
REG_N_DEATHS (REGNO (i3dest_killed))++;
if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
if (i2dest_in_i2src)
{
- if (GET_CODE (i2dest) == REG)
+ if (REG_P (i2dest))
REG_N_DEATHS (REGNO (i2dest))++;
if (newi2pat && reg_set_p (i2dest, newi2pat))
if (i1dest_in_i1src)
{
- if (GET_CODE (i1dest) == REG)
+ if (REG_P (i1dest))
REG_N_DEATHS (REGNO (i1dest))++;
if (newi2pat && reg_set_p (i1dest, newi2pat))
distribute_links (i2links);
distribute_links (i1links);
- if (GET_CODE (i2dest) == REG)
+ if (REG_P (i2dest))
{
rtx link;
rtx i2_insn = 0, i2_val = 0, set;
}
}
- if (i1 && GET_CODE (i1dest) == REG)
+ if (i1 && REG_P (i1dest))
{
rtx link;
rtx i1_insn = 0, i1_val = 0, set;
be better. */
if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
- && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
+ && REG_P (XEXP (SET_SRC (x), 0))
&& (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
- && GET_CODE (SET_DEST (x)) == REG
+ && REG_P (SET_DEST (x))
&& (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
&& (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
&& XEXP (*split, 0) == SET_DEST (x)
#define COMBINE_RTX_EQUAL_P(X,Y) \
((X) == (Y) \
- || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
+ || (REG_P (X) && REG_P (Y) \
&& REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
delete the feeding insn, which is incorrect.
So force this insn not to match in this (rare) case. */
- if (! in_dest && code == REG && GET_CODE (from) == REG
+ if (! in_dest && code == REG && REG_P (from)
&& REGNO (x) == REGNO (from))
return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
{
rtx dest = SET_DEST (XVECEXP (x, 0, i));
- if (GET_CODE (dest) != REG
+ if (!REG_P (dest)
&& GET_CODE (dest) != CC0
&& GET_CODE (dest) != PC)
{
where we want to suppress replacing something inside a
SET_SRC are handled via the IN_DEST operand. */
if (code == SET
- && (GET_CODE (SET_DEST (x)) == REG
+ && (REG_P (SET_DEST (x))
|| GET_CODE (SET_DEST (x)) == CC0
|| GET_CODE (SET_DEST (x)) == PC))
fmt = "ie";
&& (code == SUBREG || code == STRICT_LOW_PART
|| code == ZERO_EXTRACT)
&& i == 0
- && GET_CODE (new) == REG)
+ && REG_P (new))
;
else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
#ifdef CANNOT_CHANGE_MODE_CLASS
if (code == SUBREG
- && GET_CODE (to) == REG
+ && REG_P (to)
&& REGNO (to) < FIRST_PSEUDO_REGISTER
&& REG_CANNOT_CHANGE_MODE_P (REGNO (to),
GET_MODE (to),
or a SUBREG of one since we'd be making the expression more
complex if it was just a register. */
- if (GET_CODE (temp) != REG
+ if (!REG_P (temp)
&& ! (GET_CODE (temp) == SUBREG
- && GET_CODE (SUBREG_REG (temp)) == REG)
+ && REG_P (SUBREG_REG (temp)))
&& (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
{
rtx temp1 = simplify_shift_const
the bitsize of the mode - 1. This allows simplification of
"a = (b & 8) == 0;" */
if (XEXP (x, 1) == constm1_rtx
- && GET_CODE (XEXP (x, 0)) != REG
+ && !REG_P (XEXP (x, 0))
&& ! (GET_CODE (XEXP (x, 0)) == SUBREG
- && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
+ && REG_P (SUBREG_REG (XEXP (x, 0))))
&& nonzero_bits (XEXP (x, 0), mode) == 1)
return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
simplify_shift_const (NULL_RTX, ASHIFT, mode,
return simplify_shift_const (x, code, mode, XEXP (x, 0),
INTVAL (XEXP (x, 1)));
- else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
+ else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
SUBST (XEXP (x, 1),
force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
((HOST_WIDE_INT) 1
if (comparison_p
&& ((false_code = combine_reversed_comparison_code (cond))
!= UNKNOWN)
- && GET_CODE (XEXP (cond, 0)) == REG)
+ && REG_P (XEXP (cond, 0)))
{
HOST_WIDE_INT nzb;
rtx from = XEXP (cond, 0);
< GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
#endif
#ifdef CANNOT_CHANGE_MODE_CLASS
- && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
+ && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
&& REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
GET_MODE (SUBREG_REG (src)),
GET_MODE (src)))
#endif
- && (GET_CODE (dest) == REG
+ && (REG_P (dest)
|| (GET_CODE (dest) == SUBREG
- && GET_CODE (SUBREG_REG (dest)) == REG)))
+ && REG_P (SUBREG_REG (dest)))))
{
SUBST (SET_DEST (x),
gen_lowpart (GET_MODE (SUBREG_REG (src)),
&& ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
&& GET_CODE (inner) != MEM
&& (! in_dest
- || (GET_CODE (inner) == REG
+ || (REG_P (inner)
&& have_insn_for (STRICT_LOW_PART, tmode))))
|| (GET_CODE (inner) == MEM && pos_rtx == 0
&& (pos
new = adjust_address_nv (inner, tmode, offset);
}
- else if (GET_CODE (inner) == REG)
+ else if (REG_P (inner))
{
if (tmode != inner_mode)
{
for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
i < XVECLEN (newpat, 0); i++)
{
- if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
+ if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
&& ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
return -1;
notes = gen_rtx_EXPR_LIST (REG_UNUSED,
#ifdef CANNOT_CHANGE_MODE_CLASS
if (result != 0
&& GET_CODE (result) == SUBREG
- && GET_CODE (SUBREG_REG (result)) == REG
+ && REG_P (SUBREG_REG (result))
&& REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
* MAX_MACHINE_MODE
{
/* For paradoxical subregs, allow case 1 as above. Case 3 isn't
implemented. */
- if (GET_CODE (SUBREG_REG (op0)) == REG)
+ if (REG_P (SUBREG_REG (op0)))
{
op0 = SUBREG_REG (op0);
op1 = gen_lowpart (GET_MODE (op0), op1);
if (GET_CODE (dest) == SUBREG)
dest = SUBREG_REG (dest);
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
/* If we are setting the whole register, we know its value. Otherwise
show that we don't know the value. We can handle SUBREG in
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
{
if (REG_NOTE_KIND (link) == REG_DEAD
- && GET_CODE (XEXP (link, 0)) == REG)
+ && REG_P (XEXP (link, 0)))
{
unsigned int regno = REGNO (XEXP (link, 0));
unsigned int endregno
insn = XEXP (links, 0);
set = single_set (insn);
- if (! set || GET_CODE (SET_DEST (set)) != REG
+ if (! set || !REG_P (SET_DEST (set))
|| REGNO (SET_DEST (set)) != regno
|| GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
{
reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
}
- if (GET_CODE (SET_SRC (set)) == REG)
+ if (REG_P (SET_SRC (set)))
{
regno = REGNO (SET_SRC (set));
links = LOG_LINKS (insn);
check_promoted_subreg (rtx insn, rtx x)
{
if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
- && GET_CODE (SUBREG_REG (x)) == REG)
+ && REG_P (SUBREG_REG (x)))
record_promoted_value (insn, x);
else
{
int len = GET_RTX_LENGTH (GET_CODE (x));
int i;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
unsigned int regno = REGNO (x);
unsigned int endregno
&& (value = get_last_value (SUBREG_REG (x))) != 0)
return gen_lowpart (GET_MODE (x), value);
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
return 0;
regno = REGNO (x);
{
unsigned int regno, endregno;
- if (GET_CODE (dest) != REG)
+ if (!REG_P (dest))
return;
regno = REGNO (dest);
if (GET_CODE (target) == SUBREG)
target = SUBREG_REG (target);
- if (GET_CODE (target) != REG)
+ if (!REG_P (target))
return 0;
tregno = REGNO (target), regno = REGNO (x);
/* If this NOTE references a pseudo register, ensure it references
the latest copy of that register. */
- if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
+ if (XEXP (note, 0) && REG_P (XEXP (note, 0))
&& REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
if (from_insn != i3)
break;
- if (! (GET_CODE (XEXP (note, 0)) == REG
+ if (! (REG_P (XEXP (note, 0))
? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
: find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
place = i3;
now dies here, so we must put a REG_DEAD note here unless there
is one already. */
else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
- && ! (GET_CODE (XEXP (note, 0)) == REG
+ && ! (REG_P (XEXP (note, 0))
? find_regno_note (i3, REG_DEAD,
REGNO (XEXP (note, 0)))
: find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
}
else if ((REG_NOTE_KIND (note) == REG_DEAD
|| REG_NOTE_KIND (note) == REG_UNUSED)
- && GET_CODE (XEXP (note, 0)) == REG)
+ && REG_P (XEXP (note, 0)))
REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
if (place2)
{
if ((REG_NOTE_KIND (note) == REG_DEAD
|| REG_NOTE_KIND (note) == REG_UNUSED)
- && GET_CODE (XEXP (note, 0)) == REG)
+ && REG_P (XEXP (note, 0)))
REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
rtx x = *loc;
if (x != NULL_RTX
- && (GET_CODE (x) == REG || GET_CODE (x) == MEM)
+ && (REG_P (x) || GET_CODE (x) == MEM)
&& ! reg_mentioned_p (x, (rtx) expr))
return 1;
return 0;
reg = SUBREG_REG (reg);
/* We're only interested in regs. */
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
return;
SET_REGNO_REG_SET (set, REGNO (reg));
register (hard registers may require `do_not_record' to be set). */
#define HASH(X, M) \
- ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER \
+ ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER \
? (((unsigned) REG << 7) + (unsigned) REG_QTY (REGNO (X))) \
: canon_hash (X, M)) & HASH_MASK)
|| ((N) < FIRST_PSEUDO_REGISTER \
&& FIXED_REGNO_P (N) && REGNO_REG_CLASS (N) != NO_REGS))
-#define COST(X) (GET_CODE (X) == REG ? 0 : notreg_cost (X, SET))
-#define COST_IN(X,OUTER) (GET_CODE (X) == REG ? 0 : notreg_cost (X, OUTER))
+#define COST(X) (REG_P (X) ? 0 : notreg_cost (X, SET))
+#define COST_IN(X,OUTER) (REG_P (X) ? 0 : notreg_cost (X, OUTER))
/* Get the info associated with register N. */
rtx x = *xp;
int *cost_p = data;
- if (x && GET_CODE (x) == REG)
+ if (x && REG_P (x))
{
unsigned int regno = REGNO (x);
notreg_cost (rtx x, enum rtx_code outer)
{
return ((GET_CODE (x) == SUBREG
- && GET_CODE (SUBREG_REG (x)) == REG
+ && REG_P (SUBREG_REG (x))
&& GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
&& GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
&& (GET_MODE_SIZE (GET_MODE (x))
/* If this is a SUBREG, we don't want to discard other SUBREGs of the same
pseudo if they don't use overlapping words. We handle only pseudos
here for simplicity. */
- if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG
+ if (code == SUBREG && REG_P (SUBREG_REG (x))
&& REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
{
unsigned int i = REGNO (SUBREG_REG (x));
if (code == COMPARE || COMPARISON_P (x))
{
- if (GET_CODE (XEXP (x, 0)) == REG
+ if (REG_P (XEXP (x, 0))
&& ! REGNO_QTY_VALID_P (REGNO (XEXP (x, 0))))
if (insert_regs (XEXP (x, 0), NULL, 0))
{
changed = 1;
}
- if (GET_CODE (XEXP (x, 1)) == REG
+ if (REG_P (XEXP (x, 1))
&& ! REGNO_QTY_VALID_P (REGNO (XEXP (x, 1))))
if (insert_regs (XEXP (x, 1), NULL, 0))
{
static int
insert_regs (rtx x, struct table_elt *classp, int modified)
{
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
unsigned int regno = REGNO (x);
int qty_valid;
for (classp = classp->first_same_value;
classp != 0;
classp = classp->next_same_value)
- if (GET_CODE (classp->exp) == REG
+ if (REG_P (classp->exp)
&& GET_MODE (classp->exp) == GET_MODE (x))
{
make_regs_eqv (regno, REGNO (classp->exp));
not be accessible because its hash code will have changed. So assign
a quantity number now. */
- else if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == REG
+ else if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))
&& ! REGNO_QTY_VALID_P (REGNO (SUBREG_REG (x))))
{
insert_regs (SUBREG_REG (x), NULL, 0);
struct table_elt *p;
for (p = table[hash]; p; p = p->next_same_hash)
- if (mode == p->mode && ((x == p->exp && GET_CODE (x) == REG)
- || exp_equiv_p (x, p->exp, GET_CODE (x) != REG, 0)))
+ if (mode == p->mode && ((x == p->exp && REG_P (x))
+ || exp_equiv_p (x, p->exp, !REG_P (x), 0)))
return p;
return 0;
{
struct table_elt *p;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
unsigned int regno = REGNO (x);
/* Don't check the machine mode when comparing registers;
invalidating (REG:SI 0) also invalidates (REG:DF 0). */
for (p = table[hash]; p; p = p->next_same_hash)
- if (GET_CODE (p->exp) == REG
+ if (REG_P (p->exp)
&& REGNO (p->exp) == regno)
return p;
}
/* If X is a register and we haven't made a quantity for it,
something is wrong. */
- if (GET_CODE (x) == REG && ! REGNO_QTY_VALID_P (REGNO (x)))
+ if (REG_P (x) && ! REGNO_QTY_VALID_P (REGNO (x)))
abort ();
/* If X is a hard register, show it is being put in the table. */
- if (GET_CODE (x) == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
+ if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
{
unsigned int regno = REGNO (x);
unsigned int endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
elt->is_const = (CONSTANT_P (x)
/* GNU C++ takes advantage of this for `this'
(and other const values). */
- || (GET_CODE (x) == REG
+ || (REG_P (x)
&& RTX_UNCHANGING_P (x)
&& REGNO (x) >= FIRST_PSEUDO_REGISTER)
|| fixed_base_plus_p (x));
update the qtys `const_insn' to show that `this_insn' is the latest
insn making that quantity equivalent to the constant. */
- if (elt->is_const && classp && GET_CODE (classp->exp) == REG
- && GET_CODE (x) != REG)
+ if (elt->is_const && classp && REG_P (classp->exp)
+ && !REG_P (x))
{
int exp_q = REG_QTY (REGNO (classp->exp));
struct qty_table_elem *exp_ent = &qty_table[exp_q];
exp_ent->const_insn = this_insn;
}
- else if (GET_CODE (x) == REG
+ else if (REG_P (x)
&& classp
&& ! qty_table[REG_QTY (REGNO (x))].const_rtx
&& ! elt->is_const)
for (p = classp; p != 0; p = p->next_same_value)
{
- if (p->is_const && GET_CODE (p->exp) != REG)
+ if (p->is_const && !REG_P (p->exp))
{
int x_q = REG_QTY (REGNO (x));
struct qty_table_elem *x_ent = &qty_table[x_q];
}
}
- else if (GET_CODE (x) == REG
+ else if (REG_P (x)
&& qty_table[REG_QTY (REGNO (x))].const_rtx
&& GET_MODE (x) == qty_table[REG_QTY (REGNO (x))].mode)
qty_table[REG_QTY (REGNO (x))].const_insn = this_insn;
/* Remove old entry, make a new one in CLASS1's class.
Don't do this for invalid entries as we cannot find their
hash code (it also isn't necessary). */
- if (GET_CODE (exp) == REG || exp_equiv_p (exp, exp, 1, 0))
+ if (REG_P (exp) || exp_equiv_p (exp, exp, 1, 0))
{
hash_arg_in_memory = 0;
hash = HASH (exp, mode);
- if (GET_CODE (exp) == REG)
+ if (REG_P (exp))
delete_reg_equiv (REGNO (exp));
remove_from_table (elt, hash);
{
/* Note that invalidate can remove elements
after P in the current hash chain. */
- if (GET_CODE (p->exp) == REG)
+ if (REG_P (p->exp))
invalidate (p->exp, p->mode);
else
remove_from_table (p, i);
{
next = p->next_same_hash;
- if (GET_CODE (p->exp) != REG
+ if (!REG_P (p->exp)
|| REGNO (p->exp) >= FIRST_PSEUDO_REGISTER)
continue;
for (p = table[i]; p; p = next)
{
next = p->next_same_hash;
- if (GET_CODE (p->exp) != REG
+ if (!REG_P (p->exp)
&& refers_to_regno_p (regno, regno + 1, p->exp, (rtx *) 0))
remove_from_table (p, i);
}
rtx exp = p->exp;
next = p->next_same_hash;
- if (GET_CODE (exp) != REG
+ if (!REG_P (exp)
&& (GET_CODE (exp) != SUBREG
- || GET_CODE (SUBREG_REG (exp)) != REG
+ || !REG_P (SUBREG_REG (exp))
|| REGNO (SUBREG_REG (exp)) != regno
|| (((SUBREG_BYTE (exp)
+ (GET_MODE_SIZE (GET_MODE (exp)) - 1)) >= offset)
/* If X is not a register or if the register is known not to be in any
valid entries in the table, we have no work to do. */
- if (GET_CODE (x) != REG
+ if (!REG_P (x)
|| REG_IN_TABLE (REGNO (x)) < 0
|| REG_IN_TABLE (REGNO (x)) != REG_TICK (REGNO (x)))
return;
for (p = table[i]; p; p = next)
{
next = p->next_same_hash;
- if (GET_CODE (p->exp) != REG && reg_mentioned_p (x, p->exp)
+ if (!REG_P (p->exp) && reg_mentioned_p (x, p->exp)
&& exp_equiv_p (p->exp, p->exp, 1, 0)
&& i != (hash = safe_hash (p->exp, p->mode) & HASH_MASK))
{
{
next = p->next_same_hash;
- if (GET_CODE (p->exp) != REG
+ if (!REG_P (p->exp)
|| REGNO (p->exp) >= FIRST_PSEUDO_REGISTER)
continue;
q = 0;
else
for (q = p->first_same_value; q; q = q->next_same_value)
- if (GET_CODE (q->exp) == REG)
+ if (REG_P (q->exp))
break;
if (q)
want to have to forget unrelated subregs when one subreg changes. */
case SUBREG:
{
- if (GET_CODE (SUBREG_REG (x)) == REG)
+ if (REG_P (SUBREG_REG (x)))
{
hash += (((unsigned) SUBREG << 7)
+ REGNO (SUBREG_REG (x))
/* If X is a constant and Y is a register or vice versa, they may be
equivalent. We only have to validate if Y is a register. */
- if (CONSTANT_P (x) && GET_CODE (y) == REG
+ if (CONSTANT_P (x) && REG_P (y)
&& REGNO_QTY_VALID_P (REGNO (y)))
{
int y_q = REG_QTY (REGNO (y));
mode because if X is equivalent to a constant in some mode, it
doesn't vary in any mode. */
- if (GET_CODE (x) == REG
+ if (REG_P (x)
&& REGNO_QTY_VALID_P (REGNO (x)))
{
int x_q = REG_QTY (REGNO (x));
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 1)) == CONST_INT
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& REGNO_QTY_VALID_P (REGNO (XEXP (x, 0))))
{
int x0_q = REG_QTY (REGNO (XEXP (x, 0)));
load fp minus a constant into a register, then a MEM which is the
sum of the two `constant' registers. */
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
- && GET_CODE (XEXP (x, 1)) == REG
+ && REG_P (XEXP (x, 0))
+ && REG_P (XEXP (x, 1))
&& REGNO_QTY_VALID_P (REGNO (XEXP (x, 0)))
&& REGNO_QTY_VALID_P (REGNO (XEXP (x, 1))))
{
/* If replacing pseudo with hard reg or vice versa, ensure the
insn remains valid. Likewise if the insn has MATCH_DUPs. */
if (insn != 0 && new != 0
- && GET_CODE (new) == REG && GET_CODE (XEXP (x, i)) == REG
+ && REG_P (new) && REG_P (XEXP (x, i))
&& (((REGNO (new) < FIRST_PSEUDO_REGISTER)
!= (REGNO (XEXP (x, i)) < FIRST_PSEUDO_REGISTER))
|| (insn_code = recog_memoized (insn)) < 0
no easy way to unshare the MEM. In addition, looking up all stack
addresses is costly. */
if ((GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& GET_CODE (XEXP (addr, 1)) == CONST_INT
&& (regno = REGNO (XEXP (addr, 0)),
regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM
|| regno == ARG_POINTER_REGNUM))
- || (GET_CODE (addr) == REG
+ || (REG_P (addr)
&& (regno = REGNO (addr), regno == FRAME_POINTER_REGNUM
|| regno == HARD_FRAME_POINTER_REGNUM
|| regno == ARG_POINTER_REGNUM))
sometimes simplify the expression. Many simplifications
will not be valid, but some, usually applying the associative rule, will
be valid and produce better code. */
- if (GET_CODE (addr) != REG)
+ if (!REG_P (addr))
{
rtx folded = fold_rtx (copy_rtx (addr), NULL_RTX);
int addr_folded_cost = address_cost (folded, mode);
for (p = elt->first_same_value; p; p = p->next_same_value)
if (! p->flag)
{
- if ((GET_CODE (p->exp) == REG
+ if ((REG_P (p->exp)
|| exp_equiv_p (p->exp, p->exp, 1, 0))
&& ((exp_cost = address_cost (p->exp, mode)) < best_addr_cost
|| (exp_cost == best_addr_cost
if (flag_expensive_optimizations
&& ARITHMETIC_P (*loc)
- && GET_CODE (XEXP (*loc, 0)) == REG)
+ && REG_P (XEXP (*loc, 0)))
{
rtx op1 = XEXP (*loc, 1);
p && count < 32;
p = p->next_same_value, count++)
if (! p->flag
- && (GET_CODE (p->exp) == REG
+ && (REG_P (p->exp)
|| exp_equiv_p (p->exp, p->exp, 1, 0)))
{
rtx new = simplify_gen_binary (GET_CODE (*loc), Pmode,
return new;
}
- if (GET_CODE (folded_arg0) == REG
+ if (REG_P (folded_arg0)
&& GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (folded_arg0)))
{
struct table_elt *elt;
{
rtx op0 = SUBREG_REG (XEXP (elt->exp, 0));
- if (GET_CODE (op0) != REG && ! CONSTANT_P (op0))
+ if (!REG_P (op0) && ! CONSTANT_P (op0))
op0 = fold_rtx (op0, NULL_RTX);
op0 = equiv_constant (op0);
rtx op0 = gen_lowpart_common (mode, XEXP (elt->exp, 0));
rtx op1 = gen_lowpart_common (mode, XEXP (elt->exp, 1));
- if (op0 && GET_CODE (op0) != REG && ! CONSTANT_P (op0))
+ if (op0 && !REG_P (op0) && ! CONSTANT_P (op0))
op0 = fold_rtx (op0, NULL_RTX);
if (op0)
op0 = equiv_constant (op0);
- if (op1 && GET_CODE (op1) != REG && ! CONSTANT_P (op1))
+ if (op1 && !REG_P (op1) && ! CONSTANT_P (op1))
op1 = fold_rtx (op1, NULL_RTX);
if (op1)
rtx base = 0;
HOST_WIDE_INT offset = 0;
- if (GET_CODE (addr) == REG
+ if (REG_P (addr)
&& REGNO_QTY_VALID_P (REGNO (addr)))
{
int addr_q = REG_QTY (REGNO (addr));
struct qty_table_elem *arg_ent = &qty_table[arg_q];
if (arg_ent->const_rtx != NULL_RTX
- && GET_CODE (arg_ent->const_rtx) != REG
+ && !REG_P (arg_ent->const_rtx)
&& GET_CODE (arg_ent->const_rtx) != PLUS)
const_arg
= gen_lowpart (GET_MODE (arg),
/* See if the two operands are the same. */
if (folded_arg0 == folded_arg1
- || (GET_CODE (folded_arg0) == REG
- && GET_CODE (folded_arg1) == REG
+ || (REG_P (folded_arg0)
+ && REG_P (folded_arg1)
&& (REG_QTY (REGNO (folded_arg0))
== REG_QTY (REGNO (folded_arg1))))
|| ((p0 = lookup (folded_arg0,
/* If FOLDED_ARG0 is a register, see if the comparison we are
doing now is either the same as we did before or the reverse
(we only check the reverse if not floating-point). */
- else if (GET_CODE (folded_arg0) == REG)
+ else if (REG_P (folded_arg0))
{
int qty = REG_QTY (REGNO (folded_arg0));
|| (const_arg1
&& rtx_equal_p (ent->comparison_const,
const_arg1))
- || (GET_CODE (folded_arg1) == REG
+ || (REG_P (folded_arg1)
&& (REG_QTY (REGNO (folded_arg1)) == ent->comparison_qty))))
return (comparison_dominates_p (ent->comparison_code, code)
? true_rtx : false_rtx);
manner and hope the Sun compilers get it correct. */
&& INTVAL (const_arg1) !=
((HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))
- && GET_CODE (folded_arg1) == REG)
+ && REG_P (folded_arg1))
{
rtx new_const = GEN_INT (-INTVAL (const_arg1));
struct table_elt *p
if (p)
for (p = p->first_same_value; p; p = p->next_same_value)
- if (GET_CODE (p->exp) == REG)
+ if (REG_P (p->exp))
return simplify_gen_binary (MINUS, mode, folded_arg0,
canon_reg (p->exp, NULL_RTX));
}
Note that the similar optimization done by combine.c only works
if the intermediate operation's result has only one reference. */
- if (GET_CODE (folded_arg0) == REG
+ if (REG_P (folded_arg0)
&& const_arg1 && GET_CODE (const_arg1) == CONST_INT)
{
int is_shift
static rtx
equiv_constant (rtx x)
{
- if (GET_CODE (x) == REG
+ if (REG_P (x)
&& REGNO_QTY_VALID_P (REGNO (x)))
{
int x_q = REG_QTY (REGNO (x));
register, or if OP1 is neither a register or constant, we can't
do anything. */
- if (GET_CODE (op1) != REG)
+ if (!REG_P (op1))
op1 = equiv_constant (op1);
if ((reversed_nonequality && FLOAT_MODE_P (mode))
- || GET_CODE (op0) != REG || op1 == 0)
+ || !REG_P (op0) || op1 == 0)
return;
/* Put OP0 in the hash table if it isn't already. This gives it a
ent = &qty_table[qty];
ent->comparison_code = code;
- if (GET_CODE (op1) == REG)
+ if (REG_P (op1))
{
/* Look it up again--in case op0 and op1 are the same. */
op1_elt = lookup (op1, op1_hash, mode);
{
rtx clobbered = XEXP (y, 0);
- if (GET_CODE (clobbered) == REG
+ if (REG_P (clobbered)
|| GET_CODE (clobbered) == SUBREG)
invalidate (clobbered, VOIDmode);
else if (GET_CODE (clobbered) == STRICT_LOW_PART
canon_reg (XEXP (y, 0), NULL_RTX);
}
else if (GET_CODE (y) == USE
- && ! (GET_CODE (XEXP (y, 0)) == REG
+ && ! (REG_P (XEXP (y, 0))
&& REGNO (XEXP (y, 0)) < FIRST_PSEUDO_REGISTER))
canon_reg (y, NULL_RTX);
else if (GET_CODE (y) == CALL)
/* Canonicalize a USE of a pseudo register or memory location. */
else if (GET_CODE (x) == USE
- && ! (GET_CODE (XEXP (x, 0)) == REG
+ && ! (REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER))
canon_reg (XEXP (x, 0), NULL_RTX);
else if (GET_CODE (x) == CALL)
int insn_code;
sets[i].orig_src = src;
- if ((GET_CODE (new) == REG && GET_CODE (src) == REG
+ if ((REG_P (new) && REG_P (src)
&& ((REGNO (new) < FIRST_PSEUDO_REGISTER)
!= (REGNO (src) < FIRST_PSEUDO_REGISTER)))
|| (insn_code = recog_memoized (insn)) < 0
if (GET_CODE (src) == MEM
&& find_reg_note (insn, REG_EQUIV, NULL_RTX) != 0
- && GET_CODE (dest) == REG
+ && REG_P (dest)
&& REGNO (dest) >= FIRST_PSEUDO_REGISTER)
sets[i].src_volatile = 1;
for (const_elt = const_elt->first_same_value;
const_elt; const_elt = const_elt->next_same_value)
- if (GET_CODE (const_elt->exp) == REG)
+ if (REG_P (const_elt->exp))
{
src_related = gen_lowpart (mode,
const_elt->exp);
for (larger_elt = larger_elt->first_same_value;
larger_elt; larger_elt = larger_elt->next_same_value)
- if (GET_CODE (larger_elt->exp) == REG)
+ if (REG_P (larger_elt->exp))
{
src_related
= gen_lowpart (mode, larger_elt->exp);
for (larger_elt = larger_elt->first_same_value;
larger_elt; larger_elt = larger_elt->next_same_value)
- if (GET_CODE (larger_elt->exp) == REG)
+ if (REG_P (larger_elt->exp))
{
src_related = gen_lowpart (mode,
larger_elt->exp);
rtx trial;
/* Skip invalid entries. */
- while (elt && GET_CODE (elt->exp) != REG
+ while (elt && !REG_P (elt->exp)
&& ! exp_equiv_p (elt->exp, elt->exp, 1, 0))
elt = elt->next_same_value;
need to make the same substitution in any notes attached
to the RETVAL insn. */
if (libcall_insn
- && (GET_CODE (sets[i].orig_src) == REG
+ && (REG_P (sets[i].orig_src)
|| GET_CODE (sets[i].orig_src) == SUBREG
|| GET_CODE (sets[i].orig_src) == MEM))
{
with the head of the class. If we do not do this, we will have
both registers live over a portion of the basic block. This way,
their lifetimes will likely abut instead of overlapping. */
- if (GET_CODE (dest) == REG
+ if (REG_P (dest)
&& REGNO_QTY_VALID_P (REGNO (dest)))
{
int dest_q = REG_QTY (REGNO (dest));
if (dest_ent->mode == GET_MODE (dest)
&& dest_ent->first_reg != REGNO (dest)
- && GET_CODE (src) == REG && REGNO (src) == REGNO (dest)
+ && REG_P (src) && REGNO (src) == REGNO (dest)
/* Don't do this if the original insn had a hard reg as
SET_SRC or SET_DEST. */
- && (GET_CODE (sets[i].src) != REG
+ && (!REG_P (sets[i].src)
|| REGNO (sets[i].src) >= FIRST_PSEUDO_REGISTER)
- && (GET_CODE (dest) != REG || REGNO (dest) >= FIRST_PSEUDO_REGISTER))
+ && (!REG_P (dest) || REGNO (dest) >= FIRST_PSEUDO_REGISTER))
/* We can't call canon_reg here because it won't do anything if
SRC is a hard register. */
{
which can be created for a reference to a compile time computable
entry in a jump table. */
- if (n_sets == 1 && src_const && GET_CODE (dest) == REG
- && GET_CODE (src_const) != REG
+ if (n_sets == 1 && src_const && REG_P (dest)
+ && !REG_P (src_const)
&& ! (GET_CODE (src_const) == CONST
&& GET_CODE (XEXP (src_const, 0)) == MINUS
&& GET_CODE (XEXP (XEXP (src_const, 0), 0)) == LABEL_REF
else if (do_not_record)
{
- if (GET_CODE (dest) == REG || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || GET_CODE (dest) == SUBREG)
invalidate (dest, VOIDmode);
else if (GET_CODE (dest) == MEM)
{
previous quantity's chain.
Needed for memory if this is a nonvarying address, unless
we have just done an invalidate_memory that covers even those. */
- if (GET_CODE (dest) == REG || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || GET_CODE (dest) == SUBREG)
invalidate (dest, VOIDmode);
else if (GET_CODE (dest) == MEM)
{
{
rtx x = SET_DEST (sets[i].rtl);
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
mention_regs (x);
else
{
if (GET_CODE (dest) == STRICT_LOW_PART)
dest = SUBREG_REG (XEXP (dest, 0));
- if (GET_CODE (dest) == REG || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || GET_CODE (dest) == SUBREG)
/* Registers must also be inserted into chains for quantities. */
if (insert_regs (dest, sets[i].src_elt, 1))
{
int byte = 0;
/* Ignore invalid entries. */
- if (GET_CODE (elt->exp) != REG
+ if (!REG_P (elt->exp)
&& ! exp_equiv_p (elt->exp, elt->exp, 1, 0))
continue;
classp = src_elt->first_same_value;
/* Ignore invalid entries. */
while (classp
- && GET_CODE (classp->exp) != REG
+ && !REG_P (classp->exp)
&& ! exp_equiv_p (classp->exp, classp->exp, 1, 0))
classp = classp->next_same_value;
}
register to be set in the middle of a libcall, and we then get bad code
if the libcall is deleted. */
- if (n_sets == 1 && sets[0].rtl && GET_CODE (SET_DEST (sets[0].rtl)) == REG
+ if (n_sets == 1 && sets[0].rtl && REG_P (SET_DEST (sets[0].rtl))
&& NEXT_INSN (PREV_INSN (insn)) == insn
- && GET_CODE (SET_SRC (sets[0].rtl)) == REG
+ && REG_P (SET_SRC (sets[0].rtl))
&& REGNO (SET_SRC (sets[0].rtl)) >= FIRST_PSEUDO_REGISTER
&& REGNO_QTY_VALID_P (REGNO (SET_SRC (sets[0].rtl))))
{
addr_affects_sp_p (rtx addr)
{
if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
{
if (REG_TICK (STACK_POINTER_REGNUM) >= 0)
rtx ref = XEXP (x, 0);
if (ref)
{
- if (GET_CODE (ref) == REG || GET_CODE (ref) == SUBREG
+ if (REG_P (ref) || GET_CODE (ref) == SUBREG
|| GET_CODE (ref) == MEM)
invalidate (ref, VOIDmode);
else if (GET_CODE (ref) == STRICT_LOW_PART
if (GET_CODE (y) == CLOBBER)
{
rtx ref = XEXP (y, 0);
- if (GET_CODE (ref) == REG || GET_CODE (ref) == SUBREG
+ if (REG_P (ref) || GET_CODE (ref) == SUBREG
|| GET_CODE (ref) == MEM)
invalidate (ref, VOIDmode);
else if (GET_CODE (ref) == STRICT_LOW_PART
if (ent->const_rtx != NULL_RTX
&& (CONSTANT_P (ent->const_rtx)
- || GET_CODE (ent->const_rtx) == REG))
+ || REG_P (ent->const_rtx)))
{
rtx new = gen_lowpart (GET_MODE (x), ent->const_rtx);
if (new)
for (p = last_jump_equiv_class->first_same_value; p;
p = p->next_same_value)
{
- if (GET_CODE (p->exp) == MEM || GET_CODE (p->exp) == REG
+ if (MEM_P (p->exp) || REG_P (p->exp)
|| (GET_CODE (p->exp) == SUBREG
- && GET_CODE (SUBREG_REG (p->exp)) == REG))
+ && REG_P (SUBREG_REG (p->exp))))
invalidate (p->exp, VOIDmode);
else if (GET_CODE (p->exp) == STRICT_LOW_PART
|| GET_CODE (p->exp) == ZERO_EXTRACT)
are setting PC or CC0 or whose SET_SRC is already a register. */
if (GET_CODE (x) == SET
&& GET_CODE (SET_DEST (x)) != PC && GET_CODE (SET_DEST (x)) != CC0
- && GET_CODE (SET_SRC (x)) != REG)
+ && !REG_P (SET_SRC (x)))
{
src_elt = lookup (SET_SRC (x),
HASH (SET_SRC (x), GET_MODE (SET_DEST (x))),
if (src_elt)
for (src_elt = src_elt->first_same_value; src_elt;
src_elt = src_elt->next_same_value)
- if (GET_CODE (src_elt->exp) == REG && REG_LOOP_TEST_P (src_elt->exp)
+ if (REG_P (src_elt->exp) && REG_LOOP_TEST_P (src_elt->exp)
&& COST (src_elt->exp) < COST (SET_SRC (x)))
{
rtx p, set;
&& GET_CODE (p) != CODE_LABEL;
p = prev_nonnote_insn (p))
if ((set = single_set (p)) != 0
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& GET_MODE (SET_DEST (set)) == src_elt->mode
&& rtx_equal_p (SET_SRC (set), SET_SRC (x)))
{
/* See comment on similar code in cse_insn for explanation of these
tests. */
- if (GET_CODE (SET_DEST (x)) == REG || GET_CODE (SET_DEST (x)) == SUBREG
+ if (REG_P (SET_DEST (x)) || GET_CODE (SET_DEST (x)) == SUBREG
|| GET_CODE (SET_DEST (x)) == MEM)
invalidate (SET_DEST (x), VOIDmode);
else if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
case SET:
/* Unless we are setting a REG, count everything in SET_DEST. */
- if (GET_CODE (SET_DEST (x)) != REG)
+ if (!REG_P (SET_DEST (x)))
count_reg_usage (SET_DEST (x), counts, incr);
count_reg_usage (SET_SRC (x), counts, incr);
return;
|| !reg_referenced_p (cc0_rtx, PATTERN (tem))))
return false;
#endif
- else if (GET_CODE (SET_DEST (set)) != REG
+ else if (!REG_P (SET_DEST (set))
|| REGNO (SET_DEST (set)) < FIRST_PSEUDO_REGISTER
|| counts[REGNO (SET_DEST (set))] != 0
|| side_effects_p (SET_SRC (set))
rtx newreg = (rtx) data;
if (*loc
- && GET_CODE (*loc) == REG
+ && REG_P (*loc)
&& REGNO (*loc) == REGNO (newreg)
&& GET_MODE (*loc) != GET_MODE (newreg))
{
/* Check whether INSN sets CC_REG to CC_SRC. */
set = single_set (insn);
if (set
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) == REGNO (cc_reg))
{
bool found;
continue;
set = single_set (insn);
if (set
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) == REGNO (cc_reg))
{
cc_src_insn = insn;
enum machine_mode
cselib_reg_set_mode (rtx x)
{
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
return GET_MODE (x);
if (REG_VALUES (REGNO (x)) == NULL
const char *fmt;
int i;
- if (GET_CODE (x) == REG || GET_CODE (x) == MEM)
+ if (REG_P (x) || MEM_P (x))
{
cselib_val *e = cselib_lookup (x, GET_MODE (x), 0);
x = e->u.val_rtx;
}
- if (GET_CODE (y) == REG || GET_CODE (y) == MEM)
+ if (REG_P (y) || MEM_P (y))
{
cselib_val *e = cselib_lookup (y, GET_MODE (y), 0);
rtx t = l->loc;
/* Avoid infinite recursion. */
- if (GET_CODE (t) == REG || GET_CODE (t) == MEM)
+ if (REG_P (t) || GET_CODE (t) == MEM)
continue;
else if (rtx_equal_for_cselib_p (t, y))
return 1;
{
rtx t = l->loc;
- if (GET_CODE (t) == REG || GET_CODE (t) == MEM)
+ if (REG_P (t) || GET_CODE (t) == MEM)
continue;
else if (rtx_equal_for_cselib_p (x, t))
return 1;
if (GET_CODE (x) == VALUE)
return CSELIB_VAL_PTR (x);
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
struct elt_list *l;
unsigned int i = REGNO (x);
{
rtx x = (*p)->loc;
- if (GET_CODE (x) == REG && REGNO (x) == i)
+ if (REG_P (x) && REGNO (x) == i)
{
unchain_one_elt_loc_list (p);
break;
|| GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG)
dest = XEXP (dest, 0);
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
cselib_invalidate_regno (REGNO (dest), GET_MODE (dest));
else if (GET_CODE (dest) == MEM)
cselib_invalidate_mem (dest);
static void
cselib_record_set (rtx dest, cselib_val *src_elt, cselib_val *dest_addr_elt)
{
- int dreg = GET_CODE (dest) == REG ? (int) REGNO (dest) : -1;
+ int dreg = REG_P (dest) ? (int) REGNO (dest) : -1;
if (src_elt == 0 || side_effects_p (dest))
return;
sets[i].dest = dest = XEXP (dest, 0);
/* We don't know how to record anything but REG or MEM. */
- if (GET_CODE (dest) == REG
+ if (REG_P (dest)
|| (GET_CODE (dest) == MEM && cselib_record_memory))
{
rtx src = sets[i].src;
for (i = 0; i < n_sets; i++)
{
rtx dest = sets[i].dest;
- if (GET_CODE (dest) == REG || GET_CODE (dest) == MEM)
+ if (REG_P (dest) || GET_CODE (dest) == MEM)
{
int j;
for (j = i + 1; j < n_sets; j++)
for (i = 0; i < n_sets; i++)
{
rtx dest = sets[i].dest;
- if (GET_CODE (dest) == REG
+ if (REG_P (dest)
|| (GET_CODE (dest) == MEM && cselib_record_memory))
cselib_record_set (dest, sets[i].src_elt, sets[i].dest_addr_elt);
}
while (GET_CODE (value) == SUBREG)
value = SUBREG_REG (value);
- if (GET_CODE (value) == REG)
+ if (REG_P (value))
{
if (REGNO (value) >= FIRST_PSEUDO_REGISTER)
return 0;
}
home = alter_subreg (&home);
}
- if (GET_CODE (home) == REG)
+ if (REG_P (home))
{
regno = REGNO (home);
if (regno >= FIRST_PSEUDO_REGISTER)
}
else if (GET_CODE (home) == MEM
&& (GET_CODE (XEXP (home, 0)) == MEM
- || (GET_CODE (XEXP (home, 0)) == REG
+ || (REG_P (XEXP (home, 0))
&& REGNO (XEXP (home, 0)) != HARD_FRAME_POINTER_REGNUM
&& REGNO (XEXP (home, 0)) != STACK_POINTER_REGNUM
#if ARG_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
so all we can do is output the variable as a pointer.
If it's not a parameter, ignore it. */
{
- if (GET_CODE (XEXP (home, 0)) == REG)
+ if (REG_P (XEXP (home, 0)))
{
letter = 'r';
current_sym_code = N_RSYM;
TREE_TYPE (type) = TREE_TYPE (decl);
}
else if (GET_CODE (home) == MEM
- && GET_CODE (XEXP (home, 0)) == REG)
+ && REG_P (XEXP (home, 0)))
{
current_sym_code = N_LSYM;
current_sym_value = DEBUGGER_AUTO_OFFSET (XEXP (home, 0));
current_sym_value = DEBUGGER_ARG_OFFSET (current_sym_value, addr);
dbxout_finish_symbol (parms);
}
- else if (GET_CODE (DECL_RTL (parms)) == REG)
+ else if (REG_P (DECL_RTL (parms)))
{
rtx best_rtl;
char regparm_letter;
dbxout_finish_symbol (parms);
}
else if (GET_CODE (DECL_RTL (parms)) == MEM
- && GET_CODE (XEXP (DECL_RTL (parms), 0)) == REG
+ && REG_P (XEXP (DECL_RTL (parms), 0))
&& REGNO (XEXP (DECL_RTL (parms), 0)) != HARD_FRAME_POINTER_REGNUM
&& REGNO (XEXP (DECL_RTL (parms), 0)) != STACK_POINTER_REGNUM
#if ARG_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
const char *const decl_name = (DECL_NAME (parms)
? IDENTIFIER_POINTER (DECL_NAME (parms))
: "(anon)");
- if (GET_CODE (XEXP (XEXP (DECL_RTL (parms), 0), 0)) == REG)
+ if (REG_P (XEXP (XEXP (DECL_RTL (parms), 0), 0)))
current_sym_value = 0;
else
current_sym_value
in which case we want the value of that CONST_INT,
or (MEM (REG ...)),
in which case we use a value of zero. */
- if (GET_CODE (XEXP (DECL_RTL (parms), 0)) == REG)
+ if (REG_P (XEXP (DECL_RTL (parms), 0)))
current_sym_value = 0;
else
current_sym_value
/* Report parms that live in registers during the function
but were passed in memory. */
- if (GET_CODE (DECL_RTL (parms)) == REG
+ if (REG_P (DECL_RTL (parms))
&& REGNO (DECL_RTL (parms)) < FIRST_PSEUDO_REGISTER)
dbxout_symbol_location (parms, TREE_TYPE (parms),
0, DECL_RTL (parms));
{
unsigned int regno;
- if (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG)
+ if (!REG_P (reg) && GET_CODE (reg) != SUBREG)
abort ();
/* For the reg allocator we are interested in some SUBREG rtx's, but not
flags |= DF_REF_READ_WRITE;
}
- if (GET_CODE (dst) == REG
- || (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG))
+ if (REG_P (dst)
+ || (GET_CODE (dst) == SUBREG && REG_P (SUBREG_REG (dst))))
df_ref_record (df, dst, loc, insn, DF_REF_REG_DEF, flags);
}
/* While we're here, optimize this case. */
/* In case the SUBREG is not of a REG, do not optimize. */
- if (GET_CODE (SUBREG_REG (x)) != REG)
+ if (!REG_P (SUBREG_REG (x)))
{
loc = &SUBREG_REG (x);
df_uses_record (df, loc, ref_type, bb, insn, flags);
{
/* Compare promoted variables in their promoted mode. */
if (SUBREG_PROMOTED_VAR_P (temp)
- && GET_CODE (XEXP (temp, 0)) == REG)
+ && REG_P (XEXP (temp, 0)))
temp = XEXP (temp, 0);
else
temp = copy_to_reg (temp);
if (! frame_pointer_needed)
abort ();
- if (GET_CODE (XEXP (src, 0)) == REG
+ if (REG_P (XEXP (src, 0))
&& (unsigned) REGNO (XEXP (src, 0)) == cfa.reg
&& GET_CODE (XEXP (src, 1)) == CONST_INT)
{
abort ();
/* Rule 4 */
- if (GET_CODE (XEXP (src, 0)) == REG
+ if (REG_P (XEXP (src, 0))
&& REGNO (XEXP (src, 0)) == cfa.reg
&& GET_CODE (XEXP (src, 1)) == CONST_INT)
{
}
/* Rule 5 */
- else if (GET_CODE (XEXP (src, 0)) == REG
+ else if (REG_P (XEXP (src, 0))
&& REGNO (XEXP (src, 0)) == cfa_temp.reg
&& XEXP (src, 1) == stack_pointer_rtx)
{
/* Rule 7 */
case IOR:
- if (GET_CODE (XEXP (src, 0)) != REG
+ if (!REG_P (XEXP (src, 0))
|| (unsigned) REGNO (XEXP (src, 0)) != cfa_temp.reg
|| GET_CODE (XEXP (src, 1)) != CONST_INT)
abort ();
break;
case MEM:
- if (GET_CODE (src) != REG)
+ if (!REG_P (src))
abort ();
/* Saving a register to the stack. Make sure dest is relative to the
calculate the CFA. */
rtx x = XEXP (dest, 0);
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
x = XEXP (x, 0);
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
abort ();
cfa.reg = REGNO (x);
static inline int
is_pseudo_reg (rtx rtl)
{
- return ((GET_CODE (rtl) == REG && REGNO (rtl) >= FIRST_PSEUDO_REGISTER)
+ return ((REG_P (rtl) && REGNO (rtl) >= FIRST_PSEUDO_REGISTER)
|| (GET_CODE (rtl) == SUBREG
&& REGNO (SUBREG_REG (rtl)) >= FIRST_PSEUDO_REGISTER));
}
is_based_loc (rtx rtl)
{
return (GET_CODE (rtl) == PLUS
- && ((GET_CODE (XEXP (rtl, 0)) == REG
+ && ((REG_P (XEXP (rtl, 0))
&& REGNO (XEXP (rtl, 0)) < FIRST_PSEUDO_REGISTER
&& GET_CODE (XEXP (rtl, 1)) == CONST_INT)));
}
&& (CONSTANT_P (rtl)
|| (GET_CODE (rtl) == MEM
&& CONSTANT_P (XEXP (rtl, 0)))
- || (GET_CODE (rtl) == REG
+ || (REG_P (rtl)
&& TREE_CODE (decl) == VAR_DECL
&& TREE_STATIC (decl))))
{
/* Not passed in memory. */
&& GET_CODE (DECL_INCOMING_RTL (decl)) != MEM
/* Not passed by invisible reference. */
- && (GET_CODE (XEXP (rtl, 0)) != REG
+ && (!REG_P (XEXP (rtl, 0))
|| REGNO (XEXP (rtl, 0)) == HARD_FRAME_POINTER_REGNUM
|| REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM
#if ARG_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
void
set_reg_attrs_for_parm (rtx parm_rtx, rtx mem)
{
- if (GET_CODE (parm_rtx) == REG)
+ if (REG_P (parm_rtx))
set_reg_attrs_from_mem (parm_rtx, mem);
else if (GET_CODE (parm_rtx) == PARALLEL)
{
for (; i < XVECLEN (parm_rtx, 0); i++)
{
rtx x = XVECEXP (parm_rtx, 0, i);
- if (GET_CODE (XEXP (x, 0)) == REG)
+ if (REG_P (XEXP (x, 0)))
REG_ATTRS (XEXP (x, 0))
= get_reg_attrs (MEM_EXPR (mem),
INTVAL (XEXP (x, 1)));
if (!x)
return;
/* For register, we maintain the reverse information too. */
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
REG_ATTRS (x) = get_reg_attrs (t, 0);
else if (GET_CODE (x) == SUBREG)
REG_ATTRS (SUBREG_REG (x))
if (!x)
return;
/* For register, we maintain the reverse information too. */
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
REG_ATTRS (x) = get_reg_attrs (t, 0);
else if (GET_CODE (x) == SUBREG)
REG_ATTRS (SUBREG_REG (x))
REG_USERVAR_P (XEXP (reg, 0)) = 1;
REG_USERVAR_P (XEXP (reg, 1)) = 1;
}
- else if (GET_CODE (reg) == REG)
+ else if (REG_P (reg))
REG_USERVAR_P (reg) = 1;
else
abort ();
/* This is where we attempt to catch illegal subregs
created by the compiler. */
if (GET_CODE (x) != SUBREG
- || GET_CODE (reg) != REG)
+ || !REG_P (reg))
abort ();
base_regno = REGNO (reg);
if (base_regno >= FIRST_PSEUDO_REGISTER)
else if (msize < xsize)
return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0));
}
- else if (GET_CODE (x) == SUBREG || GET_CODE (x) == REG
+ else if (GET_CODE (x) == SUBREG || REG_P (x)
|| GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR
|| GET_CODE (x) == CONST_DOUBLE || GET_CODE (x) == CONST_INT)
return simplify_gen_subreg (mode, x, innermode, offset);
{
/* If this is a register which can not be accessed by words, copy it
to a pseudo register. */
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
op = copy_to_reg (op);
else
op = force_reg (mode, op);
done:
if ((GET_CODE (other) == MEM
&& ! CONSTANT_P (x)
- && GET_CODE (x) != REG
+ && !REG_P (x)
&& GET_CODE (x) != SUBREG)
- || (GET_CODE (other) == REG
+ || (REG_P (other)
&& (REGNO (other) < FIRST_PSEUDO_REGISTER
|| reg_mentioned_p (other, x))))
{
rtx
copy_all_regs (rtx x)
{
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
if (REGNO (x) != FRAME_POINTER_REGNUM
#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
On attempting to put this in an insn we will call protect_from_queue
which will turn it into a REG, which is valid. */
else if (GET_CODE (x) == QUEUED
- && GET_CODE (QUEUED_VAR (x)) == REG)
+ && REG_P (QUEUED_VAR (x)))
;
/* We get better cse by rejecting indirect addressing at this stage.
are visible. But not if cse won't be done! */
else
{
- if (! cse_not_expected && GET_CODE (x) != REG)
+ if (! cse_not_expected && !REG_P (x))
x = break_out_memory_refs (x);
/* At this point, any valid address is accepted. */
/* If we have a register that's an invalid address,
it must be a hard reg of the wrong class. Copy it to a pseudo. */
- else if (GET_CODE (x) == REG)
+ else if (REG_P (x))
x = copy_to_reg (x);
/* Last resort: copy the value to a register, since
win2:
x = oldx;
win:
- if (flag_force_addr && ! cse_not_expected && GET_CODE (x) != REG
+ if (flag_force_addr && ! cse_not_expected && !REG_P (x)
/* Don't copy an addr via a reg if it is one of our stack slots. */
&& ! (GET_CODE (x) == PLUS
&& (XEXP (x, 0) == virtual_stack_vars_rtx
a reg as a pointer if we have REG or REG + CONST_INT. */
if (oldx == x)
return x;
- else if (GET_CODE (x) == REG)
+ else if (REG_P (x))
mark_reg_pointer (x, BITS_PER_UNIT);
else if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& GET_CODE (XEXP (x, 1)) == CONST_INT)
mark_reg_pointer (XEXP (x, 0), BITS_PER_UNIT);
{
rtx temp, insn, set;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
return x;
if (general_operand (x, mode))
else
{
temp = force_operand (x, NULL_RTX);
- if (GET_CODE (temp) == REG)
+ if (REG_P (temp))
insn = get_last_insn ();
else
{
{
rtx temp;
- if (target && GET_CODE (target) == REG)
+ if (target && REG_P (target))
temp = target;
else
temp = gen_reg_rtx (mode);
probe_stack_range (STACK_CHECK_MAX_FRAME_SIZE + STACK_CHECK_PROTECT, size);
/* Don't use a TARGET that isn't a pseudo or is the wrong mode. */
- if (target == 0 || GET_CODE (target) != REG
+ if (target == 0 || !REG_P (target)
|| REGNO (target) < FIRST_PSEUDO_REGISTER
|| GET_MODE (target) != Pmode)
target = gen_reg_rtx (Pmode);
rtx end_lab = gen_label_rtx ();
rtx temp;
- if (GET_CODE (test_addr) != REG
+ if (!REG_P (test_addr)
|| REGNO (test_addr) < FIRST_PSEUDO_REGISTER)
test_addr = force_reg (Pmode, test_addr);
#endif
val = FUNCTION_VALUE (valtype, func);
- if (GET_CODE (val) == REG
+ if (REG_P (val)
&& GET_MODE (val) == BLKmode)
{
unsigned HOST_WIDE_INT bytes = int_size_in_bytes (valtype);
subregs results in Severe Tire Damage. */
abort ();
}
- if (GET_CODE (op0) == REG)
+ if (REG_P (op0))
op0 = gen_rtx_SUBREG (fieldmode, op0, byte_offset);
else
op0 = adjust_address (op0, fieldmode, offset);
int icode = movstrict_optab->handlers[fieldmode].insn_code;
/* Get appropriate low part of the value being stored. */
- if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
+ if (GET_CODE (value) == CONST_INT || REG_P (value))
value = gen_lowpart (fieldmode, value);
else if (!(GET_CODE (value) == SYMBOL_REF
|| GET_CODE (value) == LABEL_REF
if (offset != 0
|| GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
{
- if (GET_CODE (op0) != REG)
+ if (!REG_P (op0))
{
/* Since this is a destination (lvalue), we can't copy it to a
pseudo. We can trivially remove a SUBREG that does not
&& !(bitsize == 1 && GET_CODE (value) == CONST_INT)
/* Ensure insv's size is wide enough for this field. */
&& (GET_MODE_BITSIZE (op_mode) >= bitsize)
- && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
+ && ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
&& (bitsize + bitpos > GET_MODE_BITSIZE (op_mode))))
{
int xbitpos = bitpos;
/* We can't just change the mode, because this might clobber op0,
and we will need the original value of op0 if insv fails. */
xop0 = gen_rtx_SUBREG (maxmode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
- if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
+ if (REG_P (xop0) && GET_MODE (xop0) != maxmode)
xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
/* On big-endian machines, we count bits from the most significant.
and a field split across two bytes.
Such cases are not supposed to be able to occur. */
- if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || GET_CODE (op0) == SUBREG)
{
if (offset != 0)
abort ();
if (GET_MODE (value) != mode)
{
- if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
+ if ((REG_P (value) || GET_CODE (value) == SUBREG)
&& GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
value = gen_lowpart (mode, value);
else
/* Now clear the chosen bits in OP0,
except that if VALUE is -1 we need not bother. */
- subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
+ subtarget = (REG_P (op0) || ! flag_force_mem) ? op0 : 0;
if (! all_one)
{
/* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
much at a time. */
- if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || GET_CODE (op0) == SUBREG)
unit = BITS_PER_WORD;
else
unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
GET_MODE (SUBREG_REG (op0)));
offset = 0;
}
- else if (GET_CODE (op0) == REG)
+ else if (REG_P (op0))
{
word = operand_subword_force (op0, offset, GET_MODE (op0));
offset = 0;
op0 = SUBREG_REG (op0);
}
- if (GET_CODE (op0) == REG
+ if (REG_P (op0)
&& mode == GET_MODE (op0)
&& bitnum == 0
&& bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
subregs results in Severe Tire Damage. */
goto no_subreg_mode_swap;
}
- if (GET_CODE (op0) == REG)
+ if (REG_P (op0))
op0 = gen_rtx_SUBREG (mode1, op0, byte_offset);
else
op0 = adjust_address (op0, mode1, offset);
unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
unsigned int i;
- if (target == 0 || GET_CODE (target) != REG)
+ if (target == 0 || !REG_P (target))
target = gen_reg_rtx (mode);
/* Indicate for flow that the entire target reg is being set. */
if (offset != 0
|| GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
{
- if (GET_CODE (op0) != REG)
+ if (!REG_P (op0))
op0 = copy_to_reg (op0);
op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
op0, (offset * UNITS_PER_WORD));
{
if (HAVE_extzv
&& (GET_MODE_BITSIZE (extzv_mode) >= bitsize)
- && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
+ && ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
&& (bitsize + bitpos > GET_MODE_BITSIZE (extzv_mode))))
{
unsigned HOST_WIDE_INT xbitpos = bitpos, xoffset = offset;
SImode). to make it acceptable to the format of extzv. */
if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
goto extzv_loses;
- if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
+ if (REG_P (xop0) && GET_MODE (xop0) != maxmode)
xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
/* On big-endian machines, we count bits from the most significant.
if (GET_MODE (xtarget) != maxmode)
{
- if (GET_CODE (xtarget) == REG)
+ if (REG_P (xtarget))
{
int wider = (GET_MODE_SIZE (maxmode)
> GET_MODE_SIZE (GET_MODE (xtarget)));
{
if (HAVE_extv
&& (GET_MODE_BITSIZE (extv_mode) >= bitsize)
- && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
+ && ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
&& (bitsize + bitpos > GET_MODE_BITSIZE (extv_mode))))
{
int xbitpos = bitpos, xoffset = offset;
SImode) to make it acceptable to the format of extv. */
if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
goto extv_loses;
- if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
+ if (REG_P (xop0) && GET_MODE (xop0) != maxmode)
xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
/* On big-endian machines, we count bits from the most significant.
if (GET_MODE (xtarget) != maxmode)
{
- if (GET_CODE (xtarget) == REG)
+ if (REG_P (xtarget))
{
int wider = (GET_MODE_SIZE (maxmode)
> GET_MODE_SIZE (GET_MODE (xtarget)));
unsigned int total_bits = BITS_PER_WORD;
enum machine_mode mode;
- if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
+ if (GET_CODE (op0) == SUBREG || REG_P (op0))
{
/* Special treatment for a bit field split across two registers. */
if (bitsize + bitpos > BITS_PER_WORD)
tree amount = build_int_2 (bitpos, 0);
/* Maybe propagate the target for the shift. */
/* But not if we will return it--could confuse integrate.c. */
- rtx subtarget = (target != 0 && GET_CODE (target) == REG ? target : 0);
+ rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
if (tmode != mode) subtarget = 0;
op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
}
tree amount
= build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
/* Maybe propagate the target for the shift. */
- rtx subtarget = (target != 0 && GET_CODE (target) == REG ? target : 0);
+ rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
}
/* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
much at a time. */
- if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || GET_CODE (op0) == SUBREG)
unit = BITS_PER_WORD;
else
unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
GET_MODE (SUBREG_REG (op0)));
offset = 0;
}
- else if (GET_CODE (op0) == REG)
+ else if (REG_P (op0))
{
word = operand_subword_force (op0, offset, GET_MODE (op0));
offset = 0;
if (rem_flag)
{
remainder
- = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
+ = REG_P (target) ? target : gen_reg_rtx (compute_mode);
quotient = gen_reg_rtx (compute_mode);
}
else
{
quotient
- = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
+ = REG_P (target) ? target : gen_reg_rtx (compute_mode);
remainder = gen_reg_rtx (compute_mode);
}
if (rem_flag)
{
- remainder = (GET_CODE (target) == REG
+ remainder = (REG_P (target)
? target : gen_reg_rtx (compute_mode));
quotient = gen_reg_rtx (compute_mode);
}
else
{
- quotient = (GET_CODE (target) == REG
+ quotient = (REG_P (target)
? target : gen_reg_rtx (compute_mode));
remainder = gen_reg_rtx (compute_mode);
}
target = gen_reg_rtx (compute_mode);
if (rem_flag)
{
- remainder= (GET_CODE (target) == REG
+ remainder= (REG_P (target)
? target : gen_reg_rtx (compute_mode));
quotient = gen_reg_rtx (compute_mode);
}
else
{
- quotient = (GET_CODE (target) == REG
+ quotient = (REG_P (target)
? target : gen_reg_rtx (compute_mode));
remainder = gen_reg_rtx (compute_mode);
}
/* If this failed, we have to do this with set/compare/jump/set code. */
- if (GET_CODE (target) != REG
+ if (!REG_P (target)
|| reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
target = gen_reg_rtx (GET_MODE (target));
&& ((code = can_extend_p (to_mode, word_mode, unsignedp))
!= CODE_FOR_nothing))
{
- if (GET_CODE (to) == REG)
+ if (REG_P (to))
{
if (reg_overlap_mentioned_p (to, from))
from = force_reg (from_mode, from);
&& ! MEM_VOLATILE_P (from)
&& direct_load[(int) to_mode]
&& ! mode_dependent_address_p (XEXP (from, 0)))
- || GET_CODE (from) == REG
+ || REG_P (from)
|| GET_CODE (from) == SUBREG))
from = force_reg (from_mode, from);
convert_move (to, gen_lowpart (word_mode, from), 0);
&& ! MEM_VOLATILE_P (from)
&& direct_load[(int) to_mode]
&& ! mode_dependent_address_p (XEXP (from, 0)))
- || GET_CODE (from) == REG
+ || REG_P (from)
|| GET_CODE (from) == SUBREG))
from = force_reg (from_mode, from);
- if (GET_CODE (from) == REG && REGNO (from) < FIRST_PSEUDO_REGISTER
+ if (REG_P (from) && REGNO (from) < FIRST_PSEUDO_REGISTER
&& ! HARD_REGNO_MODE_OK (REGNO (from), to_mode))
from = copy_to_reg (from);
emit_move_insn (to, gen_lowpart (to_mode, from));
|| (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (oldmode)
&& ((GET_CODE (x) == MEM && ! MEM_VOLATILE_P (x)
&& direct_load[(int) mode])
- || (GET_CODE (x) == REG
+ || (REG_P (x)
&& (! HARD_REGISTER_P (x)
|| HARD_REGNO_MODE_OK (REGNO (x), mode))
&& TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
to be extracted. */
tmps[i] = XEXP (src, bytepos / slen0);
if (! CONSTANT_P (tmps[i])
- && (GET_CODE (tmps[i]) != REG || GET_MODE (tmps[i]) != mode))
+ && (!REG_P (tmps[i]) || GET_MODE (tmps[i]) != mode))
tmps[i] = extract_bit_field (tmps[i], bytelen * BITS_PER_UNIT,
(bytepos % slen0) * BITS_PER_UNIT,
1, NULL_RTX, mode, mode, ssize);
SIMD register, which is currently broken. While we get GCC
to emit proper RTL for these cases, let's dump to memory. */
else if (VECTOR_MODE_P (GET_MODE (dst))
- && GET_CODE (src) == REG)
+ && REG_P (src))
{
int slen = GET_MODE_SIZE (GET_MODE (src));
rtx mem;
&& XVECLEN (dst, 0) > 1)
tmps[i] = simplify_gen_subreg (mode, src, GET_MODE(dst), bytepos);
else if (CONSTANT_P (src)
- || (GET_CODE (src) == REG && GET_MODE (src) == mode))
+ || (REG_P (src) && GET_MODE (src) == mode))
tmps[i] = src;
else
tmps[i] = extract_bit_field (src, bytelen * BITS_PER_UNIT,
void
use_reg (rtx *call_fusage, rtx reg)
{
- if (GET_CODE (reg) != REG
+ if (!REG_P (reg)
|| REGNO (reg) >= FIRST_PSEUDO_REGISTER)
abort ();
/* A NULL entry means the parameter goes both on the stack and in
registers. This can also be a MEM for targets that pass values
partially on the stack and partially in registers. */
- if (reg != 0 && GET_CODE (reg) == REG)
+ if (reg != 0 && REG_P (reg))
use_reg (call_fusage, reg);
}
}
last_insn = emit_move_insn_1 (x, y);
- if (y_cst && GET_CODE (x) == REG
+ if (y_cst && REG_P (x)
&& (set = single_set (last_insn)) != NULL_RTX
&& SET_DEST (set) == x
&& ! rtx_equal_p (y_cst, SET_SRC (set)))
emit_unop_insn (ic, x, trunc_y, UNKNOWN);
last_insn = get_last_insn ();
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
set_unique_reg_note (last_insn, REG_EQUAL, y);
return last_insn;
size = convert_modes (Pmode, ptr_mode, size, 1);
if (CONSTANT_P (size))
anti_adjust_stack (plus_constant (size, extra));
- else if (GET_CODE (size) == REG && extra == 0)
+ else if (REG_P (size) && extra == 0)
anti_adjust_stack (size);
else
{
/* If X is a hard register in a non-integer mode, copy it into a pseudo;
SUBREGs of such registers are not allowed. */
- if ((GET_CODE (x) == REG && REGNO (x) < FIRST_PSEUDO_REGISTER
+ if ((REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER
&& GET_MODE_CLASS (GET_MODE (x)) != MODE_INT))
x = copy_to_reg (x);
{
return ((x == 0
/* Only registers can be subtargets. */
- || GET_CODE (x) != REG
+ || !REG_P (x)
/* If the register is readonly, it can't be set more than once. */
|| RTX_UNCHANGING_P (x)
/* Don't use hard regs to avoid extending their life. */
if (TREE_CODE (from) == CALL_EXPR && ! aggregate_value_p (from, from)
&& TREE_CODE (TYPE_SIZE (TREE_TYPE (from))) == INTEGER_CST
&& ! ((TREE_CODE (to) == VAR_DECL || TREE_CODE (to) == PARM_DECL)
- && GET_CODE (DECL_RTL (to)) == REG))
+ && REG_P (DECL_RTL (to))))
{
rtx value;
/* Don't move directly into a return register. */
if (TREE_CODE (to) == RESULT_DECL
- && (GET_CODE (to_rtx) == REG || GET_CODE (to_rtx) == PARALLEL))
+ && (REG_P (to_rtx) || GET_CODE (to_rtx) == PARALLEL))
{
rtx temp;
Otherwise, if TEMP is not TARGET, return TEMP
if it is constant (for efficiency),
or if we really want the correct value. */
- if (!(target && GET_CODE (target) == REG
+ if (!(target && REG_P (target)
&& REGNO (target) < FIRST_PSEUDO_REGISTER)
&& !(GET_CODE (target) == MEM && MEM_VOLATILE_P (target))
&& ! rtx_equal_p (temp, target)
/* Return TARGET itself if it is a hard register. */
else if ((want_value & 1) != 0
&& GET_MODE (target) != BLKmode
- && ! (GET_CODE (target) == REG
+ && ! (REG_P (target)
&& REGNO (target) < FIRST_PSEUDO_REGISTER))
return copy_to_reg (target);
set the initial value as zero so we can fold the value into
a constant. But if more than one register is involved,
this probably loses. */
- else if (GET_CODE (target) == REG && TREE_STATIC (exp)
+ else if (REG_P (target) && TREE_STATIC (exp)
&& GET_MODE_SIZE (GET_MODE (target)) <= UNITS_PER_WORD)
{
emit_move_insn (target, CONST0_RTX (GET_MODE (target)));
else if (size > 0
&& ((list_length (CONSTRUCTOR_ELTS (exp)) != fields_length (type))
|| mostly_zeros_p (exp))
- && (GET_CODE (target) != REG
+ && (!REG_P (target)
|| ((HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (target))
== size)))
{
start of a word, try to widen it to a full word.
This special case allows us to output C++ member function
initializations in a form that the optimizers can understand. */
- if (GET_CODE (target) == REG
+ if (REG_P (target)
&& bitsize < BITS_PER_WORD
&& bitpos % BITS_PER_WORD == 0
&& GET_MODE_CLASS (mode) == MODE_INT
/* If the constructor has fewer elements than the array,
clear the whole array first. Similarly if this is
static constructor of a non-BLKmode object. */
- if (cleared || (GET_CODE (target) == REG && TREE_STATIC (exp)))
+ if (cleared || (REG_P (target) && TREE_STATIC (exp)))
need_to_clear = 1;
else
{
twice, once with emit_move_insn and once via store_field. */
if (mode == BLKmode
- && (GET_CODE (target) == REG || GET_CODE (target) == SUBREG))
+ && (REG_P (target) || GET_CODE (target) == SUBREG))
{
rtx object = assign_temp (type, 0, 1, 1);
rtx blk_object = adjust_address (object, BLKmode, 0);
|| (mode != BLKmode && ! direct_store[(int) mode]
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
- || GET_CODE (target) == REG
+ || REG_P (target)
|| GET_CODE (target) == SUBREG
/* If the field isn't aligned enough to store as an ordinary memref,
store it as a bit field. */
/* If a value is wanted, it must be the lhs;
so make the address stable for multiple use. */
- if (value_mode != VOIDmode && GET_CODE (addr) != REG
+ if (value_mode != VOIDmode && !REG_P (addr)
&& ! CONSTANT_ADDRESS_P (addr)
/* A frame-pointer reference is already stable. */
&& ! (GET_CODE (addr) == PLUS
/* Check for subreg applied to an expression produced by loop optimizer. */
if (code == SUBREG
- && GET_CODE (SUBREG_REG (value)) != REG
+ && !REG_P (SUBREG_REG (value))
&& GET_CODE (SUBREG_REG (value)) != MEM)
{
value = simplify_gen_subreg (GET_MODE (value),
if (ARITHMETIC_P (value))
{
op2 = XEXP (value, 1);
- if (!CONSTANT_P (op2) && !(GET_CODE (op2) == REG && op2 != subtarget))
+ if (!CONSTANT_P (op2) && !(REG_P (op2) && op2 != subtarget))
subtarget = 0;
if (code == MINUS && GET_CODE (op2) == CONST_INT)
{
creating another one around this addition. */
if (code == PLUS && GET_CODE (op2) == CONST_INT
&& GET_CODE (XEXP (value, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (value, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (value, 0), 0))
&& REGNO (XEXP (XEXP (value, 0), 0)) >= FIRST_VIRTUAL_REGISTER
&& REGNO (XEXP (XEXP (value, 0), 0)) <= LAST_VIRTUAL_REGISTER)
{
if (GET_CODE (x) == SUBREG)
{
x = SUBREG_REG (x);
- if (GET_CODE (x) == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
+ if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
return 0;
}
case CALL_EXPR:
/* Assume that the call will clobber all hard registers and
all of memory. */
- if ((GET_CODE (x) == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
+ if ((REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
|| GET_CODE (x) == MEM)
return 0;
break;
if (GET_CODE (exp_rtl) == SUBREG)
{
exp_rtl = SUBREG_REG (exp_rtl);
- if (GET_CODE (exp_rtl) == REG
+ if (REG_P (exp_rtl)
&& REGNO (exp_rtl) < FIRST_PSEUDO_REGISTER)
return 0;
}
Another is a CALL_EXPR which must return in memory. */
if (! cse_not_expected && mode != BLKmode && target
- && (GET_CODE (target) != REG || REGNO (target) < FIRST_PSEUDO_REGISTER)
+ && (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
&& ! (code == CONSTRUCTOR && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
&& ! (code == CALL_EXPR && aggregate_value_p (exp, exp)))
target = 0;
See expand_decl. */
else if (GET_CODE (DECL_RTL (exp)) == MEM
- && GET_CODE (XEXP (DECL_RTL (exp), 0)) == REG)
+ && REG_P (XEXP (DECL_RTL (exp), 0)))
temp = validize_mem (DECL_RTL (exp));
/* If DECL_RTL is memory, we are in the normal case and either
&& (! memory_address_p (DECL_MODE (exp),
XEXP (DECL_RTL (exp), 0))
|| (flag_force_addr
- && GET_CODE (XEXP (DECL_RTL (exp), 0)) != REG)))
+ && !REG_P (XEXP (DECL_RTL (exp), 0)))))
{
if (alt_rtl)
*alt_rtl = DECL_RTL (exp);
if the address is a register. */
if (temp != 0)
{
- if (GET_CODE (temp) == MEM && GET_CODE (XEXP (temp, 0)) == REG)
+ if (GET_CODE (temp) == MEM && REG_P (XEXP (temp, 0)))
mark_reg_pointer (XEXP (temp, 0), DECL_ALIGN (exp));
return temp;
must be a promoted value. We return a SUBREG of the wanted mode,
but mark it so that we know that it was already extended. */
- if (GET_CODE (DECL_RTL (exp)) == REG
+ if (REG_P (DECL_RTL (exp))
&& GET_MODE (DECL_RTL (exp)) != DECL_MODE (exp))
{
/* Get the signedness used for this variable. Ensure we get the
find_function_data (context);
temp = SAVE_EXPR_RTL (exp);
- if (temp && GET_CODE (temp) == REG)
+ if (temp && REG_P (temp))
{
put_var_into_stack (exp, /*rescan=*/true);
temp = SAVE_EXPR_RTL (exp);
3, 0, 0);
SAVE_EXPR_RTL (exp) = temp;
- if (!optimize && GET_CODE (temp) == REG)
+ if (!optimize && REG_P (temp))
save_expr_regs = gen_rtx_EXPR_LIST (VOIDmode, temp,
save_expr_regs);
wanted mode but mark it so that we know that it was already
extended. */
- if (GET_CODE (temp) == REG && GET_MODE (temp) != mode)
+ if (REG_P (temp) && GET_MODE (temp) != mode)
{
temp = gen_lowpart_SUBREG (mode, SAVE_EXPR_RTL (exp));
promote_mode (type, mode, &unsignedp, 0);
must be a promoted value. We return a SUBREG of the wanted mode,
but mark it so that we know that it was already extended. */
- if (GET_CODE (SAVE_EXPR_RTL (exp)) == REG
+ if (REG_P (SAVE_EXPR_RTL (exp))
&& GET_MODE (SAVE_EXPR_RTL (exp)) != mode)
{
/* Compute the signedness and make the proper SUBREG. */
(which we know to be the width of a basic mode), then
storing into memory, and changing the mode to BLKmode. */
if (mode1 == VOIDmode
- || GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG
+ || REG_P (op0) || GET_CODE (op0) == SUBREG
|| (mode1 != BLKmode && ! direct_load[(int) mode1]
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT
op0 = validize_mem (op0);
- if (GET_CODE (op0) == MEM && GET_CODE (XEXP (op0, 0)) == REG)
+ if (GET_CODE (op0) == MEM && REG_P (XEXP (op0, 0)))
mark_reg_pointer (XEXP (op0, 0), MEM_ALIGN (op0));
op0 = extract_bit_field (op0, bitsize, bitpos, unsignedp,
op0 = copy_rtx (op0);
set_mem_attributes (op0, exp, 0);
- if (GET_CODE (XEXP (op0, 0)) == REG)
+ if (REG_P (XEXP (op0, 0)))
mark_reg_pointer (XEXP (op0, 0), MEM_ALIGN (op0));
MEM_VOLATILE_P (op0) |= volatilep;
adjust_address (target, TYPE_MODE (valtype), 0),
modifier == EXPAND_STACK_PARM ? 2 : 0);
- else if (GET_CODE (target) == REG)
+ else if (REG_P (target))
/* Store this field into a union of the proper type. */
store_field (target,
MIN ((int_size_in_bytes (TREE_TYPE
op0 = expand_expr (TREE_OPERAND (exp, 0), subtarget, VOIDmode,
EXPAND_SUM);
- if (GET_CODE (op0) != REG)
+ if (!REG_P (op0))
op0 = force_operand (op0, NULL_RTX);
- if (GET_CODE (op0) != REG)
+ if (!REG_P (op0))
op0 = copy_to_mode_reg (mode, op0);
return gen_rtx_MULT (mode, op0,
|| modifier == EXPAND_STACK_PARM
|| (GET_CODE (target) == MEM && MEM_VOLATILE_P (target))
|| GET_MODE (target) != mode
- || (GET_CODE (target) == REG
+ || (REG_P (target)
&& REGNO (target) < FIRST_PSEUDO_REGISTER))
target = gen_reg_rtx (mode);
expand_operands (TREE_OPERAND (exp, 0), TREE_OPERAND (exp, 1),
/* For foo != 0, load foo, and if it is nonzero load 1 instead. */
if (code == NE_EXPR && integer_zerop (TREE_OPERAND (exp, 1))
&& original_target
- && GET_CODE (original_target) == REG
+ && REG_P (original_target)
&& (GET_MODE (original_target)
== TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0)))))
{
|| ! safe_from_p (target, exp, 1)
/* Make sure we don't have a hard reg (such as function's return
value) live across basic blocks, if not optimizing. */
- || (!optimize && GET_CODE (target) == REG
+ || (!optimize && REG_P (target)
&& REGNO (target) < FIRST_PSEUDO_REGISTER)))
target = gen_reg_rtx (tmode != VOIDmode ? tmode : mode);
temp = assign_temp (type, 0, 0, 1);
else if (original_target
&& (safe_from_p (original_target, TREE_OPERAND (exp, 0), 1)
- || (singleton && GET_CODE (original_target) == REG
+ || (singleton && REG_P (original_target)
&& REGNO (original_target) >= FIRST_PSEUDO_REGISTER
&& original_target == var_rtx (singleton)))
&& GET_MODE (original_target) == mode
#ifdef HAVE_conditional_move
&& (! can_conditionally_move_p (mode)
- || GET_CODE (original_target) == REG
+ || REG_P (original_target)
|| TREE_ADDRESSABLE (type))
#endif
&& (GET_CODE (original_target) != MEM
might clobber it. */
if ((binary_op
&& ! safe_from_p (temp, TREE_OPERAND (binary_op, 1), 1))
- || (GET_CODE (temp) == REG
+ || (REG_P (temp)
&& REGNO (temp) < FIRST_PSEUDO_REGISTER))
temp = gen_reg_rtx (mode);
store_expr (singleton, temp,
|| TREE_CODE (TREE_OPERAND (exp, 1)) == SAVE_EXPR)
&& safe_from_p (temp, TREE_OPERAND (exp, 2), 1))
{
- if (GET_CODE (temp) == REG
+ if (REG_P (temp)
&& REGNO (temp) < FIRST_PSEUDO_REGISTER)
temp = gen_reg_rtx (mode);
store_expr (TREE_OPERAND (exp, 1), temp,
|| TREE_CODE (TREE_OPERAND (exp, 2)) == SAVE_EXPR)
&& safe_from_p (temp, TREE_OPERAND (exp, 1), 1))
{
- if (GET_CODE (temp) == REG
+ if (REG_P (temp)
&& REGNO (temp) < FIRST_PSEUDO_REGISTER)
temp = gen_reg_rtx (mode);
store_expr (TREE_OPERAND (exp, 2), temp,
if (CONSTANT_P (op0))
op0 = force_const_mem (TYPE_MODE (TREE_TYPE (TREE_OPERAND (exp, 0))),
op0);
- else if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG
+ else if (REG_P (op0) || GET_CODE (op0) == SUBREG
|| GET_CODE (op0) == CONCAT || GET_CODE (op0) == ADDRESSOF
|| GET_CODE (op0) == PARALLEL || GET_CODE (op0) == LO_SUM)
{
}
if (flag_force_addr
- && GET_CODE (op0) != REG
+ && !REG_P (op0)
&& modifier != EXPAND_CONST_ADDRESS
&& modifier != EXPAND_INITIALIZER
&& modifier != EXPAND_SUM)
op0 = force_reg (Pmode, op0);
- if (GET_CODE (op0) == REG
+ if (REG_P (op0)
&& ! REG_USERVAR_P (op0))
mark_reg_pointer (op0, TYPE_ALIGN (TREE_TYPE (type)));
bad_subreg = 1;
}
- op0_is_copy = ((GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
+ op0_is_copy = ((GET_CODE (op0) == SUBREG || REG_P (op0))
&& temp != get_last_insn ());
op1 = expand_expr (TREE_OPERAND (exp, 1), NULL_RTX, VOIDmode, 0);
}
/* If this failed, we have to do this with set/compare/jump/set code. */
- if (GET_CODE (target) != REG
+ if (!REG_P (target)
|| reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
target = gen_reg_rtx (GET_MODE (target));
out of PIC_CASE_VECTOR_ADDRESS won't be a valid address,
and break_out_memory_refs will go to work on it and mess it up. */
#ifdef PIC_CASE_VECTOR_ADDRESS
- if (flag_pic && GET_CODE (index) != REG)
+ if (flag_pic && !REG_P (index))
index = copy_to_mode_reg (Pmode, index);
#endif
function_section (current_function_decl);
#if defined(ASM_OUTPUT_REG_PUSH)
- if (sval && svrtx != NULL_RTX && GET_CODE (svrtx) == REG)
+ if (sval && svrtx != NULL_RTX && REG_P (svrtx))
ASM_OUTPUT_REG_PUSH (file, REGNO (svrtx));
#endif
#endif
#if defined(ASM_OUTPUT_REG_PUSH)
- if (sval && svrtx != NULL_RTX && GET_CODE (svrtx) == REG)
+ if (sval && svrtx != NULL_RTX && REG_P (svrtx))
ASM_OUTPUT_REG_POP (file, REGNO (svrtx));
#endif
}
if (final_sequence == 0
&& prescan >= 0
&& GET_CODE (insn) == INSN && GET_CODE (body) == SET
- && GET_CODE (SET_SRC (body)) == REG
- && GET_CODE (SET_DEST (body)) == REG
+ && REG_P (SET_SRC (body))
+ && REG_P (SET_DEST (body))
&& REGNO (SET_SRC (body)) == REGNO (SET_DEST (body)))
break;
#endif
if (new != 0)
*xp = new;
/* Simplify_subreg can't handle some REG cases, but we have to. */
- else if (GET_CODE (y) == REG)
+ else if (REG_P (y))
{
unsigned int regno = subreg_hard_regno (x, 1);
*xp = gen_rtx_REG_offset (y, GET_MODE (x), regno, SUBREG_BYTE (x));
*paddressp = 0;
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
return REG_EXPR (op);
else if (GET_CODE (op) != MEM)
return 0;
/* If X is a pseudo-register, abort now rather than writing trash to the
assembler file. */
- if (x && GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
+ if (x && REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
abort ();
PRINT_OPERAND (asm_out_file, x, code);
if (current_function_uses_pic_offset_table
&& pic_offset_table_rtx != 0
- && GET_CODE (pic_offset_table_rtx) == REG
+ && REG_P (pic_offset_table_rtx)
&& ! permitted_reg_in_leaf_functions[REGNO (pic_offset_table_rtx)])
return 0;
renumbered_regs would be 1 for an output-register;
they */
- if (GET_CODE (in_rtx) == REG)
+ if (REG_P (in_rtx))
{
int newreg;
rtx x = *px;
unsigned int regno = *(int *) pregno;
- if (GET_CODE (x) == REG && REGNO (x) == regno)
+ if (REG_P (x) && REGNO (x) == regno)
{
if (GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD)
return 2;
case ZERO_EXTRACT:
case SIGN_EXTRACT:
case STRICT_LOW_PART:
- if (GET_CODE (XEXP (*ptr, 0)) == REG && REGNO (XEXP (*ptr, 0)) == reg)
+ if (REG_P (XEXP (*ptr, 0)) && REGNO (XEXP (*ptr, 0)) == reg)
{
param->retval = XEXP (*ptr, 0);
return 1;
break;
case SUBREG:
- if (GET_CODE (SUBREG_REG (*ptr)) == REG
+ if (REG_P (SUBREG_REG (*ptr))
&& REGNO (SUBREG_REG (*ptr)) == reg)
{
param->retval = SUBREG_REG (*ptr);
/* Does this instruction increment or decrement a register? */
if ((flags & PROP_AUTOINC)
&& x != 0
- && GET_CODE (SET_DEST (x)) == REG
+ && REG_P (SET_DEST (x))
&& (GET_CODE (SET_SRC (x)) == PLUS
|| GET_CODE (SET_SRC (x)) == MINUS)
&& XEXP (SET_SRC (x), 0) == SET_DEST (x)
in the form of a comparison of a register against zero.
If the condition is more complex than that, then it is safe
not to record any information. */
- if (GET_CODE (reg) == REG
+ if (REG_P (reg)
&& XEXP (cond_true, 1) == const0_rtx)
{
rtx cond_false
|| GET_CODE (r) == ZERO_EXTRACT)
r = XEXP (r, 0);
- if (GET_CODE (r) == REG)
+ if (REG_P (r))
{
int regno = REGNO (r);
is not necessarily true for hard registers until after reload. */
else if (code == CLOBBER)
{
- if (GET_CODE (XEXP (x, 0)) == REG
+ if (REG_P (XEXP (x, 0))
&& (REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER
|| reload_completed)
&& ! REGNO_REG_SET_P (pbi->reg_live, REGNO (XEXP (x, 0))))
{
rtx r = SET_SRC (x);
- if (GET_CODE (r) == REG)
+ if (REG_P (r))
{
rtx call = XEXP (note, 0);
rtx call_pat;
break;
case SUBREG:
- if (GET_CODE (SUBREG_REG (reg)) == REG)
+ if (REG_P (SUBREG_REG (reg)))
{
enum machine_mode outer_mode = GET_MODE (reg);
enum machine_mode inner_mode = GET_MODE (SUBREG_REG (reg));
If this set is a REG, then it kills any MEMs which use the reg. */
if (optimize && (flags & PROP_SCAN_DEAD_STORES))
{
- if (GET_CODE (reg) == REG)
+ if (REG_P (reg))
invalidate_mems_from_set (pbi, reg);
/* If the memory reference had embedded side effects (autoincrement
add_to_mem_set_list (pbi, canon_rtx (reg));
}
- if (GET_CODE (reg) == REG
+ if (REG_P (reg)
&& ! (regno_first == FRAME_POINTER_REGNUM
&& (! reload_completed || frame_pointer_needed))
#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
}
}
}
- else if (GET_CODE (reg) == REG)
+ else if (REG_P (reg))
{
if (flags & (PROP_LOG_LINKS | PROP_AUTOINC))
pbi->reg_next_use[regno_first] = 0;
if (x_code == NOT)
return XEXP (x, 0);
if (COMPARISON_P (x)
- && GET_CODE (XEXP (x, 0)) == REG)
+ && REG_P (XEXP (x, 0)))
{
if (XEXP (x, 1) != const0_rtx)
abort ();
if (! validate_change (insn, &XEXP (mem, 0), inc, 0))
return;
}
- else if (GET_CODE (q) == REG
+ else if (REG_P (q)
/* PREV_INSN used here to check the semi-open interval
[insn,incr). */
&& ! reg_used_between_p (q, PREV_INSN (insn), incr)
if (GET_CODE (addr) == PLUS && GET_CODE (XEXP (addr, 1)) == CONST_INT)
offset = INTVAL (XEXP (addr, 1)), addr = XEXP (addr, 0);
- if (GET_CODE (addr) != REG)
+ if (!REG_P (addr))
return;
regno = REGNO (addr);
inc_val)),
insn, x, incr, addr);
}
- else if (GET_CODE (inc_val) == REG
+ else if (REG_P (inc_val)
&& ! reg_set_between_p (inc_val, PREV_INSN (insn),
NEXT_INSN (incr)))
case SUBREG:
#ifdef CANNOT_CHANGE_MODE_CLASS
if ((flags & PROP_REG_INFO)
- && GET_CODE (SUBREG_REG (x)) == REG
+ && REG_P (SUBREG_REG (x))
&& REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (x))
* MAX_MACHINE_MODE
/* While we're here, optimize this case. */
x = SUBREG_REG (x);
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
goto retry;
/* Fall through. */
#ifdef CANNOT_CHANGE_MODE_CLASS
if ((flags & PROP_REG_INFO)
&& GET_CODE (testreg) == SUBREG
- && GET_CODE (SUBREG_REG (testreg)) == REG
+ && REG_P (SUBREG_REG (testreg))
&& REGNO (SUBREG_REG (testreg)) >= FIRST_PSEUDO_REGISTER)
bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (testreg))
* MAX_MACHINE_MODE
if ((GET_CODE (testreg) == PARALLEL
&& GET_MODE (testreg) == BLKmode)
- || (GET_CODE (testreg) == REG
+ || (REG_P (testreg)
&& (regno = REGNO (testreg),
! (regno == FRAME_POINTER_REGNUM
&& (! reload_completed || frame_pointer_needed)))
switch (REG_NOTE_KIND (link))
{
case REG_DEAD:
- if (GET_CODE (XEXP (link, 0)) == REG)
+ if (REG_P (XEXP (link, 0)))
{
rtx reg = XEXP (link, 0);
int n;
/* If we have a sum involving a register, see if it points to a temp
slot. */
- if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
+ if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
&& (p = find_temp_slot_from_address (XEXP (x, 0))) != 0)
return p;
- else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG
+ else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 1))
&& (p = find_temp_slot_from_address (XEXP (x, 1))) != 0)
return p;
if (GET_CODE (old) != PLUS)
return;
- if (GET_CODE (new) == REG)
+ if (REG_P (new))
{
update_temp_slot_address (XEXP (old, 0), new);
update_temp_slot_address (XEXP (old, 1), new);
a temporary slot we know it points to. To be consistent with
the code below, we really should preserve all non-kept slots
if we can't find a match, but that seems to be much too costly. */
- if (GET_CODE (x) == REG && REG_POINTER (x))
+ if (REG_P (x) && REG_POINTER (x))
p = find_temp_slot_from_address (x);
/* If X is not in memory or is at a constant address, it cannot be in
if the var is non-local. */
if (TREE_CODE (decl) != SAVE_EXPR && DECL_NONLOCAL (decl)
&& GET_CODE (reg) == MEM
- && GET_CODE (XEXP (reg, 0)) == REG
+ && REG_P (XEXP (reg, 0))
&& REGNO (XEXP (reg, 0)) > LAST_VIRTUAL_REGISTER)
{
orig_reg = reg = XEXP (reg, 0);
/* Now we should have a value that resides in one or more pseudo regs. */
- if (GET_CODE (reg) == REG)
+ if (REG_P (reg))
{
if (can_use_addressof_p)
gen_mem_addressof (reg, decl, rescan);
don't delete the insn. */
&& find_reg_note (insn, REG_RETVAL, NULL_RTX) == 0
&& (rtx_equal_p (SET_SRC (set), var)
- || (GET_CODE (SET_SRC (set)) == REG
+ || (REG_P (SET_SRC (set))
&& (prev = prev_nonnote_insn (insn)) != 0
&& (prev_set = single_set (prev)) != 0
&& SET_DEST (prev_set) == SET_SRC (set)
{
struct fixup_replacement *next;
- if (GET_CODE (replacements->new) == REG)
+ if (REG_P (replacements->new))
{
rtx insert_before;
rtx seq;
if ((SET_SRC (x) == var
|| (GET_CODE (SET_SRC (x)) == SUBREG
&& SUBREG_REG (SET_SRC (x)) == var))
- && (GET_CODE (SET_DEST (x)) == REG
+ && (REG_P (SET_DEST (x))
|| (GET_CODE (SET_DEST (x)) == SUBREG
- && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG))
+ && REG_P (SUBREG_REG (SET_DEST (x)))))
&& GET_MODE (var) == promoted_mode
&& x == single_set (insn))
{
if ((SET_DEST (x) == var
|| (GET_CODE (SET_DEST (x)) == SUBREG
&& SUBREG_REG (SET_DEST (x)) == var))
- && (GET_CODE (SET_SRC (x)) == REG
+ && (REG_P (SET_SRC (x))
|| (GET_CODE (SET_SRC (x)) == SUBREG
- && GET_CODE (SUBREG_REG (SET_SRC (x))) == REG))
+ && REG_P (SUBREG_REG (SET_SRC (x)))))
&& GET_MODE (var) == promoted_mode
&& x == single_set (insn))
{
/* If we have address of a stack slot but it's not valid
(displacement is too large), compute the sum in a register. */
if (GET_CODE (ad) == PLUS
- && GET_CODE (XEXP (ad, 0)) == REG
+ && REG_P (XEXP (ad, 0))
&& ((REGNO (XEXP (ad, 0)) >= FIRST_VIRTUAL_REGISTER
&& REGNO (XEXP (ad, 0)) <= LAST_VIRTUAL_REGISTER)
|| REGNO (XEXP (ad, 0)) == FRAME_POINTER_REGNUM
if (GET_CODE (XEXP (bitfield, 0)) == MEM)
memref = XEXP (bitfield, 0);
- else if (GET_CODE (XEXP (bitfield, 0)) == REG
+ else if (REG_P (XEXP (bitfield, 0))
&& equiv_mem != 0)
memref = equiv_mem[REGNO (XEXP (bitfield, 0))];
else if (GET_CODE (XEXP (bitfield, 0)) == SUBREG
memref = SUBREG_REG (XEXP (bitfield, 0));
else if (GET_CODE (XEXP (bitfield, 0)) == SUBREG
&& equiv_mem != 0
- && GET_CODE (SUBREG_REG (XEXP (bitfield, 0))) == REG)
+ && REG_P (SUBREG_REG (XEXP (bitfield, 0))))
memref = equiv_mem[REGNO (SUBREG_REG (XEXP (bitfield, 0)))];
if (memref
&& DECL_RTL (decl) != 0
&& GET_CODE (DECL_RTL (decl)) == MEM
&& GET_CODE (XEXP (DECL_RTL (decl), 0)) == ADDRESSOF
- && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == REG)
+ && REG_P (XEXP (XEXP (DECL_RTL (decl), 0), 0)))
put_addressof_into_stack (XEXP (DECL_RTL (decl), 0), 0);
}
rtx reg = XEXP (r, 0);
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
abort ();
decl = ADDRESSOF_DECL (r);
/* If SUB is a hard or virtual register, try it as a pseudo-register.
Otherwise, perhaps SUB is an expression, so generate code to compute
it. */
- if (GET_CODE (sub) == REG && REGNO (sub) <= LAST_VIRTUAL_REGISTER)
+ if (REG_P (sub) && REGNO (sub) <= LAST_VIRTUAL_REGISTER)
sub = copy_to_reg (sub);
else
sub = force_operand (sub, NULL_RTX);
if (GET_CODE (sub) == MEM)
sub = adjust_address_nv (sub, GET_MODE (x), 0);
- else if (GET_CODE (sub) == REG
+ else if (REG_P (sub)
&& (MEM_VOLATILE_P (x) || GET_MODE (x) == BLKmode))
;
- else if (GET_CODE (sub) == REG && GET_MODE (x) != GET_MODE (sub))
+ else if (REG_P (sub) && GET_MODE (x) != GET_MODE (sub))
{
int size_x, size_sub;
rtx z = XEXP (XEXP (tem, 1), 0);
if (GET_MODE (x) == GET_MODE (z)
- || (GET_CODE (XEXP (XEXP (tem, 1), 0)) != REG
+ || (!REG_P (XEXP (XEXP (tem, 1), 0))
&& GET_CODE (XEXP (XEXP (tem, 1), 0)) != SUBREG))
abort ();
{
/* Remember the replacement so that the same one can be done
on the REG_NOTES. */
- if (GET_CODE (sub) == REG || GET_CODE (sub) == SUBREG)
+ if (REG_P (sub) || GET_CODE (sub) == SUBREG)
{
rtx tem;
tmp.insns = NULL_RTX;
if (ifmwi->pass == 0 && *r && GET_CODE (*r) == ADDRESSOF
- && GET_CODE (XEXP (*r, 0)) == REG)
+ && REG_P (XEXP (*r, 0)))
{
void **e;
tmp.key = XEXP (*r, 0);
memcpy (*e, &tmp, sizeof (tmp));
}
}
- else if (ifmwi->pass == 1 && *r && GET_CODE (*r) == REG)
+ else if (ifmwi->pass == 1 && *r && REG_P (*r))
{
struct insns_for_mem_entry *ifme;
tmp.key = *r;
enum machine_mode mode = GET_MODE (SET_DEST (pattern));
int offset = 0;
- if (GET_CODE (reg) == SUBREG && GET_CODE (SUBREG_REG (reg)) == REG
+ if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg))
&& REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER)
{
offset = subreg_regno_offset (REGNO (SUBREG_REG (reg)),
}
- if (GET_CODE (reg) == REG && REGNO (reg) < FIRST_PSEUDO_REGISTER)
+ if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)
{
reg = gen_rtx_REG (mode, REGNO (reg) + offset);
SET_DEST (pattern) = reg;
addr = XEXP (x, 0);
if (CONSTANT_P (addr)
- || (GET_CODE (addr) == ADDRESSOF && GET_CODE (XEXP (addr, 0)) == REG)
- || (GET_CODE (addr) == REG
+ || (GET_CODE (addr) == ADDRESSOF && REG_P (XEXP (addr, 0)))
+ || (REG_P (addr)
&& (REGNO (addr) < FIRST_VIRTUAL_REGISTER
|| REGNO (addr) > LAST_VIRTUAL_REGISTER)))
return;
/* The only valid sources here are PLUS or REG. Just do
the simplest possible thing to handle them. */
- if (GET_CODE (src) != REG && GET_CODE (src) != PLUS)
+ if (!REG_P (src) && GET_CODE (src) != PLUS)
{
instantiate_virtual_regs_lossage (object);
return 1;
}
start_sequence ();
- if (GET_CODE (src) != REG)
+ if (!REG_P (src))
temp = force_operand (src, NULL_RTX);
else
temp = src;
/* We know the second operand is a constant. Unless the
first operand is a REG (which has been already checked),
it needs to be checked. */
- if (GET_CODE (XEXP (x, 0)) != REG)
+ if (!REG_P (XEXP (x, 0)))
{
loc = &XEXP (x, 0);
goto restart;
if ((GET_CODE (XEXP (x, 0)) == MEM
&& instantiate_virtual_regs_1 (&XEXP (XEXP (x, 0), 0), XEXP (x, 0),
0))
- || (GET_CODE (XEXP (x, 0)) == REG
+ || (REG_P (XEXP (x, 0))
&& instantiate_virtual_regs_1 (&XEXP (x, 0), object, 0)))
return 1;
return 1;
case ADDRESSOF:
- if (GET_CODE (XEXP (x, 0)) == REG)
+ if (REG_P (XEXP (x, 0)))
return 1;
else if (GET_CODE (XEXP (x, 0)) == MEM)
/* If we have something other than a REG (e.g. a PARALLEL), then assume
it is OK. */
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
return 0;
regno = REGNO (reg);
for (i = 0; i < len; i++)
if (XEXP (XVECEXP (entry_parm, 0, i), 0) != NULL_RTX
- && GET_CODE (XEXP (XVECEXP (entry_parm, 0, i), 0)) == REG
+ && REG_P (XEXP (XVECEXP (entry_parm, 0, i), 0))
&& (GET_MODE (XEXP (XVECEXP (entry_parm, 0, i), 0))
== passed_mode)
&& INTVAL (XEXP (XVECEXP (entry_parm, 0, i), 1)) == 0)
/* If a BLKmode arrives in registers, copy it to a stack slot.
Handle calls that pass values in multiple non-contiguous
locations. The Irix 6 ABI has examples of this. */
- if (GET_CODE (entry_parm) == REG
+ if (REG_P (entry_parm)
|| (GET_CODE (entry_parm) == PARALLEL
&& (!loaded_in_reg || !optimize)))
{
if (GET_CODE (tempreg) == SUBREG
&& GET_MODE (tempreg) == nominal_mode
- && GET_CODE (SUBREG_REG (tempreg)) == REG
+ && REG_P (SUBREG_REG (tempreg))
&& nominal_mode == passed_mode
&& GET_MODE (SUBREG_REG (tempreg)) == GET_MODE (entry_parm)
&& GET_MODE_SIZE (GET_MODE (tempreg))
for (arg = DECL_ARGUMENTS (current_function_decl); arg;
arg = TREE_CHAIN (arg))
- if (GET_CODE (DECL_INCOMING_RTL (arg)) == REG
+ if (REG_P (DECL_INCOMING_RTL (arg))
&& REGNO (DECL_INCOMING_RTL (arg)) == regno
&& TYPE_MODE (DECL_ARG_TYPE (arg)) == TYPE_MODE (TREE_TYPE (arg)))
{
{
if (TREE_CODE (decl) == VAR_DECL
&& DECL_RTL_SET_P (decl)
- && GET_CODE (DECL_RTL (decl)) == REG
+ && REG_P (DECL_RTL (decl))
&& regno_clobbered_at_setjmp (REGNO (DECL_RTL (decl))))
warning ("%Jvariable '%D' might be clobbered by `longjmp' or `vfork'",
decl, decl);
for (decl = DECL_ARGUMENTS (current_function_decl);
decl; decl = TREE_CHAIN (decl))
if (DECL_RTL (decl) != 0
- && GET_CODE (DECL_RTL (decl)) == REG
+ && REG_P (DECL_RTL (decl))
&& regno_clobbered_at_setjmp (REGNO (DECL_RTL (decl))))
warning ("%Jargument '%D' might be clobbered by `longjmp' or `vfork'",
decl, decl);
if ((TREE_CODE (decl) == VAR_DECL
|| TREE_CODE (decl) == PARM_DECL)
&& DECL_RTL (decl) != 0
- && (GET_CODE (DECL_RTL (decl)) == REG
+ && (REG_P (DECL_RTL (decl))
|| (GET_CODE (DECL_RTL (decl)) == MEM
&& GET_CODE (XEXP (DECL_RTL (decl), 0)) == ADDRESSOF))
/* If this variable came from an inline function, it must be
if ((TREE_CODE (decl) == VAR_DECL
|| TREE_CODE (decl) == PARM_DECL)
&& DECL_RTL (decl) != 0
- && (GET_CODE (DECL_RTL (decl)) == REG
+ && (REG_P (DECL_RTL (decl))
|| (GET_CODE (DECL_RTL (decl)) == MEM
&& GET_CODE (XEXP (DECL_RTL (decl), 0)) == ADDRESSOF))
&& (
addr = XEXP (XEXP (addr, 0), 0);
/* Decode given address as base reg plus displacement. */
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
basereg = addr, displacement = 0;
else if (GET_CODE (addr) == PLUS && GET_CODE (XEXP (addr, 1)) == CONST_INT)
basereg = XEXP (addr, 0), displacement = INTVAL (XEXP (addr, 1));
if (! outgoing)
return;
- if (GET_CODE (outgoing) == REG)
+ if (REG_P (outgoing))
(*doit) (outgoing, arg);
else if (GET_CODE (outgoing) == PARALLEL)
{
{
rtx x = XEXP (XVECEXP (outgoing, 0, i), 0);
- if (GET_CODE (x) == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
+ if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
(*doit) (x, arg);
}
}
unchanged. Otherwise, it must be a MEM and we see what the
base register and offset are. In any case, we have to emit any
pending load to the equivalent reg of SP, if any. */
- if (GET_CODE (retaddr) == REG)
+ if (REG_P (retaddr))
{
emit_equiv_load (&info);
add_insn (insn);
continue;
}
else if (GET_CODE (retaddr) == MEM
- && GET_CODE (XEXP (retaddr, 0)) == REG)
+ && REG_P (XEXP (retaddr, 0)))
base = gen_rtx_REG (Pmode, REGNO (XEXP (retaddr, 0))), offset = 0;
else if (GET_CODE (retaddr) == MEM
&& GET_CODE (XEXP (retaddr, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (retaddr, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (retaddr, 0), 0))
&& GET_CODE (XEXP (XEXP (retaddr, 0), 1)) == CONST_INT)
{
base = gen_rtx_REG (Pmode, REGNO (XEXP (XEXP (retaddr, 0), 0)));
p->new_sp_equiv_reg = XEXP (SET_SRC (set), 0);
if (GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
p->new_sp_offset = INTVAL (XEXP (SET_SRC (set), 1));
- else if (GET_CODE (XEXP (SET_SRC (set), 1)) == REG
+ else if (REG_P (XEXP (SET_SRC (set), 1))
&& REGNO (XEXP (SET_SRC (set), 1)) < FIRST_PSEUDO_REGISTER
&& p->const_equiv[REGNO (XEXP (SET_SRC (set), 1))] != 0)
p->new_sp_offset
p->new_sp_offset += p->sp_offset;
}
- if (p->new_sp_equiv_reg == 0 || GET_CODE (p->new_sp_equiv_reg) != REG)
+ if (p->new_sp_equiv_reg == 0 || !REG_P (p->new_sp_equiv_reg))
abort ();
return;
else if (p->new_sp_equiv_reg != 0 && reg_set_p (p->new_sp_equiv_reg, set))
{
if (p->equiv_reg_src != 0
- || GET_CODE (p->new_sp_equiv_reg) != REG
- || GET_CODE (SET_DEST (set)) != REG
+ || !REG_P (p->new_sp_equiv_reg)
+ || !REG_P (SET_DEST (set))
|| GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) > BITS_PER_WORD
|| REGNO (p->new_sp_equiv_reg) != REGNO (SET_DEST (set)))
abort ();
struct epi_info *p = (struct epi_info *) data;
rtx new;
- if (GET_CODE (dest) != REG || REGNO (dest) >= FIRST_PSEUDO_REGISTER)
+ if (!REG_P (dest) || REGNO (dest) >= FIRST_PSEUDO_REGISTER)
return;
/* If we are either clobbering a register or doing a partial set,
/* If this is a binary operation between a register we have been tracking
and a constant, see if we can compute a new constant value. */
else if (ARITHMETIC_P (SET_SRC (x))
- && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
+ && REG_P (XEXP (SET_SRC (x), 0))
&& REGNO (XEXP (SET_SRC (x), 0)) < FIRST_PSEUDO_REGISTER
&& p->const_equiv[REGNO (XEXP (SET_SRC (x), 0))] != 0
&& GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
if (GET_CODE (XVECEXP (insn, 1, i)) != CLOBBER)
break;
- if (GET_CODE (XEXP (XVECEXP (insn, 1, i), 0)) == REG)
+ if (REG_P (XEXP (XVECEXP (insn, 1, i), 0)))
has_hard_reg = 1;
else if (GET_CODE (XEXP (XVECEXP (insn, 1, i), 0)) != MATCH_SCRATCH)
break;
if (! (GET_MODE (old) == GET_MODE (new)
&& ((GET_CODE (old) == MATCH_SCRATCH
&& GET_CODE (new) == MATCH_SCRATCH)
- || (GET_CODE (old) == REG && GET_CODE (new) == REG
+ || (REG_P (old) && REG_P (new)
&& REGNO (old) == REGNO (new)))))
break;
}
{
rtx y = XVECEXP (x, 0, i - 1);
if (GET_CODE (y) != CLOBBER
- || (GET_CODE (XEXP (y, 0)) != REG
+ || (!REG_P (XEXP (y, 0))
&& GET_CODE (XEXP (y, 0)) != MATCH_SCRATCH))
break;
}
{
rtx set = XVECEXP (PATTERN (insn), 0, i);
if (GET_CODE (set) == SET
- && GET_CODE (SET_DEST (set)) != REG
+ && !REG_P (SET_DEST (set))
&& !rtx_equal_p (reg, SET_DEST (set))
&& reg_overlap_mentioned_p (reg, SET_DEST (set)))
used_in_output = 1;
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
if (INSN_P (insn)
&& (set = single_set (insn)) != 0
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& reg_allocno[REGNO (SET_DEST (set))] >= 0)
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_DEAD
- && GET_CODE (XEXP (link, 0)) == REG
+ && REG_P (XEXP (link, 0))
&& reg_allocno[REGNO (XEXP (link, 0))] >= 0
&& ! CONFLICTP (reg_allocno[REGNO (SET_DEST (set))],
reg_allocno[REGNO (XEXP (link, 0))]))
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
return;
regs_set[n_regs_set++] = reg;
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
return;
regno = REGNO (reg);
/* Get the reg number for both SRC and DEST.
If neither is a reg, give up. */
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
src_regno = REGNO (src);
- else if (GET_CODE (src) == SUBREG && GET_CODE (SUBREG_REG (src)) == REG)
+ else if (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src)))
{
src_regno = REGNO (SUBREG_REG (src));
else
return;
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
dest_regno = REGNO (dest);
- else if (GET_CODE (dest) == SUBREG && GET_CODE (SUBREG_REG (dest)) == REG)
+ else if (GET_CODE (dest) == SUBREG && REG_P (SUBREG_REG (dest)))
{
dest_regno = REGNO (SUBREG_REG (dest));
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
return;
regno = REGNO (reg);
for (link = REG_NOTES (first); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_DEAD
- && GET_CODE (XEXP (link, 0)) == REG)
+ && REG_P (XEXP (link, 0)))
reg_dies (REGNO (XEXP (link, 0)), GET_MODE (XEXP (link, 0)),
c);
for (link = REG_NOTES (first); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_UNUSED
- && GET_CODE (XEXP (link, 0)) == REG)
+ && REG_P (XEXP (link, 0)))
reg_dies (REGNO (XEXP (link, 0)), GET_MODE (XEXP (link, 0)),
c);
}
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
return;
regno = REGNO (reg);
/* Nonzero iff the address is comprised from at most 1 register. */
#define CONST_BASED_ADDRESS_P(x) \
- (GET_CODE (x) == REG \
+ (REG_P (x) \
|| ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \
|| (GET_CODE (x) == LO_SUM)) \
&& (CONSTANT_P (XEXP (x, 0)) \
if (GET_CODE (x) == SET
&& register_operand (SET_DEST (x), VOIDmode))
{
- if (GET_CODE (SET_DEST (x)) == REG)
+ if (REG_P (SET_DEST (x)))
{
if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
return 1;
/* Only operate on register destinations, and even then avoid extending
the lifetime of hard registers on small register class machines. */
orig_x = x;
- if (GET_CODE (x) != REG
+ if (!REG_P (x)
|| (SMALL_REGISTER_CLASSES
&& REGNO (x) < FIRST_PSEUDO_REGISTER))
{
equiv_loc = VARRAY_CONST_EQUIV (map->const_equiv_varray,
REGNO (equiv_reg)).rtx;
loc_offset
- = GET_CODE (equiv_loc) == REG ? 0 : INTVAL (XEXP (equiv_loc, 1));
+ = REG_P (equiv_loc) ? 0 : INTVAL (XEXP (equiv_loc, 1));
return gen_rtx_SET (VOIDmode, SET_DEST (orig),
force_operand
/* Set up any constant equivalences made in this insn. */
for (i = 0; i < map->num_sets; i++)
{
- if (GET_CODE (map->equiv_sets[i].dest) == REG)
+ if (REG_P (map->equiv_sets[i].dest))
{
int regno = REGNO (map->equiv_sets[i].dest);
be a special hack and we don't know how to treat it specially.
Consider for example mulsidi3 in m68k.md.
Ordinary SUBREG of a REG needs this special treatment. */
- if (! memonly && GET_CODE (SUBREG_REG (x)) == REG)
+ if (! memonly && REG_P (SUBREG_REG (x)))
{
rtx inner = SUBREG_REG (x);
rtx new = 0;
/* If storing a recognizable value save it for later recording. */
if ((map->num_sets < MAX_RECOG_OPERANDS)
&& (CONSTANT_P (src)
- || (GET_CODE (src) == REG
+ || (REG_P (src)
&& (REGNO (src) == VIRTUAL_INCOMING_ARGS_REGNUM
|| REGNO (src) == VIRTUAL_STACK_VARS_REGNUM))
|| (GET_CODE (src) == PLUS
- && GET_CODE (XEXP (src, 0)) == REG
+ && REG_P (XEXP (src, 0))
&& (REGNO (XEXP (src, 0)) == VIRTUAL_INCOMING_ARGS_REGNUM
|| REGNO (XEXP (src, 0)) == VIRTUAL_STACK_VARS_REGNUM)
&& CONSTANT_P (XEXP (src, 1)))
/* DEST is always the innermost thing set, except in the case of
SUBREGs of hard registers. */
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
regno = REGNO (dest), mode = GET_MODE (dest);
- else if (GET_CODE (dest) == SUBREG && GET_CODE (SUBREG_REG (dest)) == REG)
+ else if (GET_CODE (dest) == SUBREG && REG_P (SUBREG_REG (dest)))
{
regno = REGNO (SUBREG_REG (dest));
if (regno < FIRST_PSEUDO_REGISTER)
; /* Do nothing. */
else if (GET_CODE (x) == MEM)
reg_equiv_memory_loc[regno] = x;
- else if (GET_CODE (x) == REG)
+ else if (REG_P (x))
{
reg_renumber[regno] = REGNO (x);
/* Poke the regno right into regno_reg_rtx
delete_computation (our_prev);
}
else if (GET_CODE (pat) == SET
- && GET_CODE (SET_DEST (pat)) == REG)
+ && REG_P (SET_DEST (pat)))
{
int dest_regno = REGNO (SET_DEST (pat));
int dest_endregno
if (REG_NOTE_KIND (note) != REG_DEAD
/* Verify that the REG_NOTE is legitimate. */
- || GET_CODE (XEXP (note, 0)) != REG)
+ || !REG_P (XEXP (note, 0)))
continue;
delete_prior_computation (note, insn);
if (x == y)
return 1;
- if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG))
- && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG
- && GET_CODE (SUBREG_REG (y)) == REG)))
+ if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
+ && (REG_P (y) || (GET_CODE (y) == SUBREG
+ && REG_P (SUBREG_REG (y)))))
{
int reg_x = -1, reg_y = -1;
int byte_x = 0, byte_y = 0;
int
true_regnum (rtx x)
{
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
if (REGNO (x) >= FIRST_PSEUDO_REGISTER && reg_renumber[REGNO (x)] >= 0)
return reg_renumber[REGNO (x)];
{
int regno, nregs;
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
return;
regno = REGNO (reg);
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
return;
regno = REGNO (reg);
validate_equiv_mem_from_store (rtx dest, rtx set ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
{
- if ((GET_CODE (dest) == REG
+ if ((REG_P (dest)
&& reg_overlap_mentioned_p (dest, equiv_mem))
|| (GET_CODE (dest) == MEM
&& true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
if ((REG_NOTE_KIND (note) == REG_INC
|| REG_NOTE_KIND (note) == REG_DEAD)
- && GET_CODE (XEXP (note, 0)) == REG
+ && REG_P (XEXP (note, 0))
&& reg_overlap_mentioned_p (XEXP (note, 0), memref))
return 0;
}
Equivalences to MEMs should be made in another pass, after the
reg_equiv[].replace information has been gathered. */
- if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
+ if (MEM_P (dest) && REG_P (src)
&& (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
&& REG_BASIC_BLOCK (regno) >= 0
&& REG_N_SETS (regno) == 1
preferred class of a pseudo depends on all instructions that set
or use it. */
- if (GET_CODE (dest) != REG
+ if (!REG_P (dest)
|| (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
|| reg_equiv[regno].init_insns == const0_rtx
|| (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
int regno;
rtx list;
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
return;
regno = REGNO (reg);
list = reg_equiv[regno].init_insns;
hard_reg = get_hard_reg_initial_reg (cfun, r1);
if (hard_reg != NULL_RTX)
{
- if (GET_CODE (hard_reg) == REG
+ if (REG_P (hard_reg)
&& IN_RANGE (REGNO (hard_reg),
0, FIRST_PSEUDO_REGISTER - 1)
&& ! call_used_regs[REGNO (hard_reg)])
continue;
}
- if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
+ if (REG_P (r0) || GET_CODE (r0) == SUBREG)
{
/* We have two priorities for hard register preferences.
If we have a move insn or an insn whose first input
int may_save_copy
= (r1 == recog_data.operand[i] && must_match_0 >= 0);
- if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
+ if (REG_P (r1) || GET_CODE (r1) == SUBREG)
win = combine_regs (r1, r0, may_save_copy,
insn_number, insn, 0);
}
if (optimize
&& GET_CODE (PATTERN (insn)) == CLOBBER
&& (r0 = XEXP (PATTERN (insn), 0),
- GET_CODE (r0) == REG)
+ REG_P (r0))
&& (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
&& XEXP (link, 0) != 0
&& GET_CODE (XEXP (link, 0)) == INSN
&& (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
NULL_RTX)) != 0)
{
- if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
+ if (r1 = XEXP (note, 0), REG_P (r1)
/* Check that we have such a sequence. */
&& no_conflict_p (insn, r0, r1))
win = combine_regs (r1, r0, 1, insn_number, insn, 1);
else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
&& (r1 = XEXP (XEXP (note, 0), 0),
- GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
+ REG_P (r1) || GET_CODE (r1) == SUBREG)
&& no_conflict_p (insn, r0, r1))
win = combine_regs (r1, r0, 0, insn_number, insn, 1);
commutative. */
else if (COMMUTATIVE_P (XEXP (note, 0))
&& (r1 = XEXP (XEXP (note, 0), 1),
- (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
+ (REG_P (r1) || GET_CODE (r1) == SUBREG))
&& no_conflict_p (insn, r0, r1))
win = combine_regs (r1, r0, 0, insn_number, insn, 1);
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_DEAD
- && GET_CODE (XEXP (link, 0)) == REG
+ && REG_P (XEXP (link, 0))
&& combined_regno != (int) REGNO (XEXP (link, 0))
&& (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0))
|| ! find_reg_note (insn, REG_NO_CONFLICT,
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (REG_NOTE_KIND (link) == REG_UNUSED
- && GET_CODE (XEXP (link, 0)) == REG)
+ && REG_P (XEXP (link, 0)))
wipe_dead_reg (XEXP (link, 0), 1);
/* If this is an insn that has a REG_RETVAL note pointing at a
{
rtx subreg = SUBREG_REG (usedreg);
- if (GET_CODE (subreg) == REG)
+ if (REG_P (subreg))
{
if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
may_save_copy = 0;
usedreg = subreg;
}
- if (GET_CODE (usedreg) != REG)
+ if (!REG_P (usedreg))
return 0;
ureg = REGNO (usedreg);
{
rtx subreg = SUBREG_REG (setreg);
- if (GET_CODE (subreg) == REG)
+ if (REG_P (subreg))
{
if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
may_save_copy = 0;
setreg = subreg;
}
- if (GET_CODE (setreg) != REG)
+ if (!REG_P (setreg))
return 0;
sreg = REGNO (setreg);
a hard register. These may actually not exist any more. */
if (GET_CODE (reg) != SUBREG
- && GET_CODE (reg) != REG)
+ && !REG_P (reg))
return;
/* Mark this register as being born. If it is used in a CLOBBER, mark
{
rtx set = XVECEXP (PATTERN (this_insn), 0, i);
if (GET_CODE (set) == SET
- && GET_CODE (SET_DEST (set)) != REG
+ && !REG_P (SET_DEST (set))
&& !rtx_equal_p (reg, SET_DEST (set))
&& reg_overlap_mentioned_p (reg, SET_DEST (set)))
output_p = 1;
when we scan the insns that actually use it. */
if (note == 0
- || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
- || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
+ || (REG_P (r1) && REGNO (r1) < FIRST_PSEUDO_REGISTER)
+ || (GET_CODE (r1) == SUBREG && REG_P (SUBREG_REG (r1))
&& REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
return 0;
if (set)
{
lhs = SET_DEST (set);
- if (GET_CODE (lhs) != REG
+ if (!REG_P (lhs)
|| altered_reg_used (&lhs, altered))
ret = true;
}
in_libcall++;
if (! in_libcall
&& (set = single_set (p))
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
#ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& SET_DEST (set) != pic_offset_table_rtx
#endif
else if (insert_temp
&& (optimize_size
|| ! can_copy_p (GET_MODE (SET_SRC (set)))
- || GET_CODE (SET_SRC (set)) == REG
+ || REG_P (SET_SRC (set))
|| (CONSTANT_P (SET_SRC (set))
&& LEGITIMATE_CONSTANT_P (SET_SRC (set)))))
;
&& ! side_effects_p (SET_SRC (set))
&& ! find_reg_note (p, REG_RETVAL, NULL_RTX)
&& (! SMALL_REGISTER_CLASSES
- || (! (GET_CODE (SET_SRC (set)) == REG
+ || (! (REG_P (SET_SRC (set))
&& (REGNO (SET_SRC (set))
< FIRST_PSEUDO_REGISTER))))
/* This test is not redundant; SET_SRC (set) might be
&& (GET_MODE_BITSIZE (GET_MODE (m->set_dest))
>= GET_MODE_BITSIZE (GET_MODE (m1->set_dest)))))
/* See if the source of M1 says it matches M. */
- && ((GET_CODE (m1->set_src) == REG
+ && ((REG_P (m1->set_src)
&& matched_regs[REGNO (m1->set_src)])
|| rtx_equal_for_loop_p (m->set_src, m1->set_src,
movables, regs))))
/* If we have a register and a constant, they may sometimes be
equal. */
- if (GET_CODE (x) == REG && regs->array[REGNO (x)].set_in_loop == -2
+ if (REG_P (x) && regs->array[REGNO (x)].set_in_loop == -2
&& CONSTANT_P (y))
{
for (m = movables->head; m; m = m->next)
&& rtx_equal_p (m->set_src, y))
return 1;
}
- else if (GET_CODE (y) == REG && regs->array[REGNO (y)].set_in_loop == -2
+ else if (REG_P (y) && regs->array[REGNO (y)].set_in_loop == -2
&& CONSTANT_P (x))
{
for (m = movables->head; m; m = m->next)
redundant stores that we have created. */
if (GET_CODE (next) == CALL_INSN
&& GET_CODE (body) == SET
- && GET_CODE (SET_DEST (body)) == REG
+ && REG_P (SET_DEST (body))
&& (n = find_reg_note (temp, REG_EQUAL,
NULL_RTX)))
{
fn_reg = SET_SRC (body);
- if (GET_CODE (fn_reg) != REG)
+ if (!REG_P (fn_reg))
fn_reg = SET_DEST (body);
fn_address = XEXP (n, 0);
fn_address_insn = temp;
|| GET_CODE (x) == SUBREG)
x = XEXP (x, 0);
- if (GET_CODE (x) != REG || REGNO (x) < FIRST_PSEUDO_REGISTER)
+ if (!REG_P (x) || REGNO (x) < FIRST_PSEUDO_REGISTER)
return;
/* If we do not have usage information, or if we know the register
this = 0;
if (code == INSN
&& (set = single_set (p))
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) == regno)
{
this = loop_invariant_p (loop, SET_SRC (set));
in SET_DEST because if a register is partially modified, it won't
show up as a potential movable so we don't care how USAGE is set
for it. */
- if (GET_CODE (SET_DEST (x)) != REG)
+ if (!REG_P (SET_DEST (x)))
find_single_use_in_loop (regs, insn, SET_DEST (x));
find_single_use_in_loop (regs, insn, SET_SRC (x));
}
static void
count_one_set (struct loop_regs *regs, rtx insn, rtx x, rtx *last_set)
{
- if (GET_CODE (x) == CLOBBER && GET_CODE (XEXP (x, 0)) == REG)
+ if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
/* Don't move a reg that has an explicit clobber.
It's not worth the pain to try to do it correctly. */
regs->array[REGNO (XEXP (x, 0))].may_not_optimize = 1;
|| GET_CODE (dest) == SIGN_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int i;
int regno = REGNO (dest);
&& JUMP_LABEL (p) != 0
&& next_real_insn (JUMP_LABEL (p)) == next_real_insn (loop->end)
&& (test = get_condition_for_loop (loop, p)) != 0
- && GET_CODE (XEXP (test, 0)) == REG
+ && REG_P (XEXP (test, 0))
&& REGNO (XEXP (test, 0)) < max_reg_before_loop
&& (bl = REG_IV_CLASS (ivs, REGNO (XEXP (test, 0)))) != 0
&& valid_initial_value_p (XEXP (test, 1), p, call_seen, loop->start)
computational information. If not, and this is a DEST_ADDR
giv, at least we know that it's a pointer, though we don't know
the alignment. */
- if (GET_CODE (v->new_reg) == REG
+ if (REG_P (v->new_reg)
&& v->giv_type == DEST_REG
&& REG_POINTER (v->dest_reg))
mark_reg_pointer (v->new_reg,
REGNO_POINTER_ALIGN (REGNO (v->dest_reg)));
- else if (GET_CODE (v->new_reg) == REG
+ else if (REG_P (v->new_reg)
&& REG_POINTER (v->src_reg))
{
unsigned int align = REGNO_POINTER_ALIGN (REGNO (v->src_reg));
mark_reg_pointer (v->new_reg, align);
}
- else if (GET_CODE (v->new_reg) == REG
- && GET_CODE (v->add_val) == REG
+ else if (REG_P (v->new_reg)
+ && REG_P (v->add_val)
&& REG_POINTER (v->add_val))
{
unsigned int align = REGNO_POINTER_ALIGN (REGNO (v->add_val));
mark_reg_pointer (v->new_reg, align);
}
- else if (GET_CODE (v->new_reg) == REG && v->giv_type == DEST_ADDR)
+ else if (REG_P (v->new_reg) && v->giv_type == DEST_ADDR)
mark_reg_pointer (v->new_reg, 0);
if (v->giv_type == DEST_ADDR)
if (GET_CODE (p) == INSN
&& (set = single_set (p))
- && GET_CODE (SET_DEST (set)) == REG)
+ && REG_P (SET_DEST (set)))
{
dest_reg = SET_DEST (set);
if (REGNO (dest_reg) < max_reg_before_loop
/* Look for a general induction variable in a register. */
if (GET_CODE (p) == INSN
&& (set = single_set (p))
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& ! regs->array[REGNO (SET_DEST (set))].may_not_optimize)
{
rtx src_reg;
/* Only consider pseudos we know about initialized in insns whose luids
we know. */
- if (GET_CODE (x) != REG
+ if (!REG_P (x)
|| REGNO (x) >= max_reg_before_loop)
return 0;
/* Each argument must be either REG, PLUS, or MULT. Convert REG to
MULT to reduce cases. */
- if (GET_CODE (arg0) == REG)
+ if (REG_P (arg0))
arg0 = gen_rtx_MULT (mode, arg0, const1_rtx);
- if (GET_CODE (arg1) == REG)
+ if (REG_P (arg1))
arg1 = gen_rtx_MULT (mode, arg1, const1_rtx);
/* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
if (*ext_val == NULL_RTX)
{
arg0 = simplify_giv_expr (loop, XEXP (x, 0), ext_val, benefit);
- if (arg0 && *ext_val == NULL_RTX && GET_CODE (arg0) == REG)
+ if (arg0 && *ext_val == NULL_RTX && REG_P (arg0))
{
*ext_val = gen_rtx_fmt_e (GET_CODE (x), mode, arg0);
return arg0;
if (code == INSN
&& (set = single_set (p))
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& SET_DEST (set) == dest_reg
&& (general_induction_var (loop, SET_SRC (set), &src_reg,
add_val, mult_val, ext_val, 0,
{
rtx set = single_set (insn);
- if (set && GET_CODE (SET_DEST (set)) == REG)
+ if (set && REG_P (SET_DEST (set)))
record_base_value (REGNO (SET_DEST (set)), SET_SRC (set), 0);
insn = NEXT_INSN (insn);
{
rtx set = single_set (p);
- if (set && GET_CODE (SET_DEST (set)) == REG
+ if (set && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) == bl->regno)
/* An insn that sets the biv is okay. */
;
/* If this is a set of a GIV based on the reversed biv, any
REG_EQUAL notes should still be correct. */
if (! set
- || GET_CODE (SET_DEST (set)) != REG
+ || !REG_P (SET_DEST (set))
|| (size_t) REGNO (SET_DEST (set)) >= ivs->n_regs
|| REG_IV_TYPE (ivs, REGNO (SET_DEST (set))) != GENERAL_INDUCT
|| REG_IV_INFO (ivs, REGNO (SET_DEST (set)))->src_reg != bl->biv->src_reg)
rtx last = XEXP (note, 0);
rtx set = single_set (last);
- if (set && GET_CODE (SET_DEST (set)) == REG)
+ if (set && REG_P (SET_DEST (set)))
{
unsigned int regno = REGNO (SET_DEST (set));
&& (GET_CODE (v->add_val) == SYMBOL_REF
|| GET_CODE (v->add_val) == LABEL_REF
|| GET_CODE (v->add_val) == CONST
- || (GET_CODE (v->add_val) == REG
+ || (REG_P (v->add_val)
&& REG_POINTER (v->add_val))))
{
if (! biv_elimination_giv_has_0_offset (bl->biv, v, insn))
&& (GET_CODE (v->add_val) == SYMBOL_REF
|| GET_CODE (v->add_val) == LABEL_REF
|| GET_CODE (v->add_val) == CONST
- || (GET_CODE (v->add_val) == REG
+ || (REG_P (v->add_val)
&& REG_POINTER (v->add_val)))
&& ! v->ignore && ! v->maybe_dead && v->always_computable
&& v->mode == mode)
return 1;
}
}
- else if (GET_CODE (arg) == REG || GET_CODE (arg) == MEM)
+ else if (REG_P (arg) || GET_CODE (arg) == MEM)
{
if (loop_invariant_p (loop, arg) == 1)
{
#if 0
/* Otherwise the reg compared with had better be a biv. */
- if (GET_CODE (arg) != REG
+ if (!REG_P (arg)
|| REG_IV_TYPE (ivs, REGNO (arg)) != BASIC_INDUCT)
return 0;
struct loop_ivs *ivs = (struct loop_ivs *) data;
struct iv_class *bl;
- if (GET_CODE (dest) != REG
+ if (!REG_P (dest)
|| REGNO (dest) >= ivs->n_regs
|| REG_IV_TYPE (ivs, REGNO (dest)) != BASIC_INDUCT)
return;
and hence this insn will never be the last use of x.
???? This comment is not correct. See for example loop_givs_reduce.
This may insert an insn before another new insn. */
- if (GET_CODE (x) == REG && REGNO (x) < max_reg_before_loop
+ if (REG_P (x) && REGNO (x) < max_reg_before_loop
&& INSN_UID (insn) < max_uid_for_loop
&& REGNO_LAST_LUID (REGNO (x)) < INSN_LUID (insn))
{
op0 = XEXP (op0, 0);
continue;
}
- else if (GET_CODE (op0) != REG)
+ else if (!REG_P (op0))
break;
/* Go back to the previous insn. Stop if it is not an INSN. We also
rtx op, reg;
if (GET_CODE (op = XEXP (link, 0)) == USE
- && GET_CODE (reg = XEXP (op, 0)) == REG
+ && REG_P (reg = XEXP (op, 0))
&& rtx_varies_p (reg, 1))
regs->array[REGNO (reg)].may_not_optimize = 1;
}
if (set
/* @@@ This test is _way_ too conservative. */
&& ! maybe_never
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER
&& REGNO (SET_DEST (set)) < last_max_reg
&& regs->array[REGNO (SET_DEST (set))].n_times_set == 1
to untangle things for the BIV detection code. */
if (set
&& ! maybe_never
- && GET_CODE (SET_SRC (set)) == REG
+ && REG_P (SET_SRC (set))
&& REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
&& REGNO (SET_SRC (set)) < last_max_reg
&& regs->array[REGNO (SET_SRC (set))].n_times_set == 1
{
if (CONSTANT_P (equiv->loc))
const_equiv = equiv;
- else if (GET_CODE (equiv->loc) == REG
+ else if (REG_P (equiv->loc)
/* Extending hard register lifetimes causes crash
on SRC targets. Doing so on non-SRC is
probably also not good idea, since we most
/* Is this the initializing insn? */
set = single_set (insn);
if (set
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) == regno)
{
if (init_insn)
/* Search for the insn that copies REGNO to NEW_REGNO? */
if (INSN_P (insn)
&& (set = single_set (insn))
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) == new_regno
- && GET_CODE (SET_SRC (set)) == REG
+ && REG_P (SET_SRC (set))
&& REGNO (SET_SRC (set)) == regno)
break;
}
if (INSN_P (insn)
&& (prev_set = single_set (prev_insn))
- && GET_CODE (SET_DEST (prev_set)) == REG
+ && REG_P (SET_DEST (prev_set))
&& REGNO (SET_DEST (prev_set)) == regno)
{
/* We have:
{
commutative_op = 1;
- if (((target == 0 || GET_CODE (target) == REG)
- ? ((GET_CODE (op1) == REG
- && GET_CODE (op0) != REG)
+ if (((target == 0 || REG_P (target))
+ ? ((REG_P (op1)
+ && !REG_P (op0))
|| target == op1)
: rtx_equal_p (op1, target))
|| GET_CODE (op0) == CONST_INT)
xtarget = gen_reg_rtx (mode);
- if (target == 0 || GET_CODE (target) != REG)
+ if (target == 0 || !REG_P (target))
target = xtarget;
/* Indicate for flow that the entire target reg is being set. */
- if (GET_CODE (target) == REG)
+ if (REG_P (target))
emit_insn (gen_rtx_CLOBBER (VOIDmode, xtarget));
/* Do the actual arithmetic. */
/* If the target is the same as one of the inputs, don't use it. This
prevents problems with the REG_EQUAL note. */
if (target == op0 || target == op1
- || (target != 0 && GET_CODE (target) != REG))
+ || (target != 0 && !REG_P (target)))
target = 0;
/* Multiply the two lower words to get a double-word product.
And storing with a SUBREG is only possible for the least
significant part, hence we can't do it for big endian
(unless we want to permute the evaluation order. */
- if (GET_CODE (target) == REG
+ if (REG_P (target)
&& (BYTES_BIG_ENDIAN
? subsize < UNITS_PER_WORD
: ((i * subsize) % UNITS_PER_WORD) != 0))
And storing with a SUBREG is only possible for the least
significant part, hence we can't do it for big endian
(unless we want to permute the evaluation order. */
- if (GET_CODE (target) == REG
+ if (REG_P (target)
&& (BYTES_BIG_ENDIAN
? subsize < UNITS_PER_WORD
: ((i * subsize) % UNITS_PER_WORD) != 0))
/* It is safe to use the target if it is the same
as the source if this is also a pseudo register */
- if (op0 == target && GET_CODE (op0) == REG
+ if (op0 == target && REG_P (op0)
&& REGNO (op0) >= FIRST_PSEUDO_REGISTER)
safe = 1;
if (target == 0 || ! safe
|| GET_MODE (target) != mode
|| (GET_CODE (target) == MEM && MEM_VOLATILE_P (target))
- || (GET_CODE (target) == REG
+ || (REG_P (target)
&& REGNO (target) < FIRST_PSEUDO_REGISTER))
target = gen_reg_rtx (mode);
{
rtx prev, next, first, last, insn;
- if (GET_CODE (target) != REG || reload_in_progress)
+ if (!REG_P (target) || reload_in_progress)
return emit_insn (insns);
else
for (insn = insns; insn; insn = NEXT_INSN (insn))
next = NEXT_INSN (insn);
add_insn (insn);
- if (op1 && GET_CODE (op1) == REG)
+ if (op1 && REG_P (op1))
REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT, op1,
REG_NOTES (insn));
- if (op0 && GET_CODE (op0) == REG)
+ if (op0 && REG_P (op0))
REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT, op0,
REG_NOTES (insn));
}
next = NEXT_INSN (insn);
- if (set != 0 && GET_CODE (SET_DEST (set)) == REG
+ if (set != 0 && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER
&& (insn == insns
|| ((! INSN_P(insns)
/* Don't use TARGET if it isn't a register, is a hard register,
or is the wrong mode. */
- if (GET_CODE (target) != REG
+ if (!REG_P (target)
|| REGNO (target) < FIRST_PSEUDO_REGISTER
|| GET_MODE (target) != fmode)
target = gen_reg_rtx (fmode);
unsigned operand, do it in a pseudo-register. */
if (GET_MODE (to) != fmode
- || GET_CODE (to) != REG || REGNO (to) < FIRST_PSEUDO_REGISTER)
+ || !REG_P (to) || REGNO (to) < FIRST_PSEUDO_REGISTER)
target = gen_reg_rtx (fmode);
/* Convert as signed integer to floating. */
if (GET_CODE (src) == MEM
&& GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
&& (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
- && GET_CODE (SET_DEST (set)) != REG)
+ && !REG_P (SET_DEST (set)))
return 0;
#endif
/* If memory loads are cheaper than register copies, don't change them. */
if (GET_CODE (src) == MEM)
old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
- else if (GET_CODE (src) == REG)
+ else if (REG_P (src))
old_cost = REGISTER_MOVE_COST (GET_MODE (src),
REGNO_REG_CLASS (REGNO (src)), dclass);
else
#endif
this_cost = rtx_cost (this_rtx, SET);
}
- else if (GET_CODE (this_rtx) == REG)
+ else if (REG_P (this_rtx))
{
#ifdef LOAD_EXTEND_OP
if (extend_op != NIL)
tends to lead to smaller instructions on some machines. */
if (this_cost < old_cost
|| (this_cost == old_cost
- && GET_CODE (this_rtx) == REG
- && GET_CODE (SET_SRC (set)) != REG))
+ && REG_P (this_rtx)
+ && !REG_P (SET_SRC (set))))
{
#ifdef LOAD_EXTEND_OP
if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
#ifdef CANNOT_CHANGE_MODE_CLASS
/* If the register cannot change mode to word_mode, it follows that
it cannot have been used in word_mode. */
- else if (GET_CODE (SET_DEST (set)) == REG
+ else if (REG_P (SET_DEST (set))
&& CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
word_mode,
REGNO_REG_CLASS (REGNO (SET_DEST (set)))))
; /* Continue ordinary processing. */
#endif
/* If this is a straight load, make the extension explicit. */
- else if (GET_CODE (SET_DEST (set)) == REG
+ else if (REG_P (SET_DEST (set))
&& recog_data.n_operands == 2
&& SET_SRC (set) == op
&& SET_DEST (set) == recog_data.operand[1-i])
continue;
for (l = v->locs; l; l = l->next)
- if (GET_CODE (l->loc) == REG)
+ if (REG_P (l->loc))
SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
}
does not yet show whether REGY changes in this insn. */
set = single_set (insn);
if (set != NULL_RTX
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& (hard_regno_nregs[REGNO (SET_DEST (set))]
[GET_MODE (SET_DEST (set))]
== 1)
&& GET_CODE (SET_SRC (set)) == PLUS
- && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
+ && REG_P (XEXP (SET_SRC (set), 1))
&& rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
&& !rtx_equal_p (XEXP (SET_SRC (set), 1), SET_DEST (set))
&& last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
link = XEXP (link, 1))
{
rtx usage_rtx = XEXP (XEXP (link, 0), 0);
- if (GET_CODE (usage_rtx) == REG)
+ if (REG_P (usage_rtx))
{
unsigned int i;
unsigned int start_reg = REGNO (usage_rtx);
for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
{
if (REG_NOTE_KIND (note) == REG_INC
- && GET_CODE (XEXP (note, 0)) == REG)
+ && REG_P (XEXP (note, 0)))
{
int regno = REGNO (XEXP (note, 0));
GET_MODE (dst));
dst = SUBREG_REG (dst);
}
- if (GET_CODE (dst) != REG)
+ if (!REG_P (dst))
return;
regno += REGNO (dst);
switch (code)
{
case SET:
- if (GET_CODE (SET_DEST (x)) == REG)
+ if (REG_P (SET_DEST (x)))
{
reload_combine_note_use (&SET_SRC (x), insn);
return;
case USE:
/* If this is the USE of a return value, we can't change it. */
- if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
+ if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
{
/* Mark the return register as used in an unknown fashion. */
rtx reg = XEXP (x, 0);
break;
case CLOBBER:
- if (GET_CODE (SET_DEST (x)) == REG)
+ if (REG_P (SET_DEST (x)))
{
/* No spurious CLOBBERs of pseudo registers may remain. */
if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
case PLUS:
/* We are interested in (plus (reg) (const_int)) . */
- if (GET_CODE (XEXP (x, 0)) != REG
+ if (!REG_P (XEXP (x, 0))
|| GET_CODE (XEXP (x, 1)) != CONST_INT)
break;
offset = XEXP (x, 1);
/* For simplicity, we only perform this optimization on
straightforward SETs. */
if (GET_CODE (pat) == SET
- && GET_CODE (SET_DEST (pat)) == REG)
+ && REG_P (SET_DEST (pat)))
{
rtx reg = SET_DEST (pat);
int regno = REGNO (reg);
(set (REGX) (PLUS (REGX) (CONST_INT A)))
...
(set (REGX) (plus (REGX) (CONST_INT B-A))) */
- else if (GET_CODE (src) == REG
+ else if (REG_P (src)
&& reg_set_luid[regno] == reg_set_luid[REGNO (src)]
&& reg_base_reg[regno] == reg_base_reg[REGNO (src)]
&& MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
{
if (REG_NOTE_KIND (note) == REG_INC
- && GET_CODE (XEXP (note, 0)) == REG)
+ && REG_P (XEXP (note, 0)))
{
/* Reset the information about this register. */
int regno = REGNO (XEXP (note, 0));
if (cnd != NULL_RTX
&& GET_CODE (cnd) == NE
- && GET_CODE (XEXP (cnd, 0)) == REG
+ && REG_P (XEXP (cnd, 0))
/* The following two checks, which are also in
move2add_note_store, are intended to reduce the
number of calls to gen_rtx_SET to avoid memory
reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
return;
}
- if (GET_CODE (dst) != REG)
+ if (!REG_P (dst))
return;
regno += REGNO (dst);
switch (GET_CODE (src))
{
case PLUS:
- if (GET_CODE (XEXP (src, 0)) == REG)
+ if (REG_P (XEXP (src, 0)))
{
base_reg = XEXP (src, 0);
if (GET_CODE (XEXP (src, 1)) == CONST_INT)
offset = INTVAL (XEXP (src, 1));
- else if (GET_CODE (XEXP (src, 1)) == REG
+ else if (REG_P (XEXP (src, 1))
&& (reg_set_luid[REGNO (XEXP (src, 1))]
> move2add_last_label_luid)
&& (MODES_OK_FOR_MOVE2ADD
An exception is the third field of a NOTE, where it indicates
that the field has several different valid contents. */
case '0':
- if (i == 1 && GET_CODE (in_rtx) == REG)
+ if (i == 1 && REG_P (in_rtx))
{
if (REGNO (in_rtx) != ORIGINAL_REGNO (in_rtx))
fprintf (outfile, " [%d]", ORIGINAL_REGNO (in_rtx));
const char *name;
#ifndef GENERATOR_FILE
- if (GET_CODE (in_rtx) == REG && value < FIRST_PSEUDO_REGISTER)
+ if (REG_P (in_rtx) && value < FIRST_PSEUDO_REGISTER)
fprintf (outfile, " %d %s", REGNO (in_rtx),
reg_names[REGNO (in_rtx)]);
- else if (GET_CODE (in_rtx) == REG
+ else if (REG_P (in_rtx)
&& value <= LAST_VIRTUAL_REGISTER)
{
if (value == VIRTUAL_INCOMING_ARGS_REGNUM)
else
fprintf (outfile, " %d", value);
- if (GET_CODE (in_rtx) == REG && REG_ATTRS (in_rtx))
+ if (REG_P (in_rtx) && REG_ATTRS (in_rtx))
{
fputs (" [", outfile);
if (ORIGINAL_REGNO (in_rtx) != REGNO (in_rtx))
coalescing (the check for this is in remember_move() below). */
while (GET_CODE (d) == STRICT_LOW_PART)
d = XEXP (d, 0);
- if (GET_CODE (d) != REG
- && (GET_CODE (d) != SUBREG || GET_CODE (SUBREG_REG (d)) != REG))
+ if (!REG_P (d)
+ && (GET_CODE (d) != SUBREG || !REG_P (SUBREG_REG (d))))
return 0;
while (GET_CODE (s) == STRICT_LOW_PART)
s = XEXP (s, 0);
- if (GET_CODE (s) != REG
- && (GET_CODE (s) != SUBREG || GET_CODE (SUBREG_REG (s)) != REG))
+ if (!REG_P (s)
+ && (GET_CODE (s) != SUBREG || !REG_P (SUBREG_REG (s))))
return 0;
s_regno = (unsigned) REGNO (GET_CODE (s) == SUBREG ? SUBREG_REG (s) : s);
Those would be difficult to coalesce (we would need to implement
handling of all the subwebs in the allocator, including that such
subwebs could be source and target of coalescing). */
- if (GET_CODE (s) == REG && GET_CODE (d) == REG)
+ if (REG_P (s) && REG_P (d))
{
struct move *m = ra_calloc (sizeof (struct move));
struct move_list *ml;
static void
init_one_web_common (struct web *web, rtx reg)
{
- if (GET_CODE (reg) != REG)
+ if (!REG_P (reg))
abort ();
/* web->id isn't initialized here. */
web->regno = REGNO (reg);
int i;
if (GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
if (REGNO (x) >= FIRST_PSEUDO_REGISTER)
return 1;
for (i = 0; i < XVECLEN (pat, 0); i++)
{
rtx t = XVECEXP (pat, 0, i);
- if (GET_CODE (t) == CLOBBER && GET_CODE (XEXP (t, 0)) == REG
+ if (GET_CODE (t) == CLOBBER && REG_P (XEXP (t, 0))
&& REGNO (XEXP (t, 0)) < FIRST_PSEUDO_REGISTER)
SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
}
|| GET_CODE (reg) == SIGN_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART)
reg = XEXP (reg, 0);
- if (GET_CODE (reg) != REG || REGNO (reg) < FIRST_PSEUDO_REGISTER)
+ if (!REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
continue;
/* Search the web corresponding to this operand. We depend on
OSDN Git Service
