gcc/

	PR target/40697
	* optabs.c (avoid_expensive_constant): Use rtx_cost to find out
	the cost of loading the constant rather than assuming
	COSTS_N_INSNS (1).
	* config/arm/arm.c (thumb1_rtx_costs) <case CONST_INT>: If the
	outer code is AND, do the same tests as the andsi3 expander and
	return COSTS_N_INSNS (1) if and is cheap.

testsuite/
	PR target/40697
	* gcc.target/arm/thumb-andsi.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@157582 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bdc8dae..7afdbac 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -4,6 +4,14 @@
        * ira-lives.c (check_and_make_def_conflict): Ignore conflict for a
        use that may match DEF.
 
+       PR target/40697
+       * optabs.c (avoid_expensive_constant): Use rtx_cost to find out
+       the cost of loading the constant rather than assuming
+       COSTS_N_INSNS (1).
+       * config/arm/arm.c (thumb1_rtx_costs) <case CONST_INT>: If the
+       outer code is AND, do the same tests as the andsi3 expander and
+       return COSTS_N_INSNS (1) if and is cheap.
+       
 2010-03-19  Michael Matz  <matz@suse.de>
 
        PR c++/43116

diff --git a/gcc/optabs.c b/gcc/optabs.c
index a36075d..a82619e 100644 (file)
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -41,6 +41,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "recog.h"
 #include "reload.h"
 #include "ggc.h"
+#include "real.h"
 #include "basic-block.h"
 #include "target.h"
 
@@ -1389,7 +1390,6 @@ avoid_expensive_constant (enum machine_mode mode, optab binoptab,
                          rtx x, bool unsignedp)
 {
   bool speed = optimize_insn_for_speed_p ();
-
   if (mode != VOIDmode
       && optimize
       && CONSTANT_P (x)
@@ -2927,7 +2927,7 @@ expand_absneg_bit (enum rtx_code code, enum machine_mode mode,
   const struct real_format *fmt;
   int bitpos, word, nwords, i;
   enum machine_mode imode;
-  double_int mask;
+  HOST_WIDE_INT hi, lo;
   rtx temp, insns;
 
   /* The format has to have a simple sign bit.  */
@@ -2963,9 +2963,18 @@ expand_absneg_bit (enum rtx_code code, enum machine_mode mode,
       nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD;
     }
 
-  mask = double_int_setbit (double_int_zero, bitpos);
+  if (bitpos < HOST_BITS_PER_WIDE_INT)
+    {
+      hi = 0;
+      lo = (HOST_WIDE_INT) 1 << bitpos;
+    }
+  else
+    {
+      hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT);
+      lo = 0;
+    }
   if (code == ABS)
-    mask = double_int_not (mask);
+    lo = ~lo, hi = ~hi;
 
   if (target == 0 || target == op0)
     target = gen_reg_rtx (mode);
@@ -2983,7 +2992,7 @@ expand_absneg_bit (enum rtx_code code, enum machine_mode mode,
            {
              temp = expand_binop (imode, code == ABS ? and_optab : xor_optab,
                                   op0_piece,
-                                  immed_double_int_const (mask, imode),
+                                  immed_double_const (lo, hi, imode),
                                   targ_piece, 1, OPTAB_LIB_WIDEN);
              if (temp != targ_piece)
                emit_move_insn (targ_piece, temp);
@@ -3001,7 +3010,7 @@ expand_absneg_bit (enum rtx_code code, enum machine_mode mode,
     {
       temp = expand_binop (imode, code == ABS ? and_optab : xor_optab,
                           gen_lowpart (imode, op0),
-                          immed_double_int_const (mask, imode),
+                          immed_double_const (lo, hi, imode),
                           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
       target = lowpart_subreg_maybe_copy (mode, temp, imode);
 
@@ -3552,7 +3561,7 @@ expand_copysign_absneg (enum machine_mode mode, rtx op0, rtx op1, rtx target,
     }
   else
     {
-      double_int mask;
+      HOST_WIDE_INT hi, lo;
 
       if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
        {
@@ -3574,10 +3583,20 @@ expand_copysign_absneg (enum machine_mode mode, rtx op0, rtx op1, rtx target,
          op1 = operand_subword_force (op1, word, mode);
        }
 
-      mask = double_int_setbit (double_int_zero, bitpos);
+      if (bitpos < HOST_BITS_PER_WIDE_INT)
+       {
+         hi = 0;
+         lo = (HOST_WIDE_INT) 1 << bitpos;
+       }
+      else
+       {
+         hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT);
+         lo = 0;
+       }
 
+      sign = gen_reg_rtx (imode);
       sign = expand_binop (imode, and_optab, op1,
-                          immed_double_int_const (mask, imode),
+                          immed_double_const (lo, hi, imode),
                           NULL_RTX, 1, OPTAB_LIB_WIDEN);
     }
 
@@ -3621,7 +3640,7 @@ expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target,
                     int bitpos, bool op0_is_abs)
 {
   enum machine_mode imode;
-  double_int mask;
+  HOST_WIDE_INT hi, lo;
   int word, nwords, i;
   rtx temp, insns;
 
@@ -3645,7 +3664,16 @@ expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target,
       nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD;
     }
 
-  mask = double_int_setbit (double_int_zero, bitpos);
+  if (bitpos < HOST_BITS_PER_WIDE_INT)
+    {
+      hi = 0;
+      lo = (HOST_WIDE_INT) 1 << bitpos;
+    }
+  else
+    {
+      hi = (HOST_WIDE_INT) 1 << (bitpos - HOST_BITS_PER_WIDE_INT);
+      lo = 0;
+    }
 
   if (target == 0 || target == op0 || target == op1)
     target = gen_reg_rtx (mode);
@@ -3662,15 +3690,13 @@ expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target,
          if (i == word)
            {
              if (!op0_is_abs)
-               op0_piece
-                 = expand_binop (imode, and_optab, op0_piece,
-                                 immed_double_int_const (double_int_not (mask),
-                                                         imode),
-                                 NULL_RTX, 1, OPTAB_LIB_WIDEN);
+               op0_piece = expand_binop (imode, and_optab, op0_piece,
+                                         immed_double_const (~lo, ~hi, imode),
+                                         NULL_RTX, 1, OPTAB_LIB_WIDEN);
 
              op1 = expand_binop (imode, and_optab,
                                  operand_subword_force (op1, i, mode),
-                                 immed_double_int_const (mask, imode),
+                                 immed_double_const (lo, hi, imode),
                                  NULL_RTX, 1, OPTAB_LIB_WIDEN);
 
              temp = expand_binop (imode, ior_optab, op0_piece, op1,
@@ -3690,14 +3716,13 @@ expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target,
   else
     {
       op1 = expand_binop (imode, and_optab, gen_lowpart (imode, op1),
-                         immed_double_int_const (mask, imode),
+                         immed_double_const (lo, hi, imode),
                          NULL_RTX, 1, OPTAB_LIB_WIDEN);
 
       op0 = gen_lowpart (imode, op0);
       if (!op0_is_abs)
        op0 = expand_binop (imode, and_optab, op0,
-                           immed_double_int_const (double_int_not (mask),
-                                                   imode),
+                           immed_double_const (~lo, ~hi, imode),
                            NULL_RTX, 1, OPTAB_LIB_WIDEN);
 
       temp = expand_binop (imode, ior_optab, op0, op1,
@@ -6031,7 +6056,7 @@ static GTY ((param_is (union tree_node))) htab_t libfunc_decls;
 static hashval_t
 libfunc_decl_hash (const void *entry)
 {
-  return IDENTIFIER_HASH_VALUE (DECL_NAME ((const_tree) entry));
+  return htab_hash_string (IDENTIFIER_POINTER (DECL_NAME ((const_tree) entry)));
 }
 
 static int

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a13e712..6c7e19c 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -2,7 +2,10 @@
 
        PR rtl-optimization/42258
        * gcc.target/arm/thumb1-mul-moves.c: New test.
-       
+
+       PR target/40697
+       * gcc.target/arm/thumb-andsi.c: New test.
+
 2010-03-19  Michael Matz  <matz@suse.de>
 
        PR c++/43116

diff --git a/gcc/testsuite/gcc.target/arm/thumb-andsi.c b/gcc/testsuite/gcc.target/arm/thumb-andsi.c
index 992d437..9e8e4d4 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/thumb-andsi.c
+++ b/gcc/testsuite/gcc.target/arm/thumb-andsi.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mthumb -Os" }  */
-/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-options "-Os -mthumb -march=armv5te" } */
 
 unsigned get_least_bits(unsigned value)
 {