* rs6000.md (prefetch): Make address V4SI mode so that the address

        is restricted to legitimate form for instruction.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@49217 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f3a9bd7..02c75c3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2002-01-25  David Edelsohn  <edelsohn@gnu.org>
+
+       * rs6000.md (prefetch): Make address V4SI mode so that the address
+       is restricted to legitimate form for instruction.
+
 2002-01-25  Bob Wilson  <bob.wilson@acm.org>
 
        * doc/install.texi (xtensa-*-elf): New target.

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3a76293..c1a716d 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -13854,39 +13854,16 @@
   DONE;
 }")
 
-(define_expand "prefetch"
-  [(prefetch (match_operand 0 "address_operand" "p")
-            (match_operand 1 "const_int_operand" "n")
-            (match_operand 2 "const_int_operand" "n"))]
-  "TARGET_POWERPC"
-  "
-{
-  if (TARGET_32BIT)
-    emit_insn (gen_prefetchsi (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_prefetchdi (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "prefetchsi"
-  [(prefetch (match_operand:SI 0 "address_operand" "r")
+(define_insn "prefetch"
+  [(prefetch (match_operand:V4SI 0 "address_operand" "p")
             (match_operand:SI 1 "const_int_operand" "n")
             (match_operand:SI 2 "const_int_operand" "n"))]
-  "TARGET_POWERPC && TARGET_32BIT"
-  "*
-{
-  return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
-}"
-  [(set_attr "type" "load")])
-
-(define_insn "prefetchdi"
-  [(prefetch (match_operand:DI 0 "address_operand" "r")
-            (match_operand:DI 1 "const_int_operand" "n")
-            (match_operand:DI 2 "const_int_operand" "n"))]
-  "TARGET_POWERPC && TARGET_64BIT"
+  "TARGET_POWERPC"
   "*
 {
-  return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
+  if (GET_CODE (operands[0]) == REG)
+    return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
+  return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
 }"
   [(set_attr "type" "load")])
 \f