* arm.md (negdi2): Remove redundant code to force values into a

	register.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158472 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3653f88..3906f65 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
 2010-04-17  Richard Earnshaw  <rearnsha@arm.com>
 
+       * arm.md (negdi2): Remove redundant code to force values into a
+       register.
+
+2010-04-17  Richard Earnshaw  <rearnsha@arm.com>
+
        * arm/bpabi.S: Add EABI alignment attributes to objects.
        * arm/bpabi-v6m.S: Likewise.
        * arm/crti.asm: Likewise.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 2d5003b..9682ba1 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3533,17 +3533,11 @@
 
 (define_expand "negdi2"
  [(parallel
-   [(set (match_operand:DI          0 "s_register_operand" "")
-         (neg:DI (match_operand:DI 1 "s_register_operand" "")))
+   [(set (match_operand:DI 0 "s_register_operand" "")
+        (neg:DI (match_operand:DI 1 "s_register_operand" "")))
     (clobber (reg:CC CC_REGNUM))])]
   "TARGET_EITHER"
-  "
-  if (TARGET_THUMB1)
-    {
-      if (GET_CODE (operands[1]) != REG)
-        operands[1] = force_reg (DImode, operands[1]);
-     }
-  "
+  ""
 )
 
 ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
@@ -3559,8 +3553,8 @@
 )
 
 (define_insn "*thumb1_negdi2"
-  [(set (match_operand:DI         0 "register_operand" "=&l")
-       (neg:DI (match_operand:DI 1 "register_operand"   "l")))
+  [(set (match_operand:DI 0 "register_operand" "=&l")
+       (neg:DI (match_operand:DI 1 "register_operand" "l")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_THUMB1"
   "mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1"