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PR target/8812
authorwilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 11 Jun 2003 04:25:47 +0000 (04:25 +0000)
committerwilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 11 Jun 2003 04:25:47 +0000 (04:25 +0000)
* reload1.c (choose_reload_regs): For equiv reg, add loop over all
hard regs for reload_reg_used_at_all and reg_class_contents checks.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@67751 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/reload1.c

index 5035995..2fcaf5a 100644 (file)
@@ -1,3 +1,9 @@
+2003-06-10  James E Wilson  <wilson@tuliptree.org>
+
+       PR target/8812
+       * reload1.c (choose_reload_regs): For equiv reg, add loop over all
+       hard regs for reload_reg_used_at_all and reg_class_contents checks.
+
 2003-06-10  Kazu Hirata  <kazu@cs.umass.edu>
 
        * config/h8300/h8300.c (print_operand): Remove support for
index 79ce9a1..f8b3d5a 100644 (file)
@@ -5685,14 +5685,27 @@ choose_reload_regs (chain)
 
              /* If we found a spill reg, reject it unless it is free
                 and of the desired class.  */
-             if (equiv != 0
-                 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
+             if (equiv != 0)
+               {
+                 int regs_used = 0;
+                 int bad_for_class = 0;
+                 int max_regno = regno + rld[r].nregs;
+
+                 for (i = regno; i < max_regno; i++)
+                   {
+                     regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
+                                                     i);
+                     bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], 
+                                                          i);
+                   }
+
+                 if ((regs_used
                       && ! free_for_value_p (regno, rld[r].mode,
                                              rld[r].opnum, rld[r].when_needed,
                                              rld[r].in, rld[r].out, r, 1))
-                     || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
-                                             regno)))
-               equiv = 0;
+                     || bad_for_class)
+                   equiv = 0;
+               }
 
              if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
                equiv = 0;