return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
}")
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "const_int_operand" "M")))]
- "TARGET_68020 && operands[0] != operands[1] && INTVAL (operands[2]) > 8"
- "*
-{
- operands[2] = GEN_INT (32 - INTVAL (operands[2]));
- return \"bfexts %1{%#0:%b2},%0\";
-}")
-
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
}")
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "const_int_operand" "M")))]
- "TARGET_68020 && operands[0] != operands[1] && INTVAL (operands[2]) > 8"
- "*
-{
- operands[2] = GEN_INT (32 - INTVAL (operands[2]));
- return \"bfextu %1{%#0:%b2},%0\";
-}")
-
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")