gcc/
2010-11-03 H.J. Lu <hongjiu.lu@intel.com>
PR target/46295
* config/i386/i386.c (ix86_expand_vector_move): Set use_avx256_p
if 256bit AVX register is used.
gcc/testsuite/
2010-11-03 H.J. Lu <hongjiu.lu@intel.com>
PR target/46295
* gcc.target/i386/pr46295.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@166277
138bc75d-0d04-0410-961f-
82ee72b054a4
+2010-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/46295
+ * config/i386/i386.c (ix86_expand_vector_move): Set use_avx256_p
+ if 256bit AVX register is used.
+
2010-11-03 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support to use
rtx op0 = operands[0], op1 = operands[1];
unsigned int align = GET_MODE_ALIGNMENT (mode);
+ if (use_avx256_p (mode, NULL_TREE))
+ cfun->machine->use_avx256_p = true;
+
/* Force constants other than zero into memory. We do not know how
the instructions used to build constants modify the upper 64 bits
of the register, once we have that information we may be able
+2010-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/46295
+ * gcc.target/i386/pr46295.c: New.
+
2010-11-03 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-sfminmax.c: New test for using double
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx -mtune=generic -dp" } */
+
+typedef double EXPRESS[5];
+void Parse_Rel_Factor (EXPRESS Express,int *Terms);
+void Parse_Vector ()
+{
+ EXPRESS Express;
+ int Terms;
+ for (Terms = 0; Terms < 5; Terms++)
+ Express[Terms] = 0.0;
+ Parse_Rel_Factor(Express,&Terms);
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */