gcc/

	PR rtl-optimization/43358
	* ira-lives.c (process_single_reg_class_operands): Adjust the costs
	of a single hard register, using simplify_subreg_regno to decide
	what that register should be.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@163249 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cd1ed69..3987c90 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2010-08-14  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       PR rtl-optimization/43358
+       * ira-lives.c (process_single_reg_class_operands): Adjust the costs
+       of a single hard register, using simplify_subreg_regno to decide
+       what that register should be.
+
 2010-08-14  Mingjie Xing  <mingjie.xing@gmail.com>
 
        * config/mips/mips.c (CODE_FOR_loongson_pmullh): Define.

diff --git a/gcc/ira-lives.c b/gcc/ira-lives.c
index 1ffed78..b189698 100644 (file)
--- a/gcc/ira-lives.c
+++ b/gcc/ira-lives.c
@@ -897,7 +897,7 @@ ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set)
 static void
 process_single_reg_class_operands (bool in_p, int freq)
 {
-  int i, regno, cost;
+  int i, regno;
   unsigned int px;
   enum reg_class cl;
   rtx operand;
@@ -924,32 +924,46 @@ process_single_reg_class_operands (bool in_p, int freq)
       if (REG_P (operand)
          && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
        {
-         enum machine_mode mode;
          enum reg_class cover_class;
 
          operand_a = ira_curr_regno_allocno_map[regno];
-         mode = ALLOCNO_MODE (operand_a);
          cover_class = ALLOCNO_COVER_CLASS (operand_a);
          if (ira_class_subset_p[cl][cover_class]
-             && ira_class_hard_regs_num[cl] != 0
-             && (ira_class_hard_reg_index[cover_class]
-                 [ira_class_hard_regs[cl][0]]) >= 0
-             && reg_class_size[cl] <= (unsigned) CLASS_MAX_NREGS (cl, mode))
+             && ira_class_hard_regs_num[cl] != 0)
            {
-             int i, size;
-             cost
-               = (freq
-                  * (in_p
-                     ? ira_get_register_move_cost (mode, cover_class, cl)
-                     : ira_get_register_move_cost (mode, cl, cover_class)));
-             ira_allocate_and_set_costs
-               (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), cover_class, 0);
-             size = ira_reg_class_nregs[cover_class][mode];
-             for (i = 0; i < size; i++)
-               ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
-                 [ira_class_hard_reg_index
-                  [cover_class][ira_class_hard_regs[cl][i]]]
-                 -= cost;
+             /* View the desired allocation of OPERAND as:
+
+                   (REG:YMODE YREGNO),
+
+                a simplification of:
+
+                   (subreg:YMODE (reg:XMODE XREGNO) OFFSET).  */
+             enum machine_mode ymode, xmode;
+             int xregno, yregno;
+             HOST_WIDE_INT offset;
+
+             xmode = recog_data.operand_mode[i];
+             xregno = ira_class_hard_regs[cl][0];
+             ymode = ALLOCNO_MODE (operand_a);
+             offset = subreg_lowpart_offset (ymode, xmode);
+             yregno = simplify_subreg_regno (xregno, xmode, offset, ymode);
+             if (yregno >= 0
+                 && ira_class_hard_reg_index[cover_class][yregno] >= 0)
+               {
+                 int cost;
+
+                 ira_allocate_and_set_costs
+                   (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a),
+                    cover_class, 0);
+                 cost
+                   = (freq
+                      * (in_p
+                         ? ira_get_register_move_cost (xmode, cover_class, cl)
+                         : ira_get_register_move_cost (xmode, cl,
+                                                       cover_class)));
+                 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
+                   [ira_class_hard_reg_index[cover_class][yregno]] -= cost;
+               }
            }
        }