PR target/33151

        * config/rs6000/predicates.md (offsettable_mem_operand): Memory
        operand without auto-inc-dec.
        * config/rs6000/rs6000.md (floatsidf2_internal): Use
        offsettable_mem_operand.
        (floatunssidf2_internal): Same.
        (fix_truncdfsi2_internal): Same.
        (floatsidf_ppc64): Same.
        (floatunssidf_ppc64): Same.
        (fix_trunctfsi2_internal): Same.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@127807 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4c4c054..1b834ba 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2007-08-26  David Edelsohn  <edelsohn@gnu.org>
+
+       PR target/33151
+       * config/rs6000/predicates.md (offsettable_mem_operand): Memory
+       operand without auto-inc-dec.
+       * config/rs6000/rs6000.md (floatsidf2_internal): Use
+       offsettable_mem_operand.
+       (floatunssidf2_internal): Same.
+       (fix_truncdfsi2_internal): Same.
+       (floatsidf_ppc64): Same.
+       (floatunssidf_ppc64): Same.
+       (fix_trunctfsi2_internal): Same.
+

 2007-08-26  Bernhard Fischer  <aldot@gcc.gnu.org>
 
        PR bootstrap/30620
 2007-08-26  Bernhard Fischer  <aldot@gcc.gnu.org>
 
        PR bootstrap/30620

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 877aa16..f56c176 100644 (file)
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -349,10 +349,10 @@
 
 ;; Return 1 if the operand is an offsettable memory operand.
 (define_predicate "offsettable_mem_operand"
 
 ;; Return 1 if the operand is an offsettable memory operand.
 (define_predicate "offsettable_mem_operand"

-  (and (match_code "mem")
-       (match_test "offsettable_address_p (reload_completed
-                                          || reload_in_progress,
-                                          mode, XEXP (op, 0))")))
+  (and (match_operand 0 "memory_operand")
+       (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC
+                   && GET_CODE (XEXP (op, 0)) != PRE_DEC
+                   && GET_CODE (XEXP (op, 0)) != PRE_MODIFY")))

 
 ;; Return 1 if the operand is a memory operand with an address divisible by 4
 (define_predicate "word_offset_memref_operand"
 
 ;; Return 1 if the operand is a memory operand with an address divisible by 4
 (define_predicate "word_offset_memref_operand"

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c9eccdd..4bc7112 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5821,7 +5821,7 @@
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
    (use (match_operand:SI 2 "gpc_reg_operand" "r"))
    (use (match_operand:DF 3 "gpc_reg_operand" "f"))
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
    (use (match_operand:SI 2 "gpc_reg_operand" "r"))
    (use (match_operand:DF 3 "gpc_reg_operand" "f"))

-   (clobber (match_operand:DF 4 "memory_operand" "=o"))
+   (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))

    (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
    (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
    (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
    (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"


@@ -5892,7 +5892,7 @@
        (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
    (use (match_operand:SI 2 "gpc_reg_operand" "r"))
    (use (match_operand:DF 3 "gpc_reg_operand" "f"))
        (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
    (use (match_operand:SI 2 "gpc_reg_operand" "r"))
    (use (match_operand:DF 3 "gpc_reg_operand" "f"))

-   (clobber (match_operand:DF 4 "memory_operand" "=o"))
+   (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))

    (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
   "#"
    (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
   "#"


@@ -5959,7 +5959,7 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
    (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
    (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))

-   (clobber (match_operand:DI 3 "memory_operand" "=o"))]
+   (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]

   "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
   "#"
   "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
   "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
   "#"
   "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"


@@ -6112,7 +6112,7 @@
 (define_insn_and_split "floatsidf_ppc64"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
 (define_insn_and_split "floatsidf_ppc64"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))

-   (clobber (match_operand:DI 2 "memory_operand" "=o"))
+   (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))

    (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
    (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
   "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
    (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
    (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
   "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"


@@ -6127,7 +6127,7 @@
 (define_insn_and_split "floatunssidf_ppc64"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
        (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
 (define_insn_and_split "floatunssidf_ppc64"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
        (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))

-   (clobber (match_operand:DI 2 "memory_operand" "=o"))
+   (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))

    (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
    (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
    (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
    (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"


@@ -8800,7 +8800,7 @@
    (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
    (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
    (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
    (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
    (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
    (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))

-   (clobber (match_operand:DI 5 "memory_operand" "=o"))]
+   (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]

   "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "#"
   "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "#"