Backport from mainline
2012-08-27 Walter Lee <walt@tilera.com>
* doc/md.texi (TILE-Gx): Fix typo.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@190730
138bc75d-0d04-0410-961f-
82ee72b054a4
Backport from mainline
2012-08-27 Walter Lee <walt@tilera.com>
+ * doc/md.texi (TILE-Gx): Fix typo.
+
+2012-08-27 Walter Lee <walt@tilera.com>
+
+ Backport from mainline
+ 2012-08-27 Walter Lee <walt@tilera.com>
+
* config/tilegx/tilegx.c (tilegx_function_profiler): Fix typo.
config/tilepro/tilepro.c (tilepro_function_profiler): Ditto.
@itemx R07
@itemx R08
@itemx R09
-@itemx R010
+@itemx R10
Each of these represents a register constraint for an individual
register, from r0 to r10.
@itemx R07
@itemx R08
@itemx R09
-@itemx R010
+@itemx R10
Each of these represents a register constraint for an individual
register, from r0 to r10.