OSDN Git Service

From Jie Zhang <jie.zhang@analog.com>:
authorbernds <bernds@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 7 Sep 2009 21:40:23 +0000 (21:40 +0000)
committerbernds <bernds@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 7 Sep 2009 21:40:23 +0000 (21:40 +0000)
* config/bfin/predicates.md (p_register_operand): New
predicate.
(dp_register_operand): New predicate.
* config/bfin/bfin-protos.h (WA_05000074): Define.
(ENABLE_WA_05000074): Define.
* config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
all cpus.
(bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
* config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
(define_attr addrtype): Allow load/store register to be
P register.
(define_attr storereg): New.
(define_cpu_unit anomaly_05000074): New.
(define_insn_reservation dsp32shiftimm): New.
(define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
(define_insn_reservation loadp): Cannot use slot2.
(define_insn_reservation loadsp): Cannot use slot2.
(define_insn_reservation storep): Cannot use slot2. Does not
apply when working around 05000074.
(define_insn_reservation storep_anomaly_05000074): New.
(define_insn_reservation storei): Does not apply when working
around 05000074.
(define_insn_reservation storei_anomaly_05000074): New.
(define_attr length): Add dsp32shiftimm case.
(define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
Set type as dsp32shiftimm for dsp32shiftimm alternatives.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@151490 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/bfin/bfin-protos.h
gcc/config/bfin/bfin.c
gcc/config/bfin/bfin.md
gcc/config/bfin/predicates.md

index e0a11b3..66c0c14 100644 (file)
        * doc/invoke.texi (Blackfin Options): Document that -mcpu now accepts
        bf542m, bf544m, bf547m, bf548m, and bf549m.
 
+       From Jie Zhang <jie.zhang@analog.com>:
+       * config/bfin/predicates.md (p_register_operand): New
+       predicate.
+       (dp_register_operand): New predicate.
+       * config/bfin/bfin-protos.h (WA_05000074): Define.
+       (ENABLE_WA_05000074): Define.
+       * config/bfin/bfin.c (bfin_cpus[]): Add WA_05000074 for
+       all cpus.
+       (bfin_gen_bundles): Put dsp32shiftimm instruction in slot[0].
+       * config/bfin/bfin.md (define_attr type): Add dsp32shiftimm.
+       (define_attr addrtype): Allow load/store register to be
+       P register.
+       (define_attr storereg): New.
+       (define_cpu_unit anomaly_05000074): New.
+       (define_insn_reservation dsp32shiftimm): New.
+       (define_insn_reservation dsp32shiftimm_anomaly_05000074): New.
+       (define_insn_reservation loadp): Cannot use slot2.
+       (define_insn_reservation loadsp): Cannot use slot2.
+       (define_insn_reservation storep): Cannot use slot2. Does not
+       apply when working around 05000074.
+       (define_insn_reservation storep_anomaly_05000074): New.
+       (define_insn_reservation storei): Does not apply when working
+       around 05000074.
+       (define_insn_reservation storei_anomaly_05000074): New.
+       (define_attr length): Add dsp32shiftimm case.
+       (define_insn movsi_insn32, movsi_insv, ashlsi3_insn, ashrsi3,
+       ror_one, rol_one, lshrsi3, lshrpdi3, ashrpdi3, movhiv2hi_low,
+       movhiv2hi_high, composev2hi, packv2hi, movv2hi_hi,
+       ssashiftv2hi3, ssashifthi3, ssashiftsi3, lshiftv2hi3, lshifthi3):
+       Set type as dsp32shiftimm for dsp32shiftimm alternatives.
+
 2009-09-07  Martin Jambor  <mjambor@suse.cz>
 
        PR middle-end/41282
index 4a96cf1..b2d3d8c 100644 (file)
 #define ENABLE_WA_LOAD_LCREGS \
   (bfin_workarounds & WA_LOAD_LCREGS)
 
+#define WA_05000074 0x00000100
+#define ENABLE_WA_05000074 \
+  (bfin_workarounds & WA_05000074)
+
 #define Mmode enum machine_mode
 
 extern rtx function_arg (CUMULATIVE_ARGS *, Mmode, tree, int);
index 2b7fde6..e523680 100644 (file)
@@ -117,199 +117,223 @@ struct bfin_cpu
 struct bfin_cpu bfin_cpus[] =
 {
   {"bf512", BFIN_CPU_BF512, 0x0000,
-   WA_SPECULATIVE_LOADS},
+   WA_SPECULATIVE_LOADS | WA_05000074},
 
   {"bf514", BFIN_CPU_BF514, 0x0000,
-   WA_SPECULATIVE_LOADS},
+   WA_SPECULATIVE_LOADS | WA_05000074},
 
   {"bf516", BFIN_CPU_BF516, 0x0000,
-   WA_SPECULATIVE_LOADS},
+   WA_SPECULATIVE_LOADS | WA_05000074},
 
   {"bf518", BFIN_CPU_BF518, 0x0000,
-   WA_SPECULATIVE_LOADS},
+   WA_SPECULATIVE_LOADS | WA_05000074},
 
   {"bf522", BFIN_CPU_BF522, 0x0002,
-   WA_SPECULATIVE_LOADS},
+   WA_SPECULATIVE_LOADS | WA_05000074},
   {"bf522", BFIN_CPU_BF522, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
   {"bf522", BFIN_CPU_BF522, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
 
   {"bf523", BFIN_CPU_BF523, 0x0002,
-   WA_SPECULATIVE_LOADS},
+   WA_SPECULATIVE_LOADS | WA_05000074},
   {"bf523", BFIN_CPU_BF523, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
   {"bf523", BFIN_CPU_BF523, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
 
   {"bf524", BFIN_CPU_BF524, 0x0002,
-   WA_SPECULATIVE_LOADS},
+   WA_SPECULATIVE_LOADS | WA_05000074},
   {"bf524", BFIN_CPU_BF524, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
   {"bf524", BFIN_CPU_BF524, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
 
   {"bf525", BFIN_CPU_BF525, 0x0002,
-   WA_SPECULATIVE_LOADS},
+   WA_SPECULATIVE_LOADS | WA_05000074},
   {"bf525", BFIN_CPU_BF525, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
   {"bf525", BFIN_CPU_BF525, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
 
   {"bf526", BFIN_CPU_BF526, 0x0002,
-   WA_SPECULATIVE_LOADS},
+   WA_SPECULATIVE_LOADS | WA_05000074},
   {"bf526", BFIN_CPU_BF526, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
   {"bf526", BFIN_CPU_BF526, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
 
   {"bf527", BFIN_CPU_BF527, 0x0002,
-   WA_SPECULATIVE_LOADS},
+   WA_SPECULATIVE_LOADS | WA_05000074},
   {"bf527", BFIN_CPU_BF527, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
   {"bf527", BFIN_CPU_BF527, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000074},
 
   {"bf531", BFIN_CPU_BF531, 0x0006,
-   WA_SPECULATIVE_LOADS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_LOAD_LCREGS | WA_05000074},
   {"bf531", BFIN_CPU_BF531, 0x0005,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000283 | WA_05000315 | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000283 | WA_05000315
+   | WA_LOAD_LCREGS | WA_05000074},
   {"bf531", BFIN_CPU_BF531, 0x0004,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
   {"bf531", BFIN_CPU_BF531, 0x0003,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf532", BFIN_CPU_BF532, 0x0006,
-   WA_SPECULATIVE_LOADS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_LOAD_LCREGS | WA_05000074},
   {"bf532", BFIN_CPU_BF532, 0x0005,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000283 | WA_05000315 | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000283 | WA_05000315
+   | WA_LOAD_LCREGS | WA_05000074},
   {"bf532", BFIN_CPU_BF532, 0x0004,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
   {"bf532", BFIN_CPU_BF532, 0x0003,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf533", BFIN_CPU_BF533, 0x0006,
-   WA_SPECULATIVE_LOADS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_LOAD_LCREGS | WA_05000074},
   {"bf533", BFIN_CPU_BF533, 0x0005,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000283 | WA_05000315 | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_05000283 | WA_05000315
+   | WA_LOAD_LCREGS | WA_05000074},
   {"bf533", BFIN_CPU_BF533, 0x0004,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
   {"bf533", BFIN_CPU_BF533, 0x0003,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf534", BFIN_CPU_BF534, 0x0003,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_LOAD_LCREGS | WA_05000074},
   {"bf534", BFIN_CPU_BF534, 0x0002,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
   {"bf534", BFIN_CPU_BF534, 0x0001,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf536", BFIN_CPU_BF536, 0x0003,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_LOAD_LCREGS | WA_05000074},
   {"bf536", BFIN_CPU_BF536, 0x0002,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
   {"bf536", BFIN_CPU_BF536, 0x0001,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf537", BFIN_CPU_BF537, 0x0003,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_LOAD_LCREGS | WA_05000074},
   {"bf537", BFIN_CPU_BF537, 0x0002,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
   {"bf537", BFIN_CPU_BF537, 0x0001,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf538", BFIN_CPU_BF538, 0x0005,
-   WA_SPECULATIVE_LOADS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_LOAD_LCREGS | WA_05000074},
   {"bf538", BFIN_CPU_BF538, 0x0004,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_LOAD_LCREGS | WA_05000074},
   {"bf538", BFIN_CPU_BF538, 0x0003,
    WA_SPECULATIVE_LOADS | WA_RETS
-   | WA_05000283 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000315 | WA_LOAD_LCREGS | WA_05000074},
   {"bf538", BFIN_CPU_BF538, 0x0002,
    WA_SPECULATIVE_LOADS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf539", BFIN_CPU_BF539, 0x0005,
-   WA_SPECULATIVE_LOADS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_LOAD_LCREGS | WA_05000074},
   {"bf539", BFIN_CPU_BF539, 0x0004,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_LOAD_LCREGS | WA_05000074},
   {"bf539", BFIN_CPU_BF539, 0x0003,
    WA_SPECULATIVE_LOADS | WA_RETS
-   | WA_05000283 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000315 | WA_LOAD_LCREGS | WA_05000074},
   {"bf539", BFIN_CPU_BF539, 0x0002,
    WA_SPECULATIVE_LOADS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf542m", BFIN_CPU_BF542M, 0x0003,
-   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_05000074},
 
   {"bf542", BFIN_CPU_BF542, 0x0002,
-   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_05000074},
   {"bf542", BFIN_CPU_BF542, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_05000074},
   {"bf542", BFIN_CPU_BF542, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf544m", BFIN_CPU_BF544M, 0x0003,
-   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_05000074},
 
   {"bf544", BFIN_CPU_BF544, 0x0002,
-   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_05000074},
   {"bf544", BFIN_CPU_BF544, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_05000074},
   {"bf544", BFIN_CPU_BF544, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf547m", BFIN_CPU_BF547M, 0x0003,
-   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_05000074},
 
   {"bf547", BFIN_CPU_BF547, 0x0002,
-   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_05000074},
   {"bf547", BFIN_CPU_BF547, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_05000074},
   {"bf547", BFIN_CPU_BF547, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf548m", BFIN_CPU_BF548M, 0x0003,
-   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_05000074},
 
   {"bf548", BFIN_CPU_BF548, 0x0002,
-   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_05000074},
   {"bf548", BFIN_CPU_BF548, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_05000074},
   {"bf548", BFIN_CPU_BF548, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf549m", BFIN_CPU_BF549M, 0x0003,
-   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_05000074},
 
   {"bf549", BFIN_CPU_BF549, 0x0002,
-   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_05000074},
   {"bf549", BFIN_CPU_BF549, 0x0001,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_05000074},
   {"bf549", BFIN_CPU_BF549, 0x0000,
-   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_LOAD_LCREGS},
+   WA_SPECULATIVE_LOADS | WA_RETS | WA_INDIRECT_CALLS | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {"bf561", BFIN_CPU_BF561, 0x0005, WA_RETS
-   | WA_05000283 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000315 | WA_LOAD_LCREGS | WA_05000074},
   {"bf561", BFIN_CPU_BF561, 0x0003,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
   {"bf561", BFIN_CPU_BF561, 0x0002,
    WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
-   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS},
+   | WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
+   | WA_05000074},
 
   {NULL, 0, 0, 0}
 };
@@ -4812,7 +4836,7 @@ bfin_gen_bundles (void)
                }
              else
                {
-                 if (type == TYPE_DSP32)
+                 if (type == TYPE_DSP32 || type == TYPE_DSP32SHIFTIMM)
                    slot[0] = insn;
                  else if (slot[1] == NULL_RTX)
                    slot[1] = insn;
index ba93214..74c7a0a 100644 (file)
    (MACFLAG_IH 11)])
 
 (define_attr "type"
-  "move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy,stall"
+  "move,movcc,mvi,mcld,mcst,dsp32,dsp32shiftimm,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy,stall"
   (const_string "misc"))
 
 (define_attr "addrtype" "32bit,preg,spreg,ireg"
   (cond [(and (eq_attr "type" "mcld")
-             (and (match_operand 0 "d_register_operand" "")
+             (and (match_operand 0 "dp_register_operand" "")
                   (match_operand 1 "mem_p_address_operand" "")))
           (const_string "preg")
         (and (eq_attr "type" "mcld")
-             (and (match_operand 0 "d_register_operand" "")
+             (and (match_operand 0 "dp_register_operand" "")
                   (match_operand 1 "mem_spfp_address_operand" "")))
           (const_string "spreg")
         (and (eq_attr "type" "mcld")
-             (and (match_operand 0 "d_register_operand" "")
+             (and (match_operand 0 "dp_register_operand" "")
                   (match_operand 1 "mem_i_address_operand" "")))
           (const_string "ireg")
         (and (eq_attr "type" "mcst")
-             (and (match_operand 1 "d_register_operand" "")
+             (and (match_operand 1 "dp_register_operand" "")
                   (match_operand 0 "mem_p_address_operand" "")))
           (const_string "preg")
         (and (eq_attr "type" "mcst")
-             (and (match_operand 1 "d_register_operand" "")
+             (and (match_operand 1 "dp_register_operand" "")
                   (match_operand 0 "mem_spfp_address_operand" "")))
           (const_string "spreg")
         (and (eq_attr "type" "mcst")
-             (and (match_operand 1 "d_register_operand" "")
+             (and (match_operand 1 "dp_register_operand" "")
                   (match_operand 0 "mem_i_address_operand" "")))
           (const_string "ireg")]
        (const_string "32bit")))
 
+(define_attr "storereg" "preg,other"
+  (cond [(and (eq_attr "type" "mcst")
+             (match_operand 1 "p_register_operand" ""))
+          (const_string "preg")]
+       (const_string "other")))
+
 ;; Scheduling definitions
 
 (define_automaton "bfin")
 ;; branch.
 (define_cpu_unit "load" "bfin")
 
+;; A logical unit used to work around anomaly 05000074.
+(define_cpu_unit "anomaly_05000074" "bfin")
+
 (define_reservation "core" "slot0+slot1+slot2")
 
 (define_insn_reservation "alu" 1
   (eq_attr "type" "dsp32")
   "slot0")
 
+(define_insn_reservation "dsp32shiftimm" 1
+  (and (eq_attr "type" "dsp32shiftimm")
+       (eq (symbol_ref "ENABLE_WA_05000074")
+          (const_int 0)))
+  "slot0")
+
+(define_insn_reservation "dsp32shiftimm_anomaly_05000074" 1
+  (and (eq_attr "type" "dsp32shiftimm")
+       (ne (symbol_ref "ENABLE_WA_05000074")
+          (const_int 0)))
+  "slot0+anomaly_05000074")
+
 (define_insn_reservation "load32" 1
   (and (not (eq_attr "seq_insns" "multi"))
        (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit")))
 (define_insn_reservation "loadp" 1
   (and (not (eq_attr "seq_insns" "multi"))
        (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg")))
-  "(slot1|slot2)+pregs+load")
+  "slot1+pregs+load")
 
 (define_insn_reservation "loadsp" 1
   (and (not (eq_attr "seq_insns" "multi"))
        (and (eq_attr "type" "mcld") (eq_attr "addrtype" "spreg")))
-  "(slot1|slot2)+pregs")
+  "slot1+pregs")
 
 (define_insn_reservation "loadi" 1
   (and (not (eq_attr "seq_insns" "multi"))
   "core")
 
 (define_insn_reservation "storep" 1
-  (and (not (eq_attr "seq_insns" "multi"))
-       (and (eq_attr "type" "mcst")
-           (ior (eq_attr "addrtype" "preg") (eq_attr "addrtype" "spreg"))))
-  "(slot1|slot2)+pregs+store")
+  (and (and (not (eq_attr "seq_insns" "multi"))
+           (and (eq_attr "type" "mcst")
+                (ior (eq_attr "addrtype" "preg")
+                     (eq_attr "addrtype" "spreg"))))
+       (ior (eq (symbol_ref "ENABLE_WA_05000074")
+               (const_int 0))
+           (eq_attr "storereg" "other")))
+  "slot1+pregs+store")
+
+(define_insn_reservation "storep_anomaly_05000074" 1
+  (and (and (not (eq_attr "seq_insns" "multi"))
+           (and (eq_attr "type" "mcst")
+                (ior (eq_attr "addrtype" "preg")
+                     (eq_attr "addrtype" "spreg"))))
+       (and (ne (symbol_ref "ENABLE_WA_05000074")
+               (const_int 0))
+           (eq_attr "storereg" "preg")))
+  "slot1+anomaly_05000074+pregs+store")
 
 (define_insn_reservation "storei" 1
-  (and (not (eq_attr "seq_insns" "multi"))
-       (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
+  (and (and (not (eq_attr "seq_insns" "multi"))
+           (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
+       (ior (eq (symbol_ref "ENABLE_WA_05000074")
+               (const_int 0))
+           (eq_attr "storereg" "other")))
   "(slot1|slot2)+store")
 
+(define_insn_reservation "storei_anomaly_05000074" 1
+  (and (and (not (eq_attr "seq_insns" "multi"))
+           (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
+       (and (ne (symbol_ref "ENABLE_WA_05000074")
+               (const_int 0))
+           (eq_attr "storereg" "preg")))
+  "((slot1+anomaly_05000074)|slot2)+store")
+
 (define_insn_reservation "multi" 2
   (eq_attr "seq_insns" "multi")
   "core")
         (eq_attr "type" "move") (const_int 2)
 
         (eq_attr "type" "dsp32") (const_int 4)
+        (eq_attr "type" "dsp32shiftimm") (const_int 4)
         (eq_attr "type" "call")  (const_int 4)
 
          (eq_attr "type" "br")
  "@
    %0 = ROT %1 BY 0%!
    %0 = %0 -|- %0%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32shiftimm,dsp32")])
 
 (define_split
   [(set (match_operand:SI 0 "d_register_operand" "")
   "@
    %d0 = %h1 << 0%!
    %d0 = %1;"
-  [(set_attr "type" "dsp32,mvi")])
+  [(set_attr "type" "dsp32shiftimm,mvi")])
 
 (define_expand "insv"
   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
   [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2)))
    (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
   "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);"
-  [(set_attr "type" "shft,dsp32,shft,shft,*")])
+  [(set_attr "type" "shft,dsp32shiftimm,shft,shft,*")])
 
 (define_insn "ashrsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
   "@
    %0 >>>= %2;
    %0 = %1 >>> %2%!"
-  [(set_attr "type" "shft,dsp32")])
+  [(set_attr "type" "shft,dsp32shiftimm")])
 
 (define_insn "rotl16"
   [(set (match_operand:SI 0 "register_operand" "=d")
        (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))]
   ""
   "%0 = ROT %1 BY -1%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32shiftimm")])
 
 (define_insn "rol_one"
   [(set (match_operand:SI 0 "register_operand" "+d")
        (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))]
   ""
   "%0 = ROT %1 BY 1%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32shiftimm")])
 
 (define_expand "lshrdi3"
   [(set (match_operand:DI 0 "register_operand" "")
    %0 >>= %2;
    %0 = %1 >> %2%!
    %0 = %1 >> %2;"
-  [(set_attr "type" "shft,dsp32,shft")])
+  [(set_attr "type" "shft,dsp32shiftimm,shft")])
 
 (define_insn "lshrpdi3"
   [(set (match_operand:PDI 0 "register_operand" "=e")
                      (match_operand:SI 2 "nonmemory_operand" "Ku5")))]
   ""
   "%0 = %1 >> %2%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32shiftimm")])
 
 (define_insn "ashrpdi3"
   [(set (match_operand:PDI 0 "register_operand" "=e")
                      (match_operand:SI 2 "nonmemory_operand" "Ku5")))]
   ""
   "%0 = %1 >>> %2%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32shiftimm")])
 
 ;; A pattern to reload the equivalent of
 ;;   (set (Dreg) (plus (FP) (large_constant)))
                        (parallel [(const_int 1)]))))]
   ""
   "%h0 = %h2 << 0%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32shiftimm")])
 
 (define_insn "movhiv2hi_high"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
         (match_operand:HI 2 "register_operand" "d")))]
   ""
   "%d0 = %h2 << 0%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32shiftimm")])
 
 ;; No earlyclobber on alternative two since our sequence ought to be safe.
 ;; The order of operands is intentional to match the VDSP builtin (high word
         (match_dup 2)
         (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))]
   ""
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32shiftimm")])
 
 ; Like composev2hi, but operating on elements of V2HI vectors.
 ; Useful on its own, and as a combiner bridge for the multiply and
    %0 = PACK (%h2,%d1)%!
    %0 = PACK (%d2,%h1)%!
    %0 = PACK (%d2,%d1)%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32shiftimm,dsp32,dsp32,dsp32,dsp32")])
 
 (define_insn "movv2hi_hi"
   [(set (match_operand:HI 0 "register_operand" "=d,d,d")
    /* optimized out */
    %h0 = %h1 << 0%!
    %h0 = %d1 << 0%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32shiftimm")])
 
 (define_expand "movv2hi_hi_low"
   [(set (match_operand:HI 0 "register_operand" "")
    %0 = ASHIFT %1 BY %h2 (V, S)%!
    %0 = %1 << %2 (V,S)%!
    %0 = %1 >>> %N2 (V,S)%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
 
 (define_insn "ssashifthi3"
   [(set (match_operand:HI 0 "register_operand" "=d,d,d")
    %0 = ASHIFT %1 BY %h2 (V, S)%!
    %0 = %1 << %2 (V,S)%!
    %0 = %1 >>> %N2 (V,S)%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
 
 (define_insn "ssashiftsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
    %0 = ASHIFT %1 BY %h2 (S)%!
    %0 = %1 << %2 (S)%!
    %0 = %1 >>> %N2 (S)%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
 
 (define_insn "lshiftv2hi3"
   [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
    %0 = LSHIFT %1 BY %h2 (V)%!
    %0 = %1 << %2 (V)%!
    %0 = %1 >> %N2 (V)%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
 
 (define_insn "lshifthi3"
   [(set (match_operand:HI 0 "register_operand" "=d,d,d")
    %0 = LSHIFT %1 BY %h2 (V)%!
    %0 = %1 << %2 (V)%!
    %0 = %1 >> %N2 (V)%!"
-  [(set_attr "type" "dsp32")])
+  [(set_attr "type" "dsp32,dsp32shiftimm,dsp32shiftimm")])
 
 ;; Load without alignment exception (masking off low bits)
 
index 37d1372..84bf591 100644 (file)
   (and (match_code "reg")
        (match_test "D_REGNO_P (REGNO (op))")))
 
+(define_predicate "p_register_operand"
+  (and (match_code "reg")
+       (match_test "P_REGNO_P (REGNO (op))")))
+
+(define_predicate "dp_register_operand"
+  (and (match_code "reg")
+       (match_test "D_REGNO_P (REGNO (op)) || P_REGNO_P (REGNO (op))")))
+
 ;; Return nonzero if OP is a LC register.
 (define_predicate "lc_register_operand"
   (and (match_code "reg")