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PR target/23816
authorrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 13 Sep 2005 19:02:04 +0000 (19:02 +0000)
committerrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 13 Sep 2005 19:02:04 +0000 (19:02 +0000)
        * config/i386/sse.md (*ieee_sminv4sf3, *ieee_smaxv4sf3)
        (*ieee_sminv2df3, *ieee_smaxv2df3): New insn patterns.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@104236 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/i386/sse.md
gcc/testsuite/gcc.dg/vect/pr23816-1.c [new file with mode: 0644]
gcc/testsuite/gcc.dg/vect/pr23816-2.c [new file with mode: 0644]

index dc690dd..39345c8 100644 (file)
@@ -1,3 +1,9 @@
+2005-09-13  Uros Bizjak  <uros@kss-loka.si>
+
+       PR target/23816
+       * config/i386/sse.md (*ieee_sminv4sf3, *ieee_smaxv4sf3)
+       (*ieee_sminv2df3, *ieee_smaxv2df3): New insn patterns.
+
 2005-09-13  Ian Lance Taylor  <ian@airs.com>
 
        * loop-doloop.c (doloop_modify): Use GEN_INT to pass an rtx rather
index 95cb797..19f91ed 100644 (file)
   [(set_attr "type" "sse")
    (set_attr "mode" "SF")])
 
+;; These versions of the min/max patterns implement exactly the operations
+;;   min = (op1 < op2 ? op1 : op2)
+;;   max = (!(op1 < op2) ? op1 : op2)
+;; Their operands are not commutative, and thus they may be used in the
+;; presence of -0.0 and NaN.
+
+(define_insn "*ieee_sminv4sf3"
+  [(set (match_operand:V4SF 0 "register_operand" "=x")
+       (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
+                     (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
+                    UNSPEC_IEEE_MIN))]
+  "TARGET_SSE"
+  "minps\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseadd")
+   (set_attr "mode" "V4SF")])
+
+(define_insn "*ieee_smaxv4sf3"
+  [(set (match_operand:V4SF 0 "register_operand" "=x")
+       (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
+                     (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
+                    UNSPEC_IEEE_MAX))]
+  "TARGET_SSE"
+  "maxps\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseadd")
+   (set_attr "mode" "V4SF")])
+
+(define_insn "*ieee_sminv2df3"
+  [(set (match_operand:V2DF 0 "register_operand" "=x")
+       (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
+                     (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
+                    UNSPEC_IEEE_MIN))]
+  "TARGET_SSE2"
+  "minpd\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseadd")
+   (set_attr "mode" "V2DF")])
+
+(define_insn "*ieee_smaxv2df3"
+  [(set (match_operand:V2DF 0 "register_operand" "=x")
+       (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
+                     (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
+                    UNSPEC_IEEE_MAX))]
+  "TARGET_SSE2"
+  "maxpd\t{%2, %0|%0, %2}"
+  [(set_attr "type" "sseadd")
+   (set_attr "mode" "V2DF")])
+
 (define_insn "sse3_addsubv4sf3"
   [(set (match_operand:V4SF 0 "register_operand" "=x")
        (vec_merge:V4SF
diff --git a/gcc/testsuite/gcc.dg/vect/pr23816-1.c b/gcc/testsuite/gcc.dg/vect/pr23816-1.c
new file mode 100644 (file)
index 0000000..9ee9892
--- /dev/null
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+
+void
+foo (float a[32], float b[2][32])
+{
+  int i;
+  for (i = 0; i < 32; i++)
+    a[i] = (b[0][i] > b[1][i]) ? b[0][i] : b[1][i];
+}
diff --git a/gcc/testsuite/gcc.dg/vect/pr23816-2.c b/gcc/testsuite/gcc.dg/vect/pr23816-2.c
new file mode 100644 (file)
index 0000000..c3ef734
--- /dev/null
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+
+void
+foo (double a[32], double b[2][32])
+{
+  int i;
+  for (i = 0; i < 32; i++)
+    a[i] = (b[0][i] > b[1][i]) ? b[0][i] : b[1][i];
+}