gcc/

2011-10-14  David Alan Gilbert  <david.gilbert@linaro.org>

	* config/arm/arm.h (TARGET_HAVE_DMB_MCR): MCR Not available in Thumb1.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179979 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6dc80be..6a141e5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2011-10-14  David Alan Gilbert  <david.gilbert@linaro.org>
+
+       * config/arm/arm.h (TARGET_HAVE_DMB_MCR): MCR Not available in Thumb1.
+

 2011-10-14  Paolo Carlini  <paolo.carlini@oracle.com>
 
        * doc/invoke.texi ([Wformat-zero-length]): Tidy.
 2011-10-14  Paolo Carlini  <paolo.carlini@oracle.com>
 
        * doc/invoke.texi ([Wformat-zero-length]): Tidy.

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 8ce2b3e..19381fb 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -288,7 +288,8 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
 #define TARGET_HAVE_DMB                (arm_arch7)
 
 /* Nonzero if this chip implements a memory barrier via CP15.  */
 #define TARGET_HAVE_DMB                (arm_arch7)
 
 /* Nonzero if this chip implements a memory barrier via CP15.  */

-#define TARGET_HAVE_DMB_MCR    (arm_arch6k && ! TARGET_HAVE_DMB)
+#define TARGET_HAVE_DMB_MCR    (arm_arch6 && ! TARGET_HAVE_DMB \
+                                && ! TARGET_THUMB1)

 
 /* Nonzero if this chip implements a memory barrier instruction.  */
 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
 
 /* Nonzero if this chip implements a memory barrier instruction.  */
 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)