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PR target/33369
authoruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 10 Sep 2007 09:10:00 +0000 (09:10 +0000)
committeruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 10 Sep 2007 09:10:00 +0000 (09:10 +0000)
* gcc/config/i386/sse.md (ashr<mode>3): Change op2 mode to SImode.
Use 'N' operand constraint for op2.
(lshr<mode>3): Ditto.
(ashl<mode>3): Ditto.
(vec_shl_<mode>): Use const_0_to_255_mul_8_operand predicate for op2.
(vec_shr_<mode>): Use const_0_to_255_mul_8_operand predicate for op2.

* gcc/config/i386/i386.c (ix86_expand_builtin) [IX86_BUILTIN_PSLL?128,
IX86_BUILTIN_PSRA*?128, IX86_BUILTIN_PSRL?128]: Convert op1 to SImode.

testsuite/ChangeLog:

PR target/33369
* gcc.dg/vect/pr33369.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@128328 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/i386/i386.c
gcc/config/i386/i386.md
gcc/config/i386/sse.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.dg/vect/pr33369.c [new file with mode: 0644]

index dcf3a5c..e6868fe 100644 (file)
@@ -1,3 +1,16 @@
+2007-09-10  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/33369
+       * gcc/config/i386/sse.md (ashr<mode>3): Change op2 mode to SImode.
+       Use 'N' operand constraint for op2.
+       (lshr<mode>3): Ditto.
+       (ashl<mode>3): Ditto.
+       (vec_shl_<mode>): Use const_0_to_255_mul_8_operand predicate for op2.
+       (vec_shr_<mode>): Use const_0_to_255_mul_8_operand predicate for op2.
+
+       * gcc/config/i386/i386.c (ix86_expand_builtin) [IX86_BUILTIN_PSLL?128,
+       IX86_BUILTIN_PSRA*?128, IX86_BUILTIN_PSRL?128]: Convert op1 to SImode.
+
 2007-09-10  Andreas Krebbel  <krebbel1@de.ibm.com>
 
        * config/s390/s390.md ("fixuns_trunc<BFP:mode><GPR:mode>2"):
index 640e9c0..b1dda95 100644 (file)
@@ -19476,8 +19476,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
       if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
        op0 = copy_to_reg (op0);
 
-      op1 = simplify_gen_subreg (TImode, op1, GET_MODE (op1), 0);
-      if (! (*insn_data[icode].operand[2].predicate) (op1, TImode))
+      op1 = simplify_gen_subreg (SImode, op1, GET_MODE (op1), 0);
+      if (! (*insn_data[icode].operand[2].predicate) (op1, SImode))
        op1 = copy_to_reg (op1);
 
       target = gen_reg_rtx (tmode);
index 3ddf7dc..5b50274 100644 (file)
   "TARGET_SSE2 && TARGET_SSE_MATH
    && (!TARGET_USE_VECTOR_CONVERTS || optimize_size)"
   "@
-   cvtsi2sd\t{%1, %0|%0, %1} 
-   cvtsi2sd\t{%1, %0|%0, %1} 
+   cvtsi2sd\t{%1, %0|%0, %1}
+   cvtsi2sd\t{%1, %0|%0, %1}
    cvtdq2pd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "DF,DF,V2DF")
index 03b2577..65207a4 100644 (file)
   [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
        (ashiftrt:SSEMODE24
          (match_operand:SSEMODE24 1 "register_operand" "0")
-         (match_operand:TI 2 "nonmemory_operand" "xn")))]
+         (match_operand:SI 2 "nonmemory_operand" "xN")))]
   "TARGET_SSE2"
   "psra<ssevecsize>\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseishft")
   [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
        (lshiftrt:SSEMODE248
          (match_operand:SSEMODE248 1 "register_operand" "0")
-         (match_operand:TI 2 "nonmemory_operand" "xn")))]
+         (match_operand:SI 2 "nonmemory_operand" "xN")))]
   "TARGET_SSE2"
   "psrl<ssevecsize>\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseishft")
   [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
        (ashift:SSEMODE248
          (match_operand:SSEMODE248 1 "register_operand" "0")
-         (match_operand:TI 2 "nonmemory_operand" "xn")))]
+         (match_operand:SI 2 "nonmemory_operand" "xN")))]
   "TARGET_SSE2"
   "psll<ssevecsize>\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseishft")
 (define_expand "vec_shl_<mode>"
   [(set (match_operand:SSEMODEI 0 "register_operand" "")
         (ashift:TI (match_operand:SSEMODEI 1 "register_operand" "")
-                  (match_operand:SI 2 "general_operand" "")))]
+                  (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
   "TARGET_SSE2"
 {
-  if (!const_0_to_255_mul_8_operand (operands[2], SImode))
-    FAIL;
   operands[0] = gen_lowpart (TImode, operands[0]);
   operands[1] = gen_lowpart (TImode, operands[1]);
 })
 (define_expand "vec_shr_<mode>"
   [(set (match_operand:SSEMODEI 0 "register_operand" "")
         (lshiftrt:TI (match_operand:SSEMODEI 1 "register_operand" "")
-                    (match_operand:SI 2 "general_operand" "")))]
+                    (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
   "TARGET_SSE2"
 {
-  if (!const_0_to_255_mul_8_operand (operands[2], SImode))
-    FAIL;
   operands[0] = gen_lowpart (TImode, operands[0]);
   operands[1] = gen_lowpart (TImode, operands[1]);
 })
index bd7bde7..9528050 100644 (file)
@@ -1,3 +1,8 @@
+2007-09-10  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/33369
+       * gcc.dg/vect/pr33369.c: New test.
+
 2007-09-10  Paul Thomas  <pault@gcc.gnu.org>
 
        PR fortran/33370
diff --git a/gcc/testsuite/gcc.dg/vect/pr33369.c b/gcc/testsuite/gcc.dg/vect/pr33369.c
new file mode 100644 (file)
index 0000000..9979cbd
--- /dev/null
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target vect_shift } */
+
+typedef struct tagPOINT
+{
+  int x;
+  int y;
+} POINT;
+
+void
+f (POINT * ptBuf)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    {
+      ptBuf[i].x = ((ptBuf[i].x) << 4);
+      ptBuf[i].y = ((ptBuf[i].y) << 4);
+    }
+}
+
+/* { dg-final { cleanup-tree-dump "vect" } } */