2012-09-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
* config/i386/i386.md : Comments on fma4 instruction selection
reflect requirement on register pressure based cost model.
* config/i386/driver-i386.c (host_detect_local_cpu): fma4
flag is set-reset as informed by the cpuid flag.
* config/i386/i386.c (processor_alias_table): fma4
flag is enabled for bdver2.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@191227
138bc75d-0d04-0410-961f-
82ee72b054a4
+2012-09-12 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline
+ 2012-09-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ * config/i386/i386.md : Comments on fma4 instruction selection
+ reflect requirement on register pressure based cost model.
+
+ * config/i386/driver-i386.c (host_detect_local_cpu): fma4
+ flag is set-reset as informed by the cpuid flag.
+
+ * config/i386/i386.c (processor_alias_table): fma4
+ flag is enabled for bdver2.
+
2012-09-12 Christian Bruel <christian.bruel@st.com>
* config/sh/newlib.h (NO_IMPLICIT_EXTERN_C): Define.
Backport from mainline.
2012-08-29 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
- Richard Earnshaw <richard.earnshaw@arm.com>
+ Richard Earnshaw <richard.earnshaw@arm.com>
PR target/54252
* config/arm/arm.c (neon_dereference_pointer): Adjust nelems by
has_abm = ecx & bit_ABM;
has_lwp = ecx & bit_LWP;
has_fma4 = ecx & bit_FMA4;
- if (vendor == SIG_AMD && has_fma4 && has_fma)
- has_fma4 = 0;
has_xop = ecx & bit_XOP;
has_tbm = ecx & bit_TBM;
has_lzcnt = ecx & bit_LZCNT;
{"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
+ | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
| PTA_FMA},
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC64,
(eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
(eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
(eq_attr "isa" "fma") (symbol_ref "TARGET_FMA")
+ ;; Fma instruction selection has to be done based on
+ ;; register pressure. For generating fma4, a cost model
+ ;; based on register pressure is required. Till then,
+ ;; fma4 instruction is disabled for targets that implement
+ ;; both fma and fma4 instruction sets.
(eq_attr "isa" "fma4")
(symbol_ref "TARGET_FMA4 && !TARGET_FMA")
]