+2004-03-11 Kazu Hirata <kazu@cs.umass.edu>
+
+ * c-typeck.c, combine.c, cse.c, dominance.c, et-forest.h,
+ ggc-page.c, var-tracking.c, config/fp-bit.c, config/c4x/c4x.c,
+ config/cris/cris.c, config/i386/ppro.md, config/i860/i860.c,
+ config/i860/i860.h, config/m32r/m32r.h, config/m32r/xm-m32r.h,
+ config/m68hc11/m68hc11.h, config/m68hc11/m68hc11.md,
+ config/mips/mips.c, config/mmix/mmix.c, config/ns32k/ns32k.h,
+ config/pa/pa.c, config/pa/pa32-regs.h, config/pa/pa64-regs.h,
+ config/pdp11/pdp11.h, config/rs6000/rs6000.c,
+ config/stormy16/stormy16.c: Fix comment typos and formatting.
+
2004-03-11 Nathanael Nerode <neroden@gcc.gnu.org>
* configure: Regenerate, since I forgot to while committing Paolo's
case ENUMERAL_TYPE:
{
- /* Speed up the case where the type values are in the same order. */
+ /* Speed up the case where the type values are in the same order. */
tree tv1 = TYPE_VALUES (t1);
tree tv2 = TYPE_VALUES (t2);
int width = GET_MODE_BITSIZE (GET_MODE (x));
rtx y;
- /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
+ /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
number, sign extend it. */
if (width > 0 && width < HOST_BITS_PER_WIDE_INT
&& (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
to save/restore the registers we actually use.
For the global variable leaf_function to be set, we need
to define LEAF_REGISTERS and all that it entails.
- Let's check ourselves... */
+ Let's check ourselves.... */
if (lookup_attribute ("leaf_pretend",
TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
}
else
{
- /* If we use ar3, we need to push it. */
+ /* If we use ar3, we need to push it. */
dont_push_ar3 = 0;
if ((size != 0) || (current_function_args_size != 0))
{
return cris_general_operand_or_symbol (xmem, GET_MODE (op));
}
-/* The CONDITIONAL_REGISTER_USAGE worker. */
+/* The CONDITIONAL_REGISTER_USAGE worker. */
void
cris_conditional_register_usage (void)
{
/* We're a further than half way by a small amount corresponding
to the bits set in "low". Knowing that, we round here and
- not in pack_d, because there we don't have "low" avaliable
+ not in pack_d, because there we don't have "low" available
anymore. */
high += GARDROUND + 1;
/* We're a further than half way by the small amount
corresponding to the bits set in "numerator". Knowing
that, we round here and not in pack_d, because there we
- don't have "numerator" avaliable anymore. */
+ don't have "numerator" available anymore. */
quotient += GARDROUND + 1;
/* Avoid further rounding in pack_d. */
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA. */
-;; The P6 familiy includes the Pentium Pro, Pentium II, Pentium III, Celeron
+;; The P6 family includes the Pentium Pro, Pentium II, Pentium III, Celeron
;; and Xeon lines of CPUs. The DFA scheduler description in this file is
;; based on information that can be found in the following three documents:
;;
;; P3FPU
;;
;; (SAC=Store Address Calculation, SDA=Store Data Unit, P3FPU = SSE unit,
-;; JUE = Jump Execution Unit, AGU = Addres Generation Unit)
+;; JUE = Jump Execution Unit, AGU = Address Generation Unit)
;;
(define_cpu_unit "p0,p1" "ppro_core")
(define_cpu_unit "p2" "ppro_load")
;; doesn't make sense because we don't know how these instructions are
;; executed in the core. So we just model that they can only be decoded
;; on decoder 0, and say that it takes a little while before the result
-;; is availale.
+;; is available.
(define_insn_reservation "ppro_complex_insn" 6
(eq_attr "type" "other,multi,call,callv,str")
"decoder0")
(eq_attr "type" "cld"))
"decoder0,(p0+p1)*2")
-;; The P6 has a sophisticated branch prediction mechanism to miminize
+;; The P6 has a sophisticated branch prediction mechanism to minimize
;; latencies due to branching. In particular, it has a fast way to
;; execute branches that are taken multiple times (such as in loops).
;; Branches not taken suffer no penalty, and correctly predicted
;; branches cost only one fetch cycle. Mispredicted branches are very
;; costly: typically 15 cycles and possibly as many as 26 cycles.
;;
-;; Unfortunatetely all this makes it quite difficult to properly model
+;; Unfortunately all this makes it quite difficult to properly model
;; the latencies for the compiler. Here I've made the choice to be
;; optimistic and assume branches are often predicted correctly, so
;; they have latency 1, and the decoders are not blocked.
/* Anything that sets just part of the register
is considered using as well as setting it.
But note that a straight SUBREG of a single-word value
- clobbers the entire value. */
+ clobbers the entire value. */
if (dest != SET_DEST (in)
&& ! (GET_CODE (SET_DEST (in)) == SUBREG
|| UNITS_PER_WORD >= GET_MODE_SIZE (GET_MODE (dest))))
/* Return a template for a store instruction with mode MODE and
arguments from the string ARGS.
- This string is in static storage. */
+ This string is in static storage. */
static const char *
store_opcode (enum machine_mode mode, const char *args, rtx reg)
#define N_REG_CLASSES (int) LIM_REG_CLASSES
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{ "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
extern struct rtx_def * m32r_compare_op0;
extern struct rtx_def * m32r_compare_op1;
-/* M32R function types. */
+/* M32R function types. */
enum m32r_function_type
{
M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
#define HOST_WORDS_BIG_ENDIAN 1
/* target machine dependencies.
- tm.h is a symbolic link to the actual target specific file. */
+ tm.h is a symbolic link to the actual target specific file. */
#include "tm.h"
/* Arguments to use with `exit'. */
sections when it shrinks the code. This results in invalid addresses
when debugging. This does not bless too much the HC11/HC12 as most
applications are embedded and small, hence a reasonable debug info.
- This problem is known for binutils 2.13, 2.14 and mainline. */
+ This problem is known for binutils 2.13, 2.14 and mainline. */
#undef HAVE_AS_DWARF2_DEBUG_LINE
/* The prefix for local labels. You should be able to define this as
;;
;; Remove one load when copying a value to/from memory and also
-;; to a register. Take care not cloberring a possible register used
+;; to a register. Take care not clobbering a possible register used
;; by operand 2.
;; Replace: "ldd 0,y; std 2,y; ldx 0,y" into "ldx 0,y; stx 2,y"
;;
int off, i;
/* Set OFF to the offset from virtual_incoming_args_rtx of
- the first float register. The FP save area lies below
+ the first float register. The FP save area lies below
the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
off = -gp_saved * UNITS_PER_WORD;
off &= ~(UNITS_PER_FPVALUE - 1);
unsigned int align)
{
/* If the target wants uninitialized const declarations in
- .rdata then don't put them in .comm. */
+ .rdata then don't put them in .comm. */
if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
&& TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
&& (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
stack_pointer_rtx,
GEN_INT (step2)));
- /* Add in the __builtin_eh_return stack adjustment. We need to
+ /* Add in the __builtin_eh_return stack adjustment. We need to
use a temporary in mips16 code. */
if (current_function_calls_eh_return)
{
the division is not immediately followed by a shift[1][2]. We also
need to stop the division from being put into a branch delay slot[3].
The easiest way to avoid both problems is to add a nop after the
- division. When a divide-by-zero check is neeeded, this nop can be
+ division. When a divide-by-zero check is needed, this nop can be
used to fill the branch delay slot.
[1] If a double-word or a variable shift executes immediately
*pretend_sizep = (MMIX_MAX_ARGS_IN_REGS - (args_so_farp->regs + 1)) * 8;
/* We assume that one argument takes up one register here. That should
- be true until we start messing with multi-reg parameters. */
+ be true until we start messing with multi-reg parameters. */
if ((7 + (MMIX_FUNCTION_ARG_SIZE (mode, vartype))) / 8 != 1)
internal_error ("MMIX Internal: Last named vararg would not fit in a register");
}
#define N_REG_CLASSES (int) LIM_REG_CLASSES
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{"NO_REGS", "GENERAL_REGS", "FLOAT_REG0", "LONG_FLOAT_REG0", "FLOAT_REGS", \
We have to do this because the REG_POINTER flag is not correctly
carried through various optimization passes and CSE may substitute
a pseudo without the pointer set for one with the pointer set. As
- a result, we loose various opportunites to create insns with
+ a result, we loose various opportunities to create insns with
unscaled indexed addresses. */
if (!TARGET_NO_SPACE_REGS
&& !cse_not_expected
\f
/* Return the best assembler insn template
- for moving operands[1] into operands[0] as a fullword. */
+ for moving operands[1] into operands[0] as a fullword. */
const char *
singlemove_string (rtx *operands)
{
OPERANDS[3] is a register for temporary storage.
OPERANDS[4] is the size as a CONST_INT
OPERANDS[5] is the alignment safe to use, as a CONST_INT.
- OPERANDS[6] is another temporary register. */
+ OPERANDS[6] is another temporary register. */
const char *
output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
{
int i;
int chars_output;
- unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
+ unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
/* The HP assembler can only take strings of 256 characters at one
time. This is a limitation on input line length, *not* the
else
{
/* Reload loop counter from memory, the store back to memory
- happens in the branch's delay slot. */
+ happens in the branch's delay slot. */
output_asm_insn ("ldw %0,%4", operands);
if (get_attr_length (insn) == 12)
return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
else if (which_alternative == 2)
{
/* Reload loop counter from memory, the store back to memory
- happens in the branch's delay slot. */
+ happens in the branch's delay slot. */
if (get_attr_length (insn) == 8)
return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
else
#define N_REG_CLASSES (int) LIM_REG_CLASSES
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
: SHIFT_REGS)
/* Get reg_class from a letter such as appears in the machine description. */
-/* Keep 'x' for backward compatibility with user asm. */
+/* Keep 'x' for backward compatibility with user asm. */
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'f' ? FP_REGS : \
(C) == 'y' ? FPUPPER_REGS : \
#define N_REG_CLASSES (int) LIM_REG_CLASSES
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
/* Get reg_class from a letter such as appears in the machine description. */
-/* Keep 'x' for backward compatibility with user asm. */
+/* Keep 'x' for backward compatibility with user asm. */
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'f' ? FP_REGS : \
(C) == 'y' ? FP_REGS : \
/* #define GENERAL_REGS ALL_REGS */
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" }
tree field = TYPE_FIELDS (type);
/* Skip all the static variables only if ABI is greater than
- 1 or equal to 0. */
+ 1 or equal to 0. */
while (field != NULL && TREE_CODE (field) == VAR_DECL)
field = TREE_CHAIN (field);
const char *section = ".dtors";
char buf[16];
- /* ??? This only works reliably with the GNU linker. */
+ /* ??? This only works reliably with the GNU linker. */
if (priority != DEFAULT_INIT_PRIORITY)
{
sprintf (buf, ".dtors.%.5u",
const char *section = ".ctors";
char buf[16];
- /* ??? This only works reliably with the GNU linker. */
+ /* ??? This only works reliably with the GNU linker. */
if (priority != DEFAULT_INIT_PRIORITY)
{
sprintf (buf, ".ctors.%.5u",
/* See if a MEM has already been loaded with a widening operation;
if it has, we can use a subreg of that. Many CISC machines
also have such operations, but this is only likely to be
- beneficial these machines. */
+ beneficial on these machines. */
if (flag_expensive_optimizations && src_related == 0
&& (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
/* Determine immediate dominator (or postdominator, according to DIR) of BB,
assuming that dominators of other blocks are correct. We also use it to
recompute the dominators in a restricted area, by iterating it until it
- reaches a fixpoint. */
+ reaches a fixed point. */
basic_block
recount_dominator (enum cdi_direction dir, basic_block bb)
struct et_node *left;
struct et_node *right; /* The brothers of the node. */
- struct et_occ *rightmost_occ; /* The rightmost occurence. */
- struct et_occ *parent_occ; /* The occurence of the parent node. */
+ struct et_occ *rightmost_occ; /* The rightmost occurrence. */
+ struct et_occ *parent_occ; /* The occurrence of the parent node. */
};
struct et_node *et_new_tree (void *data);
/* The previous page-entry with objects of the same size, or NULL if
this is the first page-entry. The PREV pointer exists solely to
- keep the cost of ggc_free managable. */
+ keep the cost of ggc_free manageable. */
struct page_entry *prev;
/* The number of bytes allocated. (This will always be a multiple
{
dataflow_set_different_value = true;
- /* Stop traversing the hash table. */
+ /* Stop traversing the hash table. */
return 0;
}
{
dataflow_set_different_value = true;
- /* Stop traversing the hash table. */
+ /* Stop traversing the hash table. */
return 0;
}
{
dataflow_set_different_value = true;
- /* Stop traversing the hash table. */
+ /* Stop traversing the hash table. */
return 0;
}
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