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PR target/34682
authoruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 7 Jan 2008 20:06:34 +0000 (20:06 +0000)
committeruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 7 Jan 2008 20:06:34 +0000 (20:06 +0000)
        * config/i386/i386.md (neg<mode>2): Rename from negsf2, negdf2 and
        negxf2.  Macroize expander using X87MODEF mode iterator.  Change
        predicates of op0 and op1 to register_operand.
        (abs<mode>2): Rename from abssf2, absdf2 and negxf2.  Macroize expander
        using X87MODEF mode iterator.  Change predicates of op0 and op1 to
        register_operand.
        ("*absneg<mode>2_mixed", "*absneg<mode>2_sse"): Rename from
        corresponding patterns and macroize using MODEF macro.  Change
        predicates of op0 and op1 to register_operand and remove
        "m" constraint. Disparage "r" alternative with "!".
        ("*absneg<mode>2_i387"): Rename from corresponding patterns and
        macroize using X87MODEF macro.  Change predicates of op0 and op1
        to register_operand and remove "m" constraint.  Disparage "r"
        alternative with "!".
        (absneg splitter with memory operands): Remove.
        ("*neg<mode>2_1", "*abs<mode>2_1"): Rename from corresponding
        patterns and macroize using X87MODEF mode iterator.
        * config/i386/sse.md (negv4sf2, absv4sf2, neg2vdf2, absv2df2):
        Change predicate of op1 to register_operand.
        * config/i386/i386.c (ix86_expand_fp_absneg_operator): Remove support
        for memory operands.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@131381 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog patch | blob | history
gcc/config/i386/i386.c patch | blob | history
gcc/config/i386/i386.md patch | blob | history
gcc/config/i386/sse.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7d7ffce..e8732d7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,28 @@
+2008-01-07  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/34682
+       * config/i386/i386.md (neg<mode>2): Rename from negsf2, negdf2 and
+       negxf2.  Macroize expander using X87MODEF mode iterator.  Change
+       predicates of op0 and op1 to register_operand.
+       (abs<mode>2): Rename from abssf2, absdf2 and negxf2.  Macroize expander
+       using X87MODEF mode iterator.  Change predicates of op0 and op1 to
+       register_operand.
+       ("*absneg<mode>2_mixed", "*absneg<mode>2_sse"): Rename from
+       corresponding patterns and macroize using MODEF macro.  Change
+       predicates of op0 and op1 to register_operand and remove
+       "m" constraint. Disparage "r" alternative with "!".
+       ("*absneg<mode>2_i387"): Rename from corresponding patterns and
+       macroize using X87MODEF macro.  Change predicates of op0 and op1
+       to register_operand and remove "m" constraint.  Disparage "r"
+       alternative with "!".
+       (absneg splitter with memory operands): Remove.
+       ("*neg<mode>2_1", "*abs<mode>2_1"): Rename from corresponding
+       patterns and macroize using X87MODEF mode iterator.
+       * config/i386/sse.md (negv4sf2, absv4sf2, neg2vdf2, absv2df2):
+       Change predicate of op1 to register_operand.
+       * config/i386/i386.c (ix86_expand_fp_absneg_operator): Remove support
+       for memory operands.2008-01-07  Richard Guenther  <rguenther@suse.de>
+
 2008-01-07  Nathan Froyd  <froydnj@codesourcery.com>
 
        * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add clause for mcpu=8548.
@@ -17,9 +42,9 @@
 
 2008-01-07  Sa Liu  <saliu@de.ibm.com>
 
-       * config/spu/spu.md (divdf3): Genetate inline code for double division. 
-       The implementation doesn't handle INF or NAN, therefore it only applies 
-       when -ffinite-math-only is given.
+       * config/spu/spu.md (divdf3): Genetate inline code for double
+       division.  The implementation doesn't handle INF or NAN, therefore it
+       only applies when -ffinite-math-only is given.
 
 2008-01-06  Paolo Carlini  <pcarlini@suse.de>
 
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 26acbc9..0f827a6 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -11020,7 +11020,6 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
                                rtx operands[])
 {
   rtx mask, set, use, clob, dst, src;
-  bool matching_memory;
   bool use_sse = false;
   bool vector_mode = VECTOR_MODE_P (mode);
   enum machine_mode elt_mode = mode;
@@ -11045,19 +11044,6 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
   dst = operands[0];
   src = operands[1];
 
-  /* If the destination is memory, and we don't have matching source
-     operands or we're using the x87, do things in registers.  */
-  matching_memory = false;
-  if (MEM_P (dst))
-    {
-      if (use_sse && rtx_equal_p (dst, src))
-       matching_memory = true;
-      else
-       dst = gen_reg_rtx (mode);
-    }
-  if (MEM_P (src) && !matching_memory)
-    src = force_reg (mode, src);
-
   if (vector_mode)
     {
       set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
@@ -11078,9 +11064,6 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
       else
        emit_insn (set);
     }
-
-  if (dst != operands[0])
-    emit_move_insn (operands[0], dst);
 }
 
 /* Expand a copysign operation.  Special case operand 0 being a constant.  */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index cff39d8..04d38f6 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10238,132 +10238,64 @@
 
 ;; Changing of sign for FP values is doable using integer unit too.
 
-(define_expand "negsf2"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "")
-       (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 || TARGET_SSE_MATH"
-  "ix86_expand_fp_absneg_operator (NEG, SFmode, operands); DONE;")
-
-(define_expand "abssf2"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "")
-       (abs:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 || TARGET_SSE_MATH"
-  "ix86_expand_fp_absneg_operator (ABS, SFmode, operands); DONE;")
-
-(define_insn "*absnegsf2_mixed"
-  [(set (match_operand:SF 0 "nonimmediate_operand"    "=x  ,x,f,rm")
-       (match_operator:SF 3 "absneg_operator"
-         [(match_operand:SF 1 "nonimmediate_operand" "0   ,x,0,0 ")]))
-   (use (match_operand:V4SF 2 "nonimmediate_operand"  "xm  ,0,X,X "))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_SSE_MATH && TARGET_MIX_SSE_I387
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
-  "#")
-
-(define_insn "*absnegsf2_sse"
-  [(set (match_operand:SF 0 "nonimmediate_operand"    "=x,x,rm")
-       (match_operator:SF 3 "absneg_operator"
-         [(match_operand:SF 1 "nonimmediate_operand" "0 ,x,0")]))
-   (use (match_operand:V4SF 2 "nonimmediate_operand"  "xm,0,X"))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_SSE_MATH
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
-  "#")
-
-(define_insn "*absnegsf2_i387"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,rm")
-       (match_operator:SF 3 "absneg_operator"
-         [(match_operand:SF 1 "nonimmediate_operand" "0,0")]))
-   (use (match_operand 2 "" ""))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_80387 && !TARGET_SSE_MATH
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
-  "#")
-
-(define_expand "negdf2"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "")
-       (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
-  "ix86_expand_fp_absneg_operator (NEG, DFmode, operands); DONE;")
-
-(define_expand "absdf2"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "")
-       (abs:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
-  "ix86_expand_fp_absneg_operator (ABS, DFmode, operands); DONE;")
+(define_expand "neg<mode>2"
+  [(set (match_operand:X87MODEF 0 "register_operand" "")
+       (neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
+  "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+  "ix86_expand_fp_absneg_operator (NEG, <MODE>mode, operands); DONE;")
 
-(define_insn "*absnegdf2_mixed"
-  [(set (match_operand:DF 0 "nonimmediate_operand"    "=x,x,f,rm")
-       (match_operator:DF 3 "absneg_operator"
-         [(match_operand:DF 1 "nonimmediate_operand" "0 ,x,0,0")]))
-   (use (match_operand:V2DF 2 "nonimmediate_operand"  "xm,0,X,X"))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
-  "#")
+(define_expand "abs<mode>2"
+  [(set (match_operand:X87MODEF 0 "register_operand" "")
+       (abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
+  "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+  "ix86_expand_fp_absneg_operator (ABS, <MODE>mode, operands); DONE;")
 
-(define_insn "*absnegdf2_sse"
-  [(set (match_operand:DF 0 "nonimmediate_operand"    "=x,x,rm")
-       (match_operator:DF 3 "absneg_operator"
-         [(match_operand:DF 1 "nonimmediate_operand" "0 ,x,0 ")]))
-   (use (match_operand:V2DF 2 "nonimmediate_operand"  "xm,0,X "))
+(define_insn "*absneg<mode>2_mixed"
+  [(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r")
+       (match_operator:MODEF 3 "absneg_operator"
+         [(match_operand:MODEF 1 "register_operand" "0,x,0,0")]))
+   (use (match_operand:<ssevecmode> 2 "nonimmediate_operand" "xm,0,X,X"))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_SSE2 && TARGET_SSE_MATH
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
+  "TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (<MODE>mode)"
   "#")
 
-(define_insn "*absnegdf2_i387"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,rm")
-       (match_operator:DF 3 "absneg_operator"
-         [(match_operand:DF 1 "nonimmediate_operand" "0,0")]))
-   (use (match_operand 2 "" ""))
+(define_insn "*absneg<mode>2_sse"
+  [(set (match_operand:MODEF 0 "register_operand" "=x,x,!r")
+       (match_operator:MODEF 3 "absneg_operator"
+         [(match_operand:MODEF 1 "register_operand" "0 ,x,0")]))
+   (use (match_operand:<ssevecmode> 2 "register_operand" "xm,0,X"))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
+  "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
   "#")
 
-(define_expand "negxf2"
-  [(set (match_operand:XF 0 "nonimmediate_operand" "")
-       (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "ix86_expand_fp_absneg_operator (NEG, XFmode, operands); DONE;")
-
-(define_expand "absxf2"
-  [(set (match_operand:XF 0 "nonimmediate_operand" "")
-       (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "ix86_expand_fp_absneg_operator (ABS, XFmode, operands); DONE;")
-
-(define_insn "*absnegxf2_i387"
-  [(set (match_operand:XF 0 "nonimmediate_operand" "=f,?rm")
-       (match_operator:XF 3 "absneg_operator"
-         [(match_operand:XF 1 "nonimmediate_operand" "0,0")]))
+(define_insn "*absneg<mode>2_i387"
+  [(set (match_operand:X87MODEF 0 "register_operand" "=f,!r")
+       (match_operator:X87MODEF 3 "absneg_operator"
+         [(match_operand:X87MODEF 1 "register_operand" "0,0")]))
    (use (match_operand 2 "" ""))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_80387
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), XFmode, operands)"
+  "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
   "#")
 
 (define_expand "negtf2"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "")
-       (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))]
+  [(set (match_operand:TF 0 "register_operand" "")
+       (neg:TF (match_operand:TF 1 "register_operand" "")))]
   "TARGET_64BIT"
   "ix86_expand_fp_absneg_operator (NEG, TFmode, operands); DONE;")
 
 (define_expand "abstf2"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "")
-       (abs:TF (match_operand:TF 1 "nonimmediate_operand" "")))]
+  [(set (match_operand:TF 0 "register_operand" "")
+       (abs:TF (match_operand:TF 1 "register_operand" "")))]
   "TARGET_64BIT"
   "ix86_expand_fp_absneg_operator (ABS, TFmode, operands); DONE;")
 
 (define_insn "*absnegtf2_sse"
-  [(set (match_operand:TF 0 "nonimmediate_operand"    "=x,x,m")
+  [(set (match_operand:TF 0 "register_operand" "=x,x")
        (match_operator:TF 3 "absneg_operator"
-         [(match_operand:TF 1 "nonimmediate_operand" "0, x,0")]))
-   (use (match_operand:TF 2 "nonimmediate_operand"    "xm,0,X"))
+         [(match_operand:TF 1 "register_operand" "0,x")]))
+   (use (match_operand:TF 2 "nonimmediate_operand" "xm,0"))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT
-   && ix86_unary_operator_ok (GET_CODE (operands[3]), TFmode, operands)"
+  "TARGET_64BIT"
   "#")
 
 ;; Splitters for fp abs and neg.
@@ -10492,83 +10424,26 @@
   operands[1] = tmp;
 })
 
-(define_split
-  [(set (match_operand 0 "memory_operand" "")
-       (match_operator 1 "absneg_operator" [(match_dup 0)]))
-   (use (match_operand 2 "" ""))
-   (clobber (reg:CC FLAGS_REG))]
-  "reload_completed"
-  [(parallel [(set (match_dup 0) (match_dup 1))
-             (clobber (reg:CC FLAGS_REG))])]
-{
-  enum machine_mode mode = GET_MODE (operands[0]);
-  int size = mode == XFmode ? 10 : GET_MODE_SIZE (mode);
-  rtx tmp;
-
-  operands[0] = adjust_address (operands[0], QImode, size - 1);
-  if (GET_CODE (operands[1]) == ABS)
-    {
-      tmp = gen_int_mode (0x7f, QImode);
-      tmp = gen_rtx_AND (QImode, operands[0], tmp);
-    }
-  else
-    {
-      tmp = gen_int_mode (0x80, QImode);
-      tmp = gen_rtx_XOR (QImode, operands[0], tmp);
-    }
-  operands[1] = tmp;
-})
-
 ;; Conditionalize these after reload. If they match before reload, we
 ;; lose the clobber and ability to use integer instructions.
 
-(define_insn "*negsf2_1"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-       (neg:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_80387 && (reload_completed || !TARGET_SSE_MATH)"
-  "fchs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "SF")])
-
-(define_insn "*negdf2_1"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-       (neg:DF (match_operand:DF 1 "register_operand" "0")))]
-  "TARGET_80387 && (reload_completed || !(TARGET_SSE2 && TARGET_SSE_MATH))"
-  "fchs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "DF")])
-
-(define_insn "*negxf2_1"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-       (neg:XF (match_operand:XF 1 "register_operand" "0")))]
-  "TARGET_80387"
+(define_insn "*neg<mode>2_1"
+  [(set (match_operand:X87MODEF 0 "register_operand" "=f")
+       (neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
+  "TARGET_80387
+   && (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
   "fchs"
   [(set_attr "type" "fsgn")
-   (set_attr "mode" "XF")])
-
-(define_insn "*abssf2_1"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-       (abs:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_80387 && (reload_completed || !TARGET_SSE_MATH)"
-  "fabs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "SF")])
-
-(define_insn "*absdf2_1"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-       (abs:DF (match_operand:DF 1 "register_operand" "0")))]
-  "TARGET_80387 && (reload_completed || !(TARGET_SSE2 && TARGET_SSE_MATH))"
-  "fabs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "DF")])
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "*absxf2_1"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-       (abs:XF (match_operand:XF 1 "register_operand" "0")))]
-  "TARGET_80387"
+(define_insn "*abs<mode>2_1"
+  [(set (match_operand:X87MODEF 0 "register_operand" "=f")
+       (abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
+  "TARGET_80387
+   && (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
   "fabs"
   [(set_attr "type" "fsgn")
-   (set_attr "mode" "DF")])
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "*negextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 16c85a0..43f7ced 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -378,13 +378,13 @@
 
 (define_expand "negv4sf2"
   [(set (match_operand:V4SF 0 "register_operand" "")
-       (neg:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
+       (neg:V4SF (match_operand:V4SF 1 "register_operand" "")))]
   "TARGET_SSE"
   "ix86_expand_fp_absneg_operator (NEG, V4SFmode, operands); DONE;")
 
 (define_expand "absv4sf2"
   [(set (match_operand:V4SF 0 "register_operand" "")
-       (abs:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
+       (abs:V4SF (match_operand:V4SF 1 "register_operand" "")))]
   "TARGET_SSE"
   "ix86_expand_fp_absneg_operator (ABS, V4SFmode, operands); DONE;")
 
@@ -2143,13 +2143,13 @@
 
 (define_expand "negv2df2"
   [(set (match_operand:V2DF 0 "register_operand" "")
-       (neg:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")))]
+       (neg:V2DF (match_operand:V2DF 1 "register_operand" "")))]
   "TARGET_SSE2"
   "ix86_expand_fp_absneg_operator (NEG, V2DFmode, operands); DONE;")
 
 (define_expand "absv2df2"
   [(set (match_operand:V2DF 0 "register_operand" "")
-       (abs:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")))]
+       (abs:V2DF (match_operand:V2DF 1 "register_operand" "")))]
   "TARGET_SSE2"
   "ix86_expand_fp_absneg_operator (ABS, V2DFmode, operands); DONE;")
 
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