* config/arm/arm.c, config/arm/arm.h, config/arm/arm.md,

	config/arm/thumb2.md: Fix comment typos.
	* doc/extend.texi: Fix a typo.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@120566 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b297e64..cc59fa0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
+
+       * config/arm/arm.c, config/arm/arm.h, config/arm/arm.md,
+       config/arm/thumb2.md: Fix comment typos.
+       * doc/extend.texi: Fix a typo.
+
 2007-01-07  Eric Christopher  <echristo@apple.com>
 
        * configure.ac: Check for __stack_chk_fail for darwin.

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index d7fa19c..731dbe2 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -449,7 +449,7 @@ static int thumb_call_reg_needed;
 #define FL_THUMB2     (1 << 16)              /* Thumb-2.  */
 #define FL_NOTM              (1 << 17)       /* Instructions not present in the 'M'
                                         profile.  */
-#define FL_DIV       (1 << 18)       /* Hardware divde.  */
+#define FL_DIV       (1 << 18)       /* Hardware divide.  */
 
 #define FL_IWMMXT     (1 << 29)              /* XScale v2 or "Intel Wireless MMX technology".  */
 
@@ -2501,7 +2501,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
            else
              i -= 7;
          }
-       /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitary
+       /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
           shifts.  */
        if (TARGET_ARM)
          i -= 2;
@@ -7702,11 +7702,11 @@ get_jump_table_size (rtx insn)
       switch (modesize)
        {
        case 1:
-         /* Round up size  of TBB table to a hafword boundary.  */
+         /* Round up size of TBB table to a haflword boundary.  */
          size = (size + 1) & ~(HOST_WIDE_INT)1;
          break;
        case 2:
-         /* No padding neccessary for TBH.  */
+         /* No padding necessary for TBH.  */
          break;
        case 4:
          /* Add two bytes for alignment on Thumb.  */
@@ -10448,7 +10448,7 @@ arm_output_epilogue (rtx sibling)
       if (frame_pointer_needed)
        {
          /* For Thumb-2 restore sp from the frame pointer.
-            Operand restrictions mean we have to incrememnt FP, then copy
+            Operand restrictions mean we have to increment FP, then copy
             to SP.  */
          amount = offsets->locals_base - offsets->saved_regs;
          operands[0] = hard_frame_pointer_rtx;
@@ -11116,7 +11116,7 @@ arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
 }
 
 
-/* Emit RTL to save coprocessor registers on funciton entry.  Returns the
+/* Emit RTL to save coprocessor registers on function entry.  Returns the
    number of bytes pushed.  */
 
 static int
@@ -11592,7 +11592,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
   
     case '.':
       /* The current condition code for a condition code setting instruction.
-        Preceeded by 's' in unified syntax, otherwise followed by 's'.  */
+        Preceded by 's' in unified syntax, otherwise followed by 's'.  */
       if (TARGET_UNIFIED_ASM)
        {
          fputc('s', stream);
@@ -12240,7 +12240,7 @@ thumb2_final_prescan_insn (rtx insn)
          continue;
        }
 
-      /* ??? Recognise conditional jumps, and combine them with IT blocks.  */
+      /* ??? Recognize conditional jumps, and combine them with IT blocks.  */
       if (GET_CODE (body) != COND_EXEC)
        break;
       /* Allow up to 4 conditionally executed instructions in a block.  */
@@ -16473,7 +16473,7 @@ arm_output_addr_const_extra (FILE *fp, rtx x)
 
 /* Output assembly for a shift instruction.
    SET_FLAGS determines how the instruction modifies the condition codes.
-   0 - Do not set conditiona codes.
+   0 - Do not set condition codes.
    1 - Set condition codes.
    2 - Use smallest instruction.  */
 const char *

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index d2f493b..318d4f4 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1881,7 +1881,7 @@ typedef struct
 #define ASM_OUTPUT_LABELREF(FILE, NAME)                \
    arm_asm_output_labelref (FILE, NAME)
 
-/* Output IT instructions for conditonally executed Thumb-2 instructions.  */
+/* Output IT instructions for conditionally executed Thumb-2 instructions.  */
 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
   if (TARGET_THUMB2)                   \
     thumb2_asm_output_opcode (STREAM);
@@ -1962,7 +1962,7 @@ typedef struct
    The usual definition accepts all pseudo regs; the other rejects
    them unless they have been allocated suitable hard regs.
    The symbol REG_OK_STRICT causes the latter definition to be used.
-   Thumb-2 has the same restictions as arm.  */
+   Thumb-2 has the same restrictions as arm.  */
 #ifndef REG_OK_STRICT
 
 #define ARM_REG_OK_FOR_BASE_P(X)               \

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 14a9862..564c755 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -10518,8 +10518,8 @@
      
     /* For the StrongARM at least it is faster to
        use STR to store only a single register.
-       In Thumb mode always use push, and the assmebler will pick
-       something approporiate.  */
+       In Thumb mode always use push, and the assembler will pick
+       something appropriate.  */
     if (num_saves == 1 && TARGET_ARM)
       output_asm_insn (\"str\\t%1, [%m0, #-4]!\", operands);
     else

diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 7406b74..a8fbcbc 100644 (file)
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -277,7 +277,7 @@
 )
 
 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
-;; of the messyness assocuated with the ARM patterns.
+;; of the messyness associated with the ARM patterns.
 (define_insn "*thumb2_movhi_insn"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")    
        (match_operand:HI 1 "general_operand"      "rI,n,r,m"))]
@@ -858,7 +858,7 @@
   "TARGET_THUMB2"
   "*
     /* ??? Output both instructions unconditionally, otherwise the conditional
-       executon insn counter gets confused.
+       execution insn counter gets confused.
     if (REGNO (operands[1])
         != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) */
       output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
@@ -890,7 +890,7 @@
   "TARGET_THUMB2"
   "*
     /* ??? Output both instructions unconditionally, otherwise the conditional
-       executon insn counter gets confused.
+       execution insn counter gets confused.
     if (REGNO (operands[1])
         != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) */
       output_asm_insn (\"mov%?\\t%Q0, %1\", operands);

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 3d05ad4..0eec8d2 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -1965,7 +1965,7 @@ void f () __attribute__ ((interrupt ("IRQ")));
 
 Permissible values for this parameter are: IRQ, FIQ, SWI, ABORT and UNDEF@.
 
-On ARMv7-M the interrupt type is ignored, and the attibute means the function
+On ARMv7-M the interrupt type is ignored, and the attribute means the function
 may be called with a word aligned stack pointer.
 
 @item interrupt_handler