* g++.dg/vect/vect.exp: Enable tests to run on spu.

        * gcc.dg/vect/vect.exp: Enable tests to run on spu.
        * gcc.dg/vect/no-section-anchors-vect-69.c: Reduce array size.
        * gcc.dg/vect/vect-70.c: Reduce array size.
        * gcc.dg/vect/fast-math-vect-reduc-7.c: Xfail for
        vect_no_compaer_double targets.
        * lib/target-supports.exp: Add spu to vect_no_align, no_vect_int_max,
        vect_float, vect_double, and vect_int.

	* config/spu/spu.md (smaxv4sf3, sminv4sf3): New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@119469 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d4f6b6b..cd810ff 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2006-12-03  Dorit Nuzman  <dorit@il.ibm.com>
+
+       * config/spu/spu.md (smaxv4sf3, sminv4sf3): New.
+
 2006-12-03  Uros Bizjak  <ubizjak@gmail.com>
 
        PR target/30041

diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index 417081b..5ad43ac 100644 (file)
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -3300,3 +3300,31 @@ selb\t%0,%4,%0,%3"
 ;;
 (include "spu-builtins.md")
 
+  
+(define_expand "smaxv4sf3"
+  [(set (match_operand:V4SF 0 "register_operand" "=r")
+        (smax:V4SF (match_operand:V4SF 1 "register_operand" "r")
+                 (match_operand:V4SF 2 "register_operand" "r")))]
+  ""
+  "
+{
+  rtx mask = gen_reg_rtx (V4SImode);
+
+  emit_insn (gen_cgt_v4sf (mask, operands[1], operands[2]));
+  emit_insn (gen_selb (operands[0], operands[2], operands[1], mask));
+  DONE;
+}") 
+
+(define_expand "sminv4sf3"
+  [(set (match_operand:V4SF 0 "register_operand" "=r")
+        (smax:V4SF (match_operand:V4SF 1 "register_operand" "r")
+                 (match_operand:V4SF 2 "register_operand" "r")))]
+  ""
+  "
+{
+  rtx mask = gen_reg_rtx (V4SImode);
+
+  emit_insn (gen_cgt_v4sf (mask, operands[1], operands[2]));
+  emit_insn (gen_selb (operands[0], operands[1], operands[2], mask));
+  DONE;
+}") 

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5adbc19..be7429e 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2006-12-03  Dorit Nuzman  <dorit@il.ibm.com>
+
+       * g++.dg/vect/vect.exp: Enable tests to run on spu.
+       * gcc.dg/vect/vect.exp: Enable tests to run on spu.
+       * gcc.dg/vect/no-section-anchors-vect-69.c: Reduce array size.
+       * gcc.dg/vect/vect-70.c: Reduce array size.
+       * gcc.dg/vect/fast-math-vect-reduc-7.c: Xfail for 
+       vect_no_compaer_double targets.
+       * lib/target-supports.exp: Add spu to vect_no_align, no_vect_int_max,
+       vect_float, vect_double, and vect_int.
+
 2006-12-03  Dorit Nuzman <dorit@il.ibm.com>
 
        * gcc.dg/vect/pr16105.c: Remove xfail on vect_no_align targets. Add

diff --git a/gcc/testsuite/g++.dg/vect/vect.exp b/gcc/testsuite/g++.dg/vect/vect.exp
index ce51c8a..6e8afa7 100644 (file)
--- a/gcc/testsuite/g++.dg/vect/vect.exp
+++ b/gcc/testsuite/g++.dg/vect/vect.exp
@@ -58,6 +58,8 @@ if [istarget "powerpc*-*-*"] {
         }
         set dg-do-what-default compile
     }
+} elseif { [istarget  "spu-*-*"] } {
+   set dg-do-what-default run
 } elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
     lappend DEFAULT_VECTCFLAGS "-msse2"
     set dg-do-what-default run

diff --git a/gcc/testsuite/gcc.dg/vect/fast-math-vect-reduc-7.c b/gcc/testsuite/gcc.dg/vect/fast-math-vect-reduc-7.c
index b25e114..c88a894 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/fast-math-vect-reduc-7.c
+++ b/gcc/testsuite/gcc.dg/vect/fast-math-vect-reduc-7.c
@@ -50,5 +50,6 @@ int main (void)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { xfail vect_no_compare_double } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_compare_double } } } */
 /* { dg-final { cleanup-tree-dump "vect" } } */

diff --git a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-69.c b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-69.c
index 6da9bfb..7ed505b 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-69.c
+++ b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-69.c
@@ -3,7 +3,7 @@
 #include <stdarg.h>
 #include "tree-vect.h"
 
-#define N 32
+#define N 8
 
 struct s{
   int m;
@@ -113,5 +113,5 @@ int main (void)
 
 /* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" } } */
 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
-/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 3 "vect" } } */
 /* { dg-final { cleanup-tree-dump "vect" } } */

diff --git a/gcc/testsuite/gcc.dg/vect/vect-70.c b/gcc/testsuite/gcc.dg/vect/vect-70.c
index cc2e4bd..4e209d4 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-70.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-70.c
@@ -3,7 +3,7 @@
 #include <stdarg.h>
 #include "tree-vect.h"
 
-#define N 16
+#define N 12
 
 struct s{
   int m;

diff --git a/gcc/testsuite/gcc.dg/vect/vect.exp b/gcc/testsuite/gcc.dg/vect/vect.exp
index 49b3d8d..0de2be3 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect.exp
+++ b/gcc/testsuite/gcc.dg/vect/vect.exp
@@ -52,6 +52,8 @@ if [istarget "powerpc*-*-*"] {
        }
        set dg-do-what-default compile
     }
+} elseif { [istarget  "spu-*-*"] } {
+   set dg-do-what-default run
 } elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
     lappend DEFAULT_VECTCFLAGS "-msse2"
     set dg-do-what-default run

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index e52139d..4dd0b8e 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1249,6 +1249,7 @@ proc check_effective_target_vect_int { } {
        set et_vect_int_saved 0
        if { [istarget i?86-*-*]
              || [istarget powerpc*-*-*]
+             || [istarget spu-*-*]
              || [istarget x86_64-*-*]
              || [istarget sparc*-*-*]
              || [istarget alpha*-*-*]
@@ -1398,6 +1399,7 @@ proc check_effective_target_vect_float { } {
        set et_vect_float_saved 0
        if { [istarget i?86-*-*]
              || [istarget powerpc*-*-*]
+             || [istarget spu-*-*]
              || [istarget mipsisa64*-*-*]
              || [istarget x86_64-*-*]
              || [istarget ia64-*-*] } {
@@ -1421,7 +1423,8 @@ proc check_effective_target_vect_double { } {
     } else {
        set et_vect_double_saved 0
        if { [istarget i?86-*-*]
-             || [istarget x86_64-*-*] } {
+             || [istarget x86_64-*-*] 
+             || [istarget spu-*-*] } {
           set et_vect_double_saved 1
        }
     }
@@ -1430,6 +1433,26 @@ proc check_effective_target_vect_double { } {
     return $et_vect_double_saved
 }
 
+# Return 0 if the target supports hardware comparison of vectors of double, 0 otherwise.
+#
+# This won't change for different subtargets so cache the result.
+
+proc check_effective_target_vect_no_compare_double { } {
+    global et_vect_no_compare_double_saved
+
+    if [info exists et_vect_no_compare_double_saved] {
+        verbose "check_effective_target_vect_no_compare_double: using cached result" 2
+    } else {
+        set et_vect_no_compare_double_saved 0
+        if { [istarget spu-*-*] } {
+           set et_vect_no_compare_double_saved 1
+        }
+    }
+
+    verbose "check_effective_target_vect_no_compare_double: returning $et_vect_no_compare_double_saved" 2
+    return $et_vect_no_compare_double_saved
+}
+
 # Return 1 if the target plus current options does not support a vector
 # max instruction on "int", 0 otherwise.
 #
@@ -1443,6 +1466,7 @@ proc check_effective_target_vect_no_int_max { } {
     } else {
        set et_vect_no_int_max_saved 0
        if { [istarget sparc*-*-*]
+            || [istarget spu-*-*]
             || [istarget alpha*-*-*] } {
            set et_vect_no_int_max_saved 1
        }
@@ -1751,6 +1775,7 @@ proc check_effective_target_vect_no_align { } {
     } else {
        set et_vect_no_align_saved 0
        if { [istarget mipsisa64*-*-*]
+            || [istarget spu-*-*]
             || [istarget sparc*-*-*]
             || [istarget ia64-*-*] } {
            set et_vect_no_align_saved 1