PR target/35768

	* pa.md: Define mode iterator P.  Define mode attribute dwc.
	(dcacheflush): Update pattern to use iterator P and attribute dwc.
	(icacheflush): Likewise.
	* pa.h (INITIALIZE_TRAMPOLINE): Use dcacheflushsi/icacheflushsi if
	!TARGET_64BIT, and dcacheflushdi/icacheflushdi if TARGET_64BIT.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@134182 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3a3d622..5fbf40d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2008-04-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+       PR target/35768
+       * pa.md: Define mode iterator P.  Define mode attribute dwc.
+       (dcacheflush): Update pattern to use iterator P and attribute dwc.
+       (icacheflush): Likewise.
+       * pa.h (INITIALIZE_TRAMPOLINE): Use dcacheflushsi/icacheflushsi if
+       !TARGET_64BIT, and dcacheflushdi/icacheflushdi if TARGET_64BIT.
+

 2008-04-11  Ben Elliston  <bje@au.ibm.com>
 
        * config/spu/spu.c (spu_init_builtins): Mark builtins as nothrow.
 2008-04-11  Ben Elliston  <bje@au.ibm.com>
 
        * config/spu/spu.c (spu_init_builtins): Mark builtins as nothrow.

diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 48e595a..bcbacb4 100644 (file)
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -1,6 +1,6 @@
 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
 /* Definitions of target machine for GNU compiler, for the HP Spectrum.

-   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
+   2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.

    Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
    and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
    Software Science at the University of Utah.
    Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
    and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
    Software Science at the University of Utah.


@@ -921,8 +921,8 @@ extern int may_call_alloca;
       emit_insn (gen_andsi3 (end_addr, tmp,                            \
                             GEN_INT (-MIN_CACHELINE_SIZE)));           \
       emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));      \
       emit_insn (gen_andsi3 (end_addr, tmp,                            \
                             GEN_INT (-MIN_CACHELINE_SIZE)));           \
       emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));      \

-      emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
-      emit_insn (gen_icacheflush (start_addr, end_addr, line_length,   \
+      emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length));\
+      emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length, \

                                  gen_reg_rtx (Pmode),                  \
                                  gen_reg_rtx (Pmode)));                \
     }                                                                  \
                                  gen_reg_rtx (Pmode),                  \
                                  gen_reg_rtx (Pmode)));                \
     }                                                                  \


@@ -953,8 +953,8 @@ extern int may_call_alloca;
       emit_insn (gen_anddi3 (end_addr, tmp,                            \
                             GEN_INT (-MIN_CACHELINE_SIZE)));           \
       emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));      \
       emit_insn (gen_anddi3 (end_addr, tmp,                            \
                             GEN_INT (-MIN_CACHELINE_SIZE)));           \
       emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));      \

-      emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
-      emit_insn (gen_icacheflush (start_addr, end_addr, line_length,   \
+      emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length));\
+      emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length, \

                                  gen_reg_rtx (Pmode),                  \
                                  gen_reg_rtx (Pmode)));                \
     }                                                                  \
                                  gen_reg_rtx (Pmode),                  \
                                  gen_reg_rtx (Pmode)));                \
     }                                                                  \

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 2aca58d..ee6037a 100644 (file)
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -1,6 +1,6 @@
 ;;- Machine description for HP PA-RISC architecture for GCC compiler
 ;;   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
 ;;- Machine description for HP PA-RISC architecture for GCC compiler
 ;;   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,

-;;   2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+;;   2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.

 ;;   Contributed by the Center for Software Science at the University
 ;;   of Utah.
 
 ;;   Contributed by the Center for Software Science at the University
 ;;   of Utah.
 


@@ -64,6 +64,16 @@
    (MAX_17BIT_OFFSET   262100) ; 17-bit branch
   ])
 
    (MAX_17BIT_OFFSET   262100) ; 17-bit branch
   ])
 

+;; Mode and code iterators
+
+;; This mode iterator allows :P to be used for patterns that operate on
+;; pointer-sized quantities.  Exactly one of the two alternatives will match.
+(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+
+;; This attribute defines the condition prefix for word and double word
+;; add, compare, subtract and logical instructions.
+(define_mode_attr dwc [(SI "") (DI "*")])
+

 ;; Insn type.  Used to default other attribute values.
 
 ;; type "unary" insns have one input operand (1) and one output operand (0)
 ;; Insn type.  Used to default other attribute values.
 
 ;; type "unary" insns have one input operand (1) and one output operand (0)


@@ -9610,42 +9620,34 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
   [(set_attr "type" "fpalu")
    (set_attr "length" "4")])
 
   [(set_attr "type" "fpalu")
    (set_attr "length" "4")])
 

-;; Flush the I and D cache lines from the start address (operand0)
-;; to the end address (operand1).  No lines are flushed if the end
-;; address is less than the start address (unsigned).
+;; The following two patterns are used by the trampoline code for nested
+;; functions.  They flush the I and D cache lines from the start address
+;; (operand0) to the end address (operand1).  No lines are flushed if the
+;; end address is less than the start address (unsigned).

 ;;
 ;;

-;; Because the range of memory flushed is variable and the size of
-;; a MEM can only be a CONST_INT, the patterns specify that they
-;; perform an unspecified volatile operation on all memory.
+;; Because the range of memory flushed is variable and the size of a MEM
+;; can only be a CONST_INT, the patterns specify that they perform an
+;; unspecified volatile operation on all memory.

 ;;
 ;; The address range for an icache flush must lie within a single
 ;; space on targets with non-equivalent space registers.
 ;;
 ;;
 ;; The address range for an icache flush must lie within a single
 ;; space on targets with non-equivalent space registers.
 ;;

-;; This is used by the trampoline code for nested functions.
-;;

 ;; Operand 0 contains the start address.
 ;; Operand 1 contains the end address.
 ;; Operand 2 contains the line length to use.
 ;; Operand 0 contains the start address.
 ;; Operand 1 contains the end address.
 ;; Operand 2 contains the line length to use.

-;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
-(define_insn "dcacheflush"
+(define_insn "dcacheflush<P:mode>"

   [(const_int 1)
    (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
    (use (match_operand 0 "pmode_register_operand" "r"))
    (use (match_operand 1 "pmode_register_operand" "r"))
    (use (match_operand 2 "pmode_register_operand" "r"))
   [(const_int 1)
    (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
    (use (match_operand 0 "pmode_register_operand" "r"))
    (use (match_operand 1 "pmode_register_operand" "r"))
    (use (match_operand 2 "pmode_register_operand" "r"))

-   (clobber (match_scratch 3 "=&0"))]
+   (clobber (match_scratch:P 3 "=&0"))]

   ""
   ""

-  "*
-{
-  if (TARGET_64BIT)
-    return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
-  else
-    return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
-}"
+  "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"

   [(set_attr "type" "multi")
    (set_attr "length" "12")])
 
   [(set_attr "type" "multi")
    (set_attr "length" "12")])
 

-(define_insn "icacheflush"
+(define_insn "icacheflush<P:mode>"

   [(const_int 2)
    (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
    (use (match_operand 0 "pmode_register_operand" "r"))
   [(const_int 2)
    (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
    (use (match_operand 0 "pmode_register_operand" "r"))


@@ -9653,15 +9655,9 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
    (use (match_operand 2 "pmode_register_operand" "r"))
    (clobber (match_operand 3 "pmode_register_operand" "=&r"))
    (clobber (match_operand 4 "pmode_register_operand" "=&r"))
    (use (match_operand 2 "pmode_register_operand" "r"))
    (clobber (match_operand 3 "pmode_register_operand" "=&r"))
    (clobber (match_operand 4 "pmode_register_operand" "=&r"))

-   (clobber (match_scratch 5 "=&0"))]
+   (clobber (match_scratch:P 5 "=&0"))]

   ""
   ""

-  "*
-{
-  if (TARGET_64BIT)
-    return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
-  else
-    return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
-}"
+  "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"

   [(set_attr "type" "multi")
    (set_attr "length" "52")])
 
   [(set_attr "type" "multi")
    (set_attr "length" "52")])