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* config/i386/i386.md (splitters for int-float conversion): Use
authoruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 1 Nov 2011 21:36:30 +0000 (21:36 +0000)
committeruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 1 Nov 2011 21:36:30 +0000 (21:36 +0000)
reg_or_subregno in splitter constraints.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180745 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/i386/i386.md

index 5f33433..6027b43 100644 (file)
@@ -1,16 +1,21 @@
+2011-11-01  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (splitters for int-float conversion): Use
+       reg_or_subregno in splitter constraints.
+
 2011-11-01  Jakub Jelinek  <jakub@redhat.com>
 
        * config/i386/i386-protos.h (ix86_expand_adjust_ufix_to_sfix_si): New
        prototype.
        * config/i386/i386.c (ix86_expand_adjust_ufix_to_sfix_si): New
        function.
-       * config/i386/sse.md (fixuns_trunc<mode><sseintvecmodelower>2): Use
-       it.
+       * config/i386/sse.md (fixuns_trunc<mode><sseintvecmodelower>2): Use it.
        (ssepackfltmode): New mode attr.
        (vec_pack_ufix_trunc_<mode>): New expander.
 
-2011-10-30  Uros Bizjak  <ubizjak@gmail.com>
+2011-11-01  Uros Bizjak  <ubizjak@gmail.com>
 
+       PR target/50940
        * config/i386/i386.md (floatsi<mode>2_vector_sse_with_temp splitter):
        Compare <ssevecmode>mode with V4SFmode, not V4SImode.
 
@@ -46,7 +51,7 @@
        * config/avr/avr.h (BRANCH_COST): Define to avr_branch_cost.
        * config/avr/avr.c (avr_rtx_costs_1): Adjust [U]DIV/[U]MOD costs.
        * config/avr/avr.md (*addqi3.lt0, *addhi3.lt0, *addsi3.lt0): New insns.
-       (*addhi3_zero_extend1): Remov % in constraint of operand 1.
+       (*addhi3_zero_extend1): Remove % in constraint of operand 1.
        (*addhi3.sign_extend1, *subhi3.sign_extend2): New insns.
 
 2011-11-01  Tom de Vries  <tom@codesourcery.com>
index a8ebfa4..4fae10d 100644 (file)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
    && TARGET_INTER_UNIT_CONVERSIONS
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-          && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
 (define_split
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-          && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(set (match_dup 2) (match_dup 1))
    (set (match_dup 0) (float:MODEF (match_dup 2)))])
 
   "TARGET_SSE2 && TARGET_SSE_MATH
    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-          && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(const_int 0)]
 {
   rtx op1 = operands[1];
   "TARGET_SSE2 && TARGET_SSE_MATH
    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-          && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(const_int 0)]
 {
   operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
   "TARGET_SSE2 && TARGET_SSE_MATH
    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-          && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(const_int 0)]
 {
   rtx op1 = operands[1];
   "TARGET_SSE2 && TARGET_SSE_MATH
    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-          && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(const_int 0)]
 {
   operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-          && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
 (define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit"
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-          && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(set (match_dup 2) (match_dup 1))
    (set (match_dup 0) (float:MODEF (match_dup 2)))])
 
   "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
    && reload_completed
-   && (SSE_REG_P (operands[0])
-       || (GET_CODE (operands[0]) == SUBREG
-          && SSE_REG_P (operands[0])))"
+   && SSE_REGNO_P (reg_or_subregno (operands[0]))"
   [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
 (define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp"