* config/i386/i386.md (*bt<mode>): Macroize insn from *btsi and

	*btdi_rex64 using SWI48 mode iterator.
	(*jcc_bt<mode>): Ditto from *jcc_btsi and *jcc_btdi_rex64.
	(*jcc_bt<mode>_mask): Ditto from *jcc_btsi_mask and
	*jcc_btdi_mask_rex64.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158438 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index dbec827..2562c03 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2010-04-16  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (*bt<mode>): Macroize insn from *btsi and
+       *btdi_rex64 using SWI48 mode iterator.
+       (*jcc_bt<mode>): Ditto from *jcc_btsi and *jcc_btdi_rex64.
+       (*jcc_bt<mode>_mask): Ditto from *jcc_btsi_mask and
+       *jcc_btdi_mask_rex64.
+

 2010-04-16  Anatoly Sokolov  <aesok@post.ru>
 
        * double-int.h (tree_to_double_int): Convert to macro.
 2010-04-16  Anatoly Sokolov  <aesok@post.ru>
 
        * double-int.h (tree_to_double_int): Convert to macro.


@@ -303,7 +311,7 @@
        (logic): Ditto from logicprefix.
        (absneg_mnemonic): Ditto from absnegprefix.
        * config/i386/mmx.md: Update all users of maxminiprefix,
        (logic): Ditto from logicprefix.
        (absneg_mnemonic): Ditto from absnegprefix.
        * config/i386/mmx.md: Update all users of maxminiprefix,

-       maxminfprefix and loficprefix for rename.
+       maxminfprefix and logicprefix for rename.

        * config/i386/sse.md: Ditto.
        * config/i386/sync.md (sync_<code><mode>): Update for
        logicprefix rename.
        * config/i386/sse.md: Ditto.
        * config/i386/sync.md (sync_<code><mode>): Update for
        logicprefix rename.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 3a87177..d142c7f 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -85,7 +85,6 @@
    (UNSPEC_SET_RIP             16)
    (UNSPEC_SET_GOT_OFFSET      17)
    (UNSPEC_MEMORY_BLOCKAGE     18)
    (UNSPEC_SET_RIP             16)
    (UNSPEC_SET_GOT_OFFSET      17)
    (UNSPEC_MEMORY_BLOCKAGE     18)

-   (UNSPEC_SSE_PROLOGUE_SAVE_LOW 19)

 
    ; TLS support
    (UNSPEC_TP                  20)
 
    ; TLS support
    (UNSPEC_TP                  20)


@@ -343,7 +342,7 @@
 \f
 ;; Processor type.
 (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom,
 \f
 ;; Processor type.
 (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom,

-                   generic64,amdfam10,bdver1"
+                   generic64,amdfam10"

   (const (symbol_ref "ix86_schedule")))
 
 ;; A basic instruction type.  Refinements due to arguments to be
   (const (symbol_ref "ix86_schedule")))
 
 ;; A basic instruction type.  Refinements due to arguments to be


@@ -2380,13 +2379,11 @@
    && !x86_64_immediate_operand (operands[1], DImode) && 1"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2) (match_dup 3))]
    && !x86_64_immediate_operand (operands[1], DImode) && 1"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2) (match_dup 3))]

-{
-  split_di (&operands[1], 1, &operands[2], &operands[3]);
-
-  operands[1] = gen_lowpart (DImode, operands[2]);
-  operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
-                                                  GEN_INT (4)));
-})
+  "split_di (&operands[1], 1, &operands[2], &operands[3]);
+   operands[1] = gen_lowpart (DImode, operands[2]);
+   operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
+                                                   GEN_INT (4)));
+  ")

 
 (define_split
   [(set (match_operand:DI 0 "push_operand" "")
 
 (define_split
   [(set (match_operand:DI 0 "push_operand" "")


@@ -2397,13 +2394,11 @@
    && !x86_64_immediate_operand (operands[1], DImode)"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2) (match_dup 3))]
    && !x86_64_immediate_operand (operands[1], DImode)"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2) (match_dup 3))]

-{
-  split_di (&operands[1], 1, &operands[2], &operands[3]);
-
-  operands[1] = gen_lowpart (DImode, operands[2]);
-  operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
-                                                  GEN_INT (4)));
-})
+  "split_di (&operands[1], 1, &operands[2], &operands[3]);
+   operands[1] = gen_lowpart (DImode, operands[2]);
+   operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
+                                                   GEN_INT (4)));
+  ")

 
 (define_insn "*pushdi2_prologue_rex64"
   [(set (match_operand:DI 0 "push_operand" "=<")
 
 (define_insn "*pushdi2_prologue_rex64"
   [(set (match_operand:DI 0 "push_operand" "=<")


@@ -3113,15 +3108,9 @@
        case MODE_V4SF:
          return "%vxorps\t%0, %d0";
        case MODE_V2DF:
        case MODE_V4SF:
          return "%vxorps\t%0, %d0";
        case MODE_V2DF:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vxorps\t%0, %d0";
-         else
-           return "%vxorpd\t%0, %d0";
+         return "%vxorpd\t%0, %d0";

        case MODE_TI:
        case MODE_TI:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vxorps\t%0, %d0";
-         else
-           return "%vpxor\t%0, %d0";
+         return "%vpxor\t%0, %d0";

        default:
          gcc_unreachable ();
        }
        default:
          gcc_unreachable ();
        }


@@ -3133,15 +3122,9 @@
        case MODE_V4SF:
          return "%vmovaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:
        case MODE_V4SF:
          return "%vmovaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vmovaps\t{%1, %0|%0, %1}";
-         else
-           return "%vmovapd\t{%1, %0|%0, %1}";
+         return "%vmovapd\t{%1, %0|%0, %1}";

        case MODE_TI:
        case MODE_TI:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vmovaps\t{%1, %0|%0, %1}";
-         else
-           return "%vmovdqa\t{%1, %0|%0, %1}";
+         return "%vmovdqa\t{%1, %0|%0, %1}";

        case MODE_DI:
          return "%vmovq\t{%1, %0|%0, %1}";
        case MODE_DF:
        case MODE_DI:
          return "%vmovq\t{%1, %0|%0, %1}";
        case MODE_DF:


@@ -3275,15 +3258,9 @@
        case MODE_V4SF:
          return "%vxorps\t%0, %d0";
        case MODE_V2DF:
        case MODE_V4SF:
          return "%vxorps\t%0, %d0";
        case MODE_V2DF:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vxorps\t%0, %d0";
-         else
-           return "%vxorpd\t%0, %d0";
+         return "%vxorpd\t%0, %d0";

        case MODE_TI:
        case MODE_TI:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vxorps\t%0, %d0";
-         else
-           return "%vpxor\t%0, %d0";
+         return "%vpxor\t%0, %d0";

        default:
          gcc_unreachable ();
        }
        default:
          gcc_unreachable ();
        }


@@ -3295,15 +3272,9 @@
        case MODE_V4SF:
          return "%vmovaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:
        case MODE_V4SF:
          return "%vmovaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vmovaps\t{%1, %0|%0, %1}";
-         else
-           return "%vmovapd\t{%1, %0|%0, %1}";
+         return "%vmovapd\t{%1, %0|%0, %1}";

        case MODE_TI:
        case MODE_TI:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "%vmovaps\t{%1, %0|%0, %1}";
-         else
-           return "%vmovdqa\t{%1, %0|%0, %1}";
+         return "%vmovdqa\t{%1, %0|%0, %1}";

        case MODE_DI:
          return "%vmovq\t{%1, %0|%0, %1}";
        case MODE_DF:
        case MODE_DI:
          return "%vmovq\t{%1, %0|%0, %1}";
        case MODE_DF:


@@ -3427,15 +3398,9 @@
        case MODE_V4SF:
          return "xorps\t%0, %0";
        case MODE_V2DF:
        case MODE_V4SF:
          return "xorps\t%0, %0";
        case MODE_V2DF:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "xorps\t%0, %0";
-         else
-           return "xorpd\t%0, %0";
+         return "xorpd\t%0, %0";

        case MODE_TI:
        case MODE_TI:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "xorps\t%0, %0";
-         else
-           return "pxor\t%0, %0";
+         return "pxor\t%0, %0";

        default:
          gcc_unreachable ();
        }
        default:
          gcc_unreachable ();
        }


@@ -3447,15 +3412,9 @@
        case MODE_V4SF:
          return "movaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:
        case MODE_V4SF:
          return "movaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "movaps\t{%1, %0|%0, %1}";
-         else
-           return "movapd\t{%1, %0|%0, %1}";
+         return "movapd\t{%1, %0|%0, %1}";

        case MODE_TI:
        case MODE_TI:

-         if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
-           return "movaps\t{%1, %0|%0, %1}";
-         else
-           return "movdqa\t{%1, %0|%0, %1}";
+         return "movdqa\t{%1, %0|%0, %1}";

        case MODE_DI:
          return "movq\t{%1, %0|%0, %1}";
        case MODE_DF:
        case MODE_DI:
          return "movq\t{%1, %0|%0, %1}";
        case MODE_DF:


@@ -7967,7 +7926,7 @@
              (use (match_dup 1))
              (clobber (reg:CC FLAGS_REG))])]
 {
              (use (match_dup 1))
              (clobber (reg:CC FLAGS_REG))])]
 {

-  operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
+  operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);

 
   if (<MODE>mode != HImode
       && (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD))
 
   if (<MODE>mode != HImode
       && (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD))


@@ -9884,10 +9843,6 @@
       gcc_assert (operands[2] == const1_rtx);
       return "add{w}\t%0, %0";
 
       gcc_assert (operands[2] == const1_rtx);
       return "add{w}\t%0, %0";
 

-    case TYPE_ALU:
-      gcc_assert (operands[2] == const1_rtx);
-      return "add{w}\t%0, %0";
-

     default:
       if (operands[2] == const1_rtx
          && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
     default:
       if (operands[2] == const1_rtx
          && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))


@@ -11318,7 +11273,7 @@
 
 ;; Avoid useless masking of bit offset operand.  "and" in SImode is correct
 ;; also for DImode, this is what combine produces.
 
 ;; Avoid useless masking of bit offset operand.  "and" in SImode is correct
 ;; also for DImode, this is what combine produces.

-(define_insn_and_split "*jcc_bt<mode>_mask"
+define_insn_and_split "*jcc_bt<mode>_mask"

   [(set (pc)
        (if_then_else (match_operator 0 "bt_comparison_operator"
                        [(zero_extract:SWI48
   [(set (pc)
        (if_then_else (match_operator 0 "bt_comparison_operator"
                        [(zero_extract:SWI48


@@ -11577,7 +11532,6 @@
   [(const_int 0)]
 {
   operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[2]);
   [(const_int 0)]
 {
   operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[2]);

-

   ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
                        operands[3], operands[7],
                        operands[4], operands[5], operands[6], NULL_RTX);
   ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
                        operands[3], operands[7],
                        operands[4], operands[5], operands[6], NULL_RTX);


@@ -11601,7 +11555,6 @@
 {
   operands[7] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
   operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[7]);
 {
   operands[7] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
   operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[7]);

-

   ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
                        operands[3], operands[7],
                        operands[4], operands[5], operands[6], operands[2]);
   ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
                        operands[3], operands[7],
                        operands[4], operands[5], operands[6], operands[2]);


@@ -12221,33 +12174,38 @@
   "leave"
   [(set_attr "type" "leave")])
 \f
   "leave"
   [(set_attr "type" "leave")])
 \f

-;; Bit manipulation instructions.
+(define_expand "ffssi2"
+  [(parallel
+     [(set (match_operand:SI 0 "register_operand" "")
+          (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
+      (clobber (match_scratch:SI 2 ""))
+      (clobber (reg:CC FLAGS_REG))])]
+  ""
+{
+  if (TARGET_CMOVE)
+    {
+      emit_insn (gen_ffs_cmove (operands[0], operands[1]));
+      DONE;
+    }
+})

 
 

-(define_expand "ffs<mode>2"
+(define_expand "ffs_cmove"

   [(set (match_dup 2) (const_int -1))
    (parallel [(set (reg:CCZ FLAGS_REG)
   [(set (match_dup 2) (const_int -1))
    (parallel [(set (reg:CCZ FLAGS_REG)

-                  (compare:CCZ
-                    (match_operand:SWI48 1 "nonimmediate_operand" "")
-                    (const_int 0)))
-             (set (match_operand:SWI48 0 "register_operand" "")
-                  (ctz:SWI48 (match_dup 1)))])
-   (set (match_dup 0) (if_then_else:SWI48
+                  (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "")
+                               (const_int 0)))
+             (set (match_operand:SI 0 "register_operand" "")
+                  (ctz:SI (match_dup 1)))])
+   (set (match_dup 0) (if_then_else:SI

                        (eq (reg:CCZ FLAGS_REG) (const_int 0))
                        (match_dup 2)
                        (match_dup 0)))
                        (eq (reg:CCZ FLAGS_REG) (const_int 0))
                        (match_dup 2)
                        (match_dup 0)))

-   (parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (const_int 1)))
+   (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))

              (clobber (reg:CC FLAGS_REG))])]
              (clobber (reg:CC FLAGS_REG))])]

-  ""
-{
-  if (<MODE>mode == SImode && !TARGET_CMOVE)
-    {
-      emit_insn (gen_ffssi2_no_cmove (operands[0], operands [1]));
-      DONE;
-    }
-  operands[2] = gen_reg_rtx (<MODE>mode);
-})
+  "TARGET_CMOVE"
+  "operands[2] = gen_reg_rtx (SImode);")

 
 

-(define_insn_and_split "ffssi2_no_cmove"
+(define_insn_and_split "*ffs_no_cmove"

   [(set (match_operand:SI 0 "register_operand" "=r")
        (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
    (clobber (match_scratch:SI 2 "=&q"))
   [(set (match_operand:SI 0 "register_operand" "=r")
        (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
    (clobber (match_scratch:SI 2 "=&q"))


@@ -12271,68 +12229,93 @@
   ix86_expand_clear (operands[2]);
 })
 
   ix86_expand_clear (operands[2]);
 })
 

-(define_insn "*ffs<mode>_1"
+(define_insn "*ffssi_1"

   [(set (reg:CCZ FLAGS_REG)
   [(set (reg:CCZ FLAGS_REG)

-       (compare:CCZ (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+       (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")

                     (const_int 0)))
                     (const_int 0)))

-   (set (match_operand:SWI48 0 "register_operand" "=r")
-       (ctz:SWI48 (match_dup 1)))]
+   (set (match_operand:SI 0 "register_operand" "=r")
+       (ctz:SI (match_dup 1)))]

   ""
   ""

-  "bsf{<imodesuffix>}\t{%1, %0|%0, %1}"
+  "bsf{l}\t{%1, %0|%0, %1}"

   [(set_attr "type" "alu1")
    (set_attr "prefix_0f" "1")
   [(set_attr "type" "alu1")
    (set_attr "prefix_0f" "1")

-   (set_attr "mode" "<MODE>")])
+   (set_attr "mode" "SI")])

 
 

-(define_insn "ctz<mode>2"
-  [(set (match_operand:SWI48 0 "register_operand" "=r")
-       (ctz:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
+(define_expand "ffsdi2"
+  [(set (match_dup 2) (const_int -1))
+   (parallel [(set (reg:CCZ FLAGS_REG)
+                  (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "")
+                               (const_int 0)))
+             (set (match_operand:DI 0 "register_operand" "")
+                  (ctz:DI (match_dup 1)))])
+   (set (match_dup 0) (if_then_else:DI
+                       (eq (reg:CCZ FLAGS_REG) (const_int 0))
+                       (match_dup 2)
+                       (match_dup 0)))
+   (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
+             (clobber (reg:CC FLAGS_REG))])]
+  "TARGET_64BIT"
+  "operands[2] = gen_reg_rtx (DImode);")
+
+(define_insn "*ffsdi_1"
+  [(set (reg:CCZ FLAGS_REG)
+       (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
+                    (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+       (ctz:DI (match_dup 1)))]
+  "TARGET_64BIT"
+  "bsf{q}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "DI")])
+
+(define_insn "ctzsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))

    (clobber (reg:CC FLAGS_REG))]
   ""
    (clobber (reg:CC FLAGS_REG))]
   ""

-  "bsf{<imodesuffix>}\t{%1, %0|%0, %1}"
+  "bsf{l}\t{%1, %0|%0, %1}"

   [(set_attr "type" "alu1")
    (set_attr "prefix_0f" "1")
   [(set_attr "type" "alu1")
    (set_attr "prefix_0f" "1")

-   (set_attr "mode" "<MODE>")])
+   (set_attr "mode" "SI")])
+
+(define_insn "ctzdi2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_64BIT"
+  "bsf{q}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "DI")])

 
 

-(define_expand "clz<mode>2"
+(define_expand "clzsi2"

   [(parallel
   [(parallel

-     [(set (match_operand:SWI248 0 "register_operand" "")
-          (minus:SWI248
-            (match_dup 2)
-            (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" ""))))
+     [(set (match_operand:SI 0 "register_operand" "")
+          (minus:SI (const_int 31)
+                    (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))

       (clobber (reg:CC FLAGS_REG))])
    (parallel
       (clobber (reg:CC FLAGS_REG))])
    (parallel

-     [(set (match_dup 0) (xor:SWI248 (match_dup 0) (match_dup 2)))
+     [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))

       (clobber (reg:CC FLAGS_REG))])]
   ""
 {
   if (TARGET_ABM)
     {
       (clobber (reg:CC FLAGS_REG))])]
   ""
 {
   if (TARGET_ABM)
     {

-      emit_insn (gen_clz<mode>2_abm (operands[0], operands[1]));
+      emit_insn (gen_clzsi2_abm (operands[0], operands[1]));

       DONE;
     }
       DONE;
     }

-  operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);

 })
 
 })
 

-(define_insn "clz<mode>2_abm"
-  [(set (match_operand:SWI248 0 "register_operand" "=r")
-       (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
+(define_insn "clzsi2_abm"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))

    (clobber (reg:CC FLAGS_REG))]
   "TARGET_ABM"
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_ABM"

-  "lzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
+  "lzcnt{l}\t{%1, %0|%0, %1}"

   [(set_attr "prefix_rep" "1")
    (set_attr "type" "bitmanip")
   [(set_attr "prefix_rep" "1")
    (set_attr "type" "bitmanip")

-   (set_attr "mode" "<MODE>")])
-
-(define_insn "bsr_rex64"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (minus:DI (const_int 63)
-                 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT"
-  "bsr{q}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "alu1")
-   (set_attr "prefix_0f" "1")
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "SI")])

 
 (define_insn "bsr"
   [(set (match_operand:SI 0 "register_operand" "=r")
 
 (define_insn "bsr"
   [(set (match_operand:SI 0 "register_operand" "=r")


@@ -12345,17 +12328,6 @@
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "SI")])
 
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "SI")])
 

-(define_insn "*bsrhi"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-       (minus:HI (const_int 15)
-                 (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
-   (clobber (reg:CC FLAGS_REG))]
-  ""
-  "bsr{w}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "alu1")
-   (set_attr "prefix_0f" "1")
-   (set_attr "mode" "HI")])
-

 (define_insn "popcount<mode>2"
   [(set (match_operand:SWI248 0 "register_operand" "=r")
        (popcount:SWI248
 (define_insn "popcount<mode>2"
   [(set (match_operand:SWI248 0 "register_operand" "=r")
        (popcount:SWI248


@@ -12386,7 +12358,7 @@
 #if TARGET_MACHO
   return "popcnt\t{%1, %0|%0, %1}";
 #else
 #if TARGET_MACHO
   return "popcnt\t{%1, %0|%0, %1}";
 #else

-  return "popcnt{l}\t{%1, %0|%0, %1}";
+  return "popcnt{<imodesuffix>}\t{%1, %0|%0, %1}";

 #endif
 }
   [(set_attr "prefix_rep" "1")
 #endif
 }
   [(set_attr "prefix_rep" "1")


@@ -12412,12 +12384,12 @@
    (set_attr "type" "bitmanip")
    (set_attr "mode" "SI")])
 
    (set_attr "type" "bitmanip")
    (set_attr "mode" "SI")])
 

-(define_expand "bswap<mode>2"
-  [(set (match_operand:SWI48 0 "register_operand" "")
-       (bswap:SWI48 (match_operand:SWI48 1 "register_operand" "")))]
+(define_expand "bswapsi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+       (bswap:SI (match_operand:SI 1 "register_operand" "")))]

   ""
 {
   ""
 {

-  if (<MODE>mode == SImode && !(TARGET_BSWAP || TARGET_MOVBE))
+  if (!(TARGET_BSWAP || TARGET_MOVBE))

     {
       rtx x = operands[0];
 
     {
       rtx x = operands[0];
 


@@ -12429,29 +12401,28 @@
     }
 })
 
     }
 })
 

-(define_insn "*bswap<mode>2_movbe"
-  [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,r,m")
-       (bswap:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,m,r")))]
-  "TARGET_MOVBE
-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+(define_insn "*bswapsi_movbe"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m")
+       (bswap:SI (match_operand:SI 1 "nonimmediate_operand" "0,m,r")))]
+  "TARGET_MOVBE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"

   "@
     bswap\t%0
     movbe\t{%1, %0|%0, %1}
     movbe\t{%1, %0|%0, %1}"
   "@
     bswap\t%0
     movbe\t{%1, %0|%0, %1}
     movbe\t{%1, %0|%0, %1}"

-  [(set_attr "type" "bitmanip,imov,imov")
-   (set_attr "modrm" "0,1,1")
-   (set_attr "prefix_0f" "*,1,1")
+  [(set_attr "type" "*,imov,imov")
+   (set_attr "modrm" "*,1,1")
+   (set_attr "prefix_0f" "1")

    (set_attr "prefix_extra" "*,1,1")
    (set_attr "prefix_extra" "*,1,1")

-   (set_attr "mode" "<MODE>")])
+   (set_attr "length" "2,*,*")
+   (set_attr "mode" "SI")])

 
 

-(define_insn "*bswap<mode>2_1"
-  [(set (match_operand:SWI48 0 "register_operand" "=r")
-       (bswap:SWI48 (match_operand:SWI48 1 "register_operand" "0")))]
+(define_insn "*bswapsi_1"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (bswap:SI (match_operand:SI 1 "register_operand" "0")))]

   "TARGET_BSWAP"
   "bswap\t%0"
   "TARGET_BSWAP"
   "bswap\t%0"

-  [(set_attr "type" "bitmanip")
-   (set_attr "modrm" "0")
-   (set_attr "mode" "<MODE>")])
+  [(set_attr "prefix_0f" "1")
+   (set_attr "length" "2")])

 
 (define_insn "*bswaphi_lowpart_1"
   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+Q,r"))
 
 (define_insn "*bswaphi_lowpart_1"
   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+Q,r"))


@@ -12473,6 +12444,114 @@
   [(set_attr "length" "4")
    (set_attr "mode" "HI")])
 
   [(set_attr "length" "4")
    (set_attr "mode" "HI")])
 

+(define_expand "bswapdi2"
+  [(set (match_operand:DI 0 "register_operand" "")
+       (bswap:DI (match_operand:DI 1 "register_operand" "")))]
+  "TARGET_64BIT"
+  "")
+
+(define_insn "*bswapdi_movbe"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
+       (bswap:DI (match_operand:DI 1 "nonimmediate_operand" "0,m,r")))]
+  "TARGET_64BIT && TARGET_MOVBE
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "@
+    bswap\t%0
+    movbe\t{%1, %0|%0, %1}
+    movbe\t{%1, %0|%0, %1}"
+  [(set_attr "type" "*,imov,imov")
+   (set_attr "modrm" "*,1,1")
+   (set_attr "prefix_0f" "1")
+   (set_attr "prefix_extra" "*,1,1")
+   (set_attr "length" "3,*,*")
+   (set_attr "mode" "DI")])
+
+(define_insn "*bswapdi_1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (bswap:DI (match_operand:DI 1 "register_operand" "0")))]
+  "TARGET_64BIT"
+  "bswap\t%0"
+  [(set_attr "prefix_0f" "1")
+   (set_attr "length" "3")])
+
+(define_expand "clzdi2"
+  [(parallel
+     [(set (match_operand:DI 0 "register_operand" "")
+          (minus:DI (const_int 63)
+                    (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
+      (clobber (reg:CC FLAGS_REG))])
+   (parallel
+     [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
+      (clobber (reg:CC FLAGS_REG))])]
+  "TARGET_64BIT"
+{
+  if (TARGET_ABM)
+    {
+      emit_insn (gen_clzdi2_abm (operands[0], operands[1]));
+      DONE;
+    }
+})
+
+(define_insn "clzdi2_abm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_64BIT && TARGET_ABM"
+  "lzcnt{q}\t{%1, %0|%0, %1}"
+  [(set_attr "prefix_rep" "1")
+   (set_attr "type" "bitmanip")
+   (set_attr "mode" "DI")])
+
+(define_insn "bsr_rex64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (minus:DI (const_int 63)
+                 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_64BIT"
+  "bsr{q}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "DI")])
+
+(define_expand "clzhi2"
+  [(parallel
+     [(set (match_operand:HI 0 "register_operand" "")
+          (minus:HI (const_int 15)
+                    (clz:HI (match_operand:HI 1 "nonimmediate_operand" ""))))
+      (clobber (reg:CC FLAGS_REG))])
+   (parallel
+     [(set (match_dup 0) (xor:HI (match_dup 0) (const_int 15)))
+      (clobber (reg:CC FLAGS_REG))])]
+  ""
+{
+  if (TARGET_ABM)
+    {
+      emit_insn (gen_clzhi2_abm (operands[0], operands[1]));
+      DONE;
+    }
+})
+
+(define_insn "clzhi2_abm"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+       (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_ABM"
+  "lzcnt{w}\t{%1, %0|%0, %1}"
+  [(set_attr "prefix_rep" "1")
+   (set_attr "type" "bitmanip")
+   (set_attr "mode" "HI")])
+
+(define_insn "*bsrhi"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+       (minus:HI (const_int 15)
+                 (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
+   (clobber (reg:CC FLAGS_REG))]
+  ""
+  "bsr{w}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "HI")])
+

 (define_expand "paritydi2"
   [(set (match_operand:DI 0 "register_operand" "")
        (parity:DI (match_operand:DI 1 "register_operand" "")))]
 (define_expand "paritydi2"
   [(set (match_operand:DI 0 "register_operand" "")
        (parity:DI (match_operand:DI 1 "register_operand" "")))]


@@ -12501,25 +12580,6 @@
   DONE;
 })
 
   DONE;
 })
 

-(define_expand "paritysi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-       (parity:SI (match_operand:SI 1 "register_operand" "")))]
-  "! TARGET_POPCNT"
-{
-  rtx scratch = gen_reg_rtx (QImode);
-  rtx cond;
-
-  emit_insn (gen_paritysi2_cmp (NULL_RTX, NULL_RTX, operands[1]));
-
-  cond = gen_rtx_fmt_ee (ORDERED, QImode,
-                        gen_rtx_REG (CCmode, FLAGS_REG),
-                        const0_rtx);
-  emit_insn (gen_rtx_SET (VOIDmode, scratch, cond));
-
-  emit_insn (gen_zero_extendqisi2 (operands[0], scratch));
-  DONE;
-})
-

 (define_insn_and_split "paritydi2_cmp"
   [(set (reg:CC FLAGS_REG)
        (parity:CC (match_operand:DI 3 "register_operand" "0")))
 (define_insn_and_split "paritydi2_cmp"
   [(set (reg:CC FLAGS_REG)
        (parity:CC (match_operand:DI 3 "register_operand" "0")))


@@ -12550,6 +12610,25 @@
     operands[1] = gen_highpart (SImode, operands[3]);
 })
 
     operands[1] = gen_highpart (SImode, operands[3]);
 })
 

+(define_expand "paritysi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+       (parity:SI (match_operand:SI 1 "register_operand" "")))]
+  "! TARGET_POPCNT"
+{
+  rtx scratch = gen_reg_rtx (QImode);
+  rtx cond;
+
+  emit_insn (gen_paritysi2_cmp (NULL_RTX, NULL_RTX, operands[1]));
+
+  cond = gen_rtx_fmt_ee (ORDERED, QImode,
+                        gen_rtx_REG (CCmode, FLAGS_REG),
+                        const0_rtx);
+  emit_insn (gen_rtx_SET (VOIDmode, scratch, cond));
+
+  emit_insn (gen_zero_extendqisi2 (operands[0], scratch));
+  DONE;
+})
+

 (define_insn_and_split "paritysi2_cmp"
   [(set (reg:CC FLAGS_REG)
        (parity:CC (match_operand:SI 2 "register_operand" "0")))
 (define_insn_and_split "paritysi2_cmp"
   [(set (reg:CC FLAGS_REG)
        (parity:CC (match_operand:SI 2 "register_operand" "0")))


@@ -15867,7 +15946,7 @@
        (mem:BLK (match_dup 4)))
    (use (match_dup 5))]
   "TARGET_64BIT"
        (mem:BLK (match_dup 4)))
    (use (match_dup 5))]
   "TARGET_64BIT"

-  "rep{%;} movsq"
+  "rep movsq"

   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "both")
   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "both")


@@ -15886,7 +15965,7 @@
        (mem:BLK (match_dup 4)))
    (use (match_dup 5))]
   "!TARGET_64BIT"
        (mem:BLK (match_dup 4)))
    (use (match_dup 5))]
   "!TARGET_64BIT"

-  "rep{%;} movs{l|d}"
+  "rep movs{l|d}"

   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "both")
   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "both")


@@ -15905,7 +15984,7 @@
        (mem:BLK (match_dup 4)))
    (use (match_dup 5))]
   "TARGET_64BIT"
        (mem:BLK (match_dup 4)))
    (use (match_dup 5))]
   "TARGET_64BIT"

-  "rep{%;} movs{l|d}"
+  "rep movs{l|d}"

   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "both")
   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "both")


@@ -15922,7 +16001,7 @@
        (mem:BLK (match_dup 4)))
    (use (match_dup 5))]
   "!TARGET_64BIT"
        (mem:BLK (match_dup 4)))
    (use (match_dup 5))]
   "!TARGET_64BIT"

-  "rep{%;} movsb"
+  "rep movsb"

   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "both")
   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "both")


@@ -15939,7 +16018,7 @@
        (mem:BLK (match_dup 4)))
    (use (match_dup 5))]
   "TARGET_64BIT"
        (mem:BLK (match_dup 4)))
    (use (match_dup 5))]
   "TARGET_64BIT"

-  "rep{%;} movsb"
+  "rep movsb"

   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "both")
   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "both")


@@ -16120,7 +16199,7 @@
    (use (match_operand:DI 2 "register_operand" "a"))
    (use (match_dup 4))]
   "TARGET_64BIT"
    (use (match_operand:DI 2 "register_operand" "a"))
    (use (match_dup 4))]
   "TARGET_64BIT"

-  "rep{%;} stosq"
+  "rep stosq"

   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "store")
   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "store")


@@ -16137,7 +16216,7 @@
    (use (match_operand:SI 2 "register_operand" "a"))
    (use (match_dup 4))]
   "!TARGET_64BIT"
    (use (match_operand:SI 2 "register_operand" "a"))
    (use (match_dup 4))]
   "!TARGET_64BIT"

-  "rep{%;} stos{l|d}"
+  "rep stos{l|d}"

   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "store")
   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "store")


@@ -16154,7 +16233,7 @@
    (use (match_operand:SI 2 "register_operand" "a"))
    (use (match_dup 4))]
   "TARGET_64BIT"
    (use (match_operand:SI 2 "register_operand" "a"))
    (use (match_dup 4))]
   "TARGET_64BIT"

-  "rep{%;} stos{l|d}"
+  "rep stos{l|d}"

   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "store")
   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "store")


@@ -16170,7 +16249,7 @@
    (use (match_operand:QI 2 "register_operand" "a"))
    (use (match_dup 4))]
   "!TARGET_64BIT"
    (use (match_operand:QI 2 "register_operand" "a"))
    (use (match_dup 4))]
   "!TARGET_64BIT"

-  "rep{%;} stosb"
+  "rep stosb"

   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "store")
   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "store")


@@ -16186,7 +16265,7 @@
    (use (match_operand:QI 2 "register_operand" "a"))
    (use (match_dup 4))]
   "TARGET_64BIT"
    (use (match_operand:QI 2 "register_operand" "a"))
    (use (match_dup 4))]
   "TARGET_64BIT"

-  "rep{%;} stosb"
+  "rep stosb"

   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "store")
   [(set_attr "type" "str")
    (set_attr "prefix_rep" "1")
    (set_attr "memory" "store")


@@ -16302,7 +16381,7 @@
    (clobber (match_operand:SI 1 "register_operand" "=D"))
    (clobber (match_operand:SI 2 "register_operand" "=c"))]
   "!TARGET_64BIT"
    (clobber (match_operand:SI 1 "register_operand" "=D"))
    (clobber (match_operand:SI 2 "register_operand" "=c"))]
   "!TARGET_64BIT"

-  "repz{%;} cmpsb"
+  "repz cmpsb"

   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rep" "1")])
   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rep" "1")])


@@ -16317,7 +16396,7 @@
    (clobber (match_operand:DI 1 "register_operand" "=D"))
    (clobber (match_operand:DI 2 "register_operand" "=c"))]
   "TARGET_64BIT"
    (clobber (match_operand:DI 1 "register_operand" "=D"))
    (clobber (match_operand:DI 2 "register_operand" "=c"))]
   "TARGET_64BIT"

-  "repz{%;} cmpsb"
+  "repz cmpsb"

   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rex" "0")
   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rex" "0")


@@ -16353,7 +16432,7 @@
    (clobber (match_operand:SI 1 "register_operand" "=D"))
    (clobber (match_operand:SI 2 "register_operand" "=c"))]
   "!TARGET_64BIT"
    (clobber (match_operand:SI 1 "register_operand" "=D"))
    (clobber (match_operand:SI 2 "register_operand" "=c"))]
   "!TARGET_64BIT"

-  "repz{%;} cmpsb"
+  "repz cmpsb"

   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rep" "1")])
   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rep" "1")])


@@ -16371,7 +16450,7 @@
    (clobber (match_operand:DI 1 "register_operand" "=D"))
    (clobber (match_operand:DI 2 "register_operand" "=c"))]
   "TARGET_64BIT"
    (clobber (match_operand:DI 1 "register_operand" "=D"))
    (clobber (match_operand:DI 2 "register_operand" "=c"))]
   "TARGET_64BIT"

-  "repz{%;} cmpsb"
+  "repz cmpsb"

   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rex" "0")
   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rex" "0")


@@ -16419,7 +16498,7 @@
    (clobber (match_operand:SI 1 "register_operand" "=D"))
    (clobber (reg:CC FLAGS_REG))]
   "!TARGET_64BIT"
    (clobber (match_operand:SI 1 "register_operand" "=D"))
    (clobber (reg:CC FLAGS_REG))]
   "!TARGET_64BIT"

-  "repnz{%;} scasb"
+  "repnz scasb"

   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rep" "1")])
   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rep" "1")])


@@ -16433,7 +16512,7 @@
    (clobber (match_operand:DI 1 "register_operand" "=D"))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
    (clobber (match_operand:DI 1 "register_operand" "=D"))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"

-  "repnz{%;} scasb"
+  "repnz scasb"

   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rex" "0")
   [(set_attr "type" "str")
    (set_attr "mode" "QI")
    (set_attr "prefix_rex" "0")


@@ -16704,10 +16783,8 @@
        (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
                      (match_dup 7)
                      (match_dup 8)))]
        (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
                      (match_dup 7)
                      (match_dup 8)))]

-{
-  split_di (&operands[2], 2, &operands[5], &operands[7]);
-  split_di (&operands[0], 1, &operands[2], &operands[3]);
-})
+  "split_di (&operands[2], 2, &operands[5], &operands[7]);
+   split_di (&operands[0], 1, &operands[2], &operands[3]);")

 
 (define_insn "*movxfcc_1"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 
 (define_insn "*movxfcc_1"
   [(set (match_operand:XF 0 "register_operand" "=f,f")


@@ -18364,113 +18441,13 @@
                                (reg:DI XMM5_REG)
                                (reg:DI XMM6_REG)
                                (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
                                (reg:DI XMM5_REG)
                                (reg:DI XMM6_REG)
                                (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))

-             (clobber (reg:CC FLAGS_REG))
-             (clobber (match_operand:DI 1 "register_operand" ""))
+             (use (match_operand:DI 1 "register_operand" ""))

              (use (match_operand:DI 2 "immediate_operand" ""))
              (use (match_operand:DI 2 "immediate_operand" ""))

-             (use (label_ref:DI (match_operand 3 "" "")))
-             (clobber (match_operand:DI 4 "register_operand" ""))
-             (use (match_dup 1))])]
+             (use (label_ref:DI (match_operand 3 "" "")))])]

   "TARGET_64BIT"
   "")
 
   "TARGET_64BIT"
   "")
 

-;; Pre-reload version of prologue save.  Until after prologue generation we don't know
-;; what the size of save instruction will be.
-;; Operand 0+operand 6 is the memory save area
-;; Operand 1 is number of registers to save (will get overwritten to operand 5)
-;; Operand 2 is number of non-vaargs SSE arguments
-;; Operand 3 is label starting the save block
-;; Operand 4 is used for temporary computation of jump address
-(define_insn "*sse_prologue_save_insn1"
-  [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
-                         (match_operand:DI 6 "const_int_operand" "n")))
-       (unspec:BLK [(reg:DI XMM0_REG)
-                    (reg:DI XMM1_REG)
-                    (reg:DI XMM2_REG)
-                    (reg:DI XMM3_REG)
-                    (reg:DI XMM4_REG)
-                    (reg:DI XMM5_REG)
-                    (reg:DI XMM6_REG)
-                    (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
-   (clobber (reg:CC FLAGS_REG))
-   (clobber (match_operand:DI 1 "register_operand" "=r"))
-   (use (match_operand:DI 2 "const_int_operand" "i"))
-   (use (label_ref:DI (match_operand 3 "" "X")))
-   (clobber (match_operand:DI 4 "register_operand" "=&r"))
-   (use (match_operand:DI 5 "register_operand" "1"))]
-  "TARGET_64BIT
-   && INTVAL (operands[6]) + X86_64_SSE_REGPARM_MAX * 16 - 16 < 128
-   && INTVAL (operands[6]) + INTVAL (operands[2]) * 16 >= -128"
-  "#"
-  [(set_attr "type" "other")
-   (set_attr "memory" "store")
-   (set_attr "mode" "DI")])
-
-;; We know size of save instruction; expand the computation of jump address
-;; in the jumptable.
-(define_split
-  [(parallel [(set (match_operand:BLK 0 "" "")
-                   (unspec:BLK [(reg:DI XMM0_REG)
-                                (reg:DI XMM1_REG)
-                                (reg:DI XMM2_REG)
-                                (reg:DI XMM3_REG)
-                                (reg:DI XMM4_REG)
-                                (reg:DI XMM5_REG)
-                                (reg:DI XMM6_REG)
-                                (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
-              (clobber (reg:CC FLAGS_REG))
-              (clobber (match_operand:DI 1 "register_operand" ""))
-              (use (match_operand:DI 2 "const_int_operand" ""))
-              (use (match_operand 3 "" ""))
-              (clobber (match_operand:DI 4 "register_operand" ""))
-              (use (match_operand:DI 5 "register_operand" ""))])]
-  "reload_completed"
-  [(parallel [(set (match_dup 0)
-                  (unspec:BLK [(reg:DI XMM0_REG)
-                               (reg:DI XMM1_REG)
-                               (reg:DI XMM2_REG)
-                               (reg:DI XMM3_REG)
-                               (reg:DI XMM4_REG)
-                               (reg:DI XMM5_REG)
-                               (reg:DI XMM6_REG)
-                               (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE_LOW))
-             (use (match_dup 1))
-             (use (match_dup 2))
-             (use (match_dup 3))
-             (use (match_dup 5))])]
-{
-  /* Movaps is 4 bytes, AVX and movsd is 5 bytes.  */
-  int size = 4 + (TARGET_AVX || crtl->stack_alignment_needed < 128);
-
-  /* Compute address to jump to:
-     label - eax*size + nnamed_sse_arguments*size. */
-  if (size == 5)
-    emit_insn (gen_rtx_SET (VOIDmode, operands[4],
-                           gen_rtx_PLUS
-                             (Pmode,
-                              gen_rtx_MULT (Pmode, operands[1],
-                                            GEN_INT (4)),
-                              operands[1])));
-  else  if (size == 4)
-    emit_insn (gen_rtx_SET (VOIDmode, operands[4],
-                           gen_rtx_MULT (Pmode, operands[1],
-                                         GEN_INT (4))));
-  else
-    gcc_unreachable ();
-  if (INTVAL (operands[2]))
-    emit_move_insn
-      (operands[1],
-       gen_rtx_CONST (DImode,
-                     gen_rtx_PLUS (DImode,
-                                   operands[3],
-                                   GEN_INT (INTVAL (operands[2])
-                                            * size))));
-  else
-    emit_move_insn (operands[1], operands[3]);
-  emit_insn (gen_subdi3 (operands[1], operands[1], operands[4]));
-  operands[5] = GEN_INT (size);
-})
-
-(define_insn "sse_prologue_save_insn"
+(define_insn "*sse_prologue_save_insn"

   [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
                          (match_operand:DI 4 "const_int_operand" "n")))
        (unspec:BLK [(reg:DI XMM0_REG)
   [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
                          (match_operand:DI 4 "const_int_operand" "n")))
        (unspec:BLK [(reg:DI XMM0_REG)


@@ -18480,11 +18457,10 @@
                     (reg:DI XMM4_REG)
                     (reg:DI XMM5_REG)
                     (reg:DI XMM6_REG)
                     (reg:DI XMM4_REG)
                     (reg:DI XMM5_REG)
                     (reg:DI XMM6_REG)

-                    (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE_LOW))
+                    (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))

    (use (match_operand:DI 1 "register_operand" "r"))
    (use (match_operand:DI 2 "const_int_operand" "i"))
    (use (match_operand:DI 1 "register_operand" "r"))
    (use (match_operand:DI 2 "const_int_operand" "i"))

-   (use (label_ref:DI (match_operand 3 "" "X")))
-   (use (match_operand:DI 5 "const_int_operand" "i"))]
+   (use (label_ref:DI (match_operand 3 "" "X")))]

   "TARGET_64BIT
    && INTVAL (operands[4]) + X86_64_SSE_REGPARM_MAX * 16 - 16 < 128
    && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
   "TARGET_64BIT
    && INTVAL (operands[4]) + X86_64_SSE_REGPARM_MAX * 16 - 16 < 128
    && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"


@@ -18504,10 +18480,7 @@
       PUT_MODE (operands[4], TImode);
       if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
         output_asm_insn ("rex", operands);
       PUT_MODE (operands[4], TImode);
       if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
         output_asm_insn ("rex", operands);

-      if (crtl->stack_alignment_needed < 128)
-        output_asm_insn ("%vmovsd\t{%5, %4|%4, %5}", operands);
-      else
-        output_asm_insn ("%vmovaps\t{%5, %4|%4, %5}", operands);
+      output_asm_insn ("%vmovaps\t{%5, %4|%4, %5}", operands);

     }
   (*targetm.asm_out.internal_label) (asm_out_file, "L",
                                     CODE_LABEL_NUMBER (operands[3]));
     }
   (*targetm.asm_out.internal_label) (asm_out_file, "L",
                                     CODE_LABEL_NUMBER (operands[3]));


@@ -18516,11 +18489,11 @@
   [(set_attr "type" "other")
    (set_attr "length_immediate" "0")
    (set_attr "length_address" "0")
   [(set_attr "type" "other")
    (set_attr "length_immediate" "0")
    (set_attr "length_address" "0")

-   ;; 2 bytes for jump and opernds[4] bytes for each save.

    (set (attr "length")
    (set (attr "length")

-     (plus (const_int 2)
-          (mult (symbol_ref ("INTVAL (operands[5])"))
-                (symbol_ref ("X86_64_SSE_REGPARM_MAX - INTVAL (operands[2])")))))
+     (if_then_else
+       (eq (symbol_ref "TARGET_AVX") (const_int 0))
+       (const_string "34")
+       (const_string "42")))

    (set_attr "memory" "store")
    (set_attr "modrm" "0")
    (set_attr "prefix" "maybe_vex")
    (set_attr "memory" "store")
    (set_attr "modrm" "0")
    (set_attr "prefix" "maybe_vex")