OSDN Git Service

2009-11-04 Richard Earnshaw <rearnsha@arm.com>
authorrearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 4 Nov 2009 14:09:55 +0000 (14:09 +0000)
committerrearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 4 Nov 2009 14:09:55 +0000 (14:09 +0000)
PR target/40835
* arm.md (peephole2 patterns for move and compare): New.

2009-11-04  Wei Guozhi  <carrot@google.com>

PR target/40835
* gcc.target/arm/pr40835: New testcase.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@153895 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/arm/arm.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/arm/pr40835.c [new file with mode: 0644]

index 8afa6d1..1367409 100644 (file)
@@ -1,3 +1,8 @@
+2009-11-04  Richard Earnshaw  <rearnsha@arm.com>
+
+       PR target/40835
+       * arm.md (peephole2 patterns for move and compare): New.
+
 2009-11-04  Nick Clifton  <nickc@redhat.com>
 
        * defaults.h (CONSTANT_ADDRESS_P): Provide a default definition.
index b8bf700..fbc52f4 100644 (file)
                (const_int 6)
                (const_int 8))))]
 )
+
 (define_insn "*movsi_cbranchsi4"
   [(set (pc)
        (if_then_else
           (const_int 10)))))]
 )
 
+(define_peephole2
+  [(set (match_operand:SI 0 "low_register_operand" "")
+       (match_operand:SI 1 "low_register_operand" ""))
+   (set (pc)
+       (if_then_else (match_operator 2 "arm_comparison_operator"
+                      [(match_dup 1) (const_int 0)])
+                     (label_ref (match_operand 3 "" ""))
+                     (pc)))]
+  "TARGET_THUMB1"
+  [(parallel
+    [(set (pc)
+       (if_then_else (match_op_dup 2 [(match_dup 1) (const_int 0)])
+                     (label_ref (match_dup 3))
+                     (pc)))
+     (set (match_dup 0) (match_dup 1))])]
+  ""
+)
+
+;; Sigh!  This variant shouldn't be needed, but combine often fails to
+;; merge cases like this because the op1 is a hard register in
+;; CLASS_LIKELY_SPILLED_P.
+(define_peephole2
+  [(set (match_operand:SI 0 "low_register_operand" "")
+       (match_operand:SI 1 "low_register_operand" ""))
+   (set (pc)
+       (if_then_else (match_operator 2 "arm_comparison_operator"
+                      [(match_dup 0) (const_int 0)])
+                     (label_ref (match_operand 3 "" ""))
+                     (pc)))]
+  "TARGET_THUMB1"
+  [(parallel
+    [(set (pc)
+       (if_then_else (match_op_dup 2 [(match_dup 1) (const_int 0)])
+                     (label_ref (match_dup 3))
+                     (pc)))
+     (set (match_dup 0) (match_dup 1))])]
+  ""
+)
+
 (define_insn "*negated_cbranchsi4"
   [(set (pc)
        (if_then_else
index 5ef448c..62d1625 100644 (file)
@@ -1,3 +1,8 @@
+2009-11-04  Wei Guozhi  <carrot@google.com>
+
+       PR target/40835
+       * gcc.target/arm/pr40835: New testcase.
+
 2009-11-04  Revital Eres  <eres@il.ibm.com>
 
        * gcc.target/powerpc/vsx-vectorize-3.c: Adjust tetcase following
diff --git a/gcc/testsuite/gcc.target/arm/pr40835.c b/gcc/testsuite/gcc.target/arm/pr40835.c
new file mode 100644 (file)
index 0000000..baf9403
--- /dev/null
@@ -0,0 +1,55 @@
+/* { dg-options "-mthumb -Os -march=armv5te" }  */
+/* { dg-final { scan-assembler-not "cmp" } } */
+
+int bar();
+void goo(int, int);
+
+void eq()
+{
+  int v = bar();
+  if (v == 0)
+    return;
+  goo(1, v);
+}
+
+void ge()
+{
+  int v = bar();
+  if (v >= 0)
+    return;
+  goo(1, v);
+}
+
+void gt()
+{
+  int v = bar();
+  if (v > 0)
+    return;
+  goo(1, v);
+}
+
+void lt()
+{
+  int v = bar();
+  if (v < 0)
+    return;
+  goo(1, v);
+}
+
+void le()
+{
+  int v = bar();
+  if (v <= 0)
+    return;
+  goo(1, v);
+}
+
+unsigned int foo();
+
+void leu()
+{
+  unsigned int v = foo();
+  if (v <= 0)
+    return;
+  goo(1, v);
+}