.\" Automatically generated by Pod::Man version 1.15
-.\" Wed Apr 25 21:39:15 2001
+.\" Sun May 20 12:45:49 2001
.\"
.\" Standard preamble:
.\" ======================================================================
.\" ======================================================================
.\"
.IX Title "GCC 1"
-.TH GCC 1 "gcc-3.1" "2001-04-25" "GNU"
+.TH GCC 1 "gcc-3.1" "2001-05-20" "GNU"
.UC
.SH "NAME"
gcc \- \s-1GNU\s0 project C and \*(C+ compiler
\&\-Wno-non-template-friend \-Wold-style-cast
\&\-Woverloaded-virtual \-Wno-pmf-conversions
\&\-Wsign-promo \-Wsynth\fR
+.Ip "\fIObjective-C Language Options\fR" 4
+.IX Item "Objective-C Language Options"
+\&\fB\-fconstant-string-class=\fR\fIclass name\fR
+\&\fB\-fgnu-runtime \-fnext-runtime \-gen-decls
+\&\-Wno-protocol \-Wselector\fR
.Ip "\fILanguage Independent Options\fR" 4
.IX Item "Language Independent Options"
\&\fB\-fmessage-length=\fR\fIn\fR
\&\fB\-mintel-syntax \-mieee-fp \-mno-fancy-math-387
\&\-mno-fp-ret-in-387 \-msoft-float \-msvr3\-shlib
\&\-mno-wide-multiply \-mrtd \-malign-double
-\&\-malign-jumps=\fR\fInum\fR \fB\-malign-loops=\fR\fInum\fR
-\&\fB\-malign-functions=\fR\fInum\fR \fB\-mpreferred-stack-boundary=\fR\fInum\fR
+\&\-mpreferred-stack-boundary=\fR\fInum\fR
\&\fB\-mthreads \-mno-align-stringops \-minline-all-stringops
\&\-mpush-args \-maccumulate-outgoing-args \-m128bit-long-double
-\&\-m96bit-long-double \-mregparm=\fR\fInum\fR
+\&\-m96bit-long-double \-mregparm=\fR\fInum\fR \fB\-momit-leaf-frame-pointer\fR
.Sp
\&\fI\s-1HPPA\s0 Options\fR
.Sp
such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, and
predefined macros such as \f(CW\*(C`unix\*(C'\fR and \f(CW\*(C`vax\*(C'\fR that identify the
type of system you are using. It also enables the undesirable and
-rarely used \s-1ISO\s0 trigraph feature. For the C compiler,
+rarely used \s-1ISO\s0 trigraph feature. For the C compiler,
it disables recognition of \*(C+ style \fB//\fR comments as well as
the \f(CW\*(C`inline\*(C'\fR keyword.
.Sp
.Ip "\fB\-std=\fR" 4
.IX Item "-std="
Determine the language standard. A value for this option must be provided;
-possible values are
+possible values are
.RS 4
.Ip "\fBiso9899:1990\fR" 4
.IX Item "iso9899:1990"
.Sp
This option is no longer useful on most targets, now that support has
been added for putting variables into \s-1BSS\s0 without making them common.
+.Ip "\fB\-fno-const-strings\fR" 4
+.IX Item "-fno-const-strings"
+Give string constants type \f(CW\*(C`char *\*(C'\fR instead of type \f(CW\*(C`const
+char *\*(C'\fR. By default, G++ uses type \f(CW\*(C`const char *\*(C'\fR as required by
+the standard. Even if you use \fB\-fno-const-strings\fR, you cannot
+actually modify the value of a string constant, unless you also use
+\&\fB\-fwritable-strings\fR.
+.Sp
+This option might be removed in a future release of G++. For maximum
+portability, you should structure your code so that it works with
+string constants that have type \f(CW\*(C`const char *\*(C'\fR.
.Ip "\fB\-fdollars-in-identifiers\fR" 4
.IX Item "-fdollars-in-identifiers"
Accept \fB$\fR in identifiers. You can also explicitly prohibit use of
.Ip "\fB\-fno-gnu-keywords\fR" 4
.IX Item "-fno-gnu-keywords"
Do not recognize \f(CW\*(C`typeof\*(C'\fR as a keyword, so that code can use this
-word as an identifier. You can use the keyword \f(CW\*(C`_\|_typeof_\|_\*(C'\fR instead.
+word as an identifier. You can use the keyword \f(CW\*(C`_\|_typeof_\|_\*(C'\fR instead.
\&\fB\-ansi\fR implies \fB\-fno-gnu-keywords\fR.
.Ip "\fB\-fhonor-std\fR" 4
.IX Item "-fhonor-std"
.IX Item "-fms-extensions"
Disable pedantic warnings about constructs used in \s-1MFC\s0, such as implicit
int and getting a pointer to member function via non-standard syntax.
+.Ip "\fB\-fno-nonansi-builtins\fR" 4
+.IX Item "-fno-nonansi-builtins"
+Disable builtin declarations of functions that are not mandated by
+\&\s-1ANSI/ISO\s0 C. These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR,
+\&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions.
.Ip "\fB\-fno-operator-names\fR" 4
.IX Item "-fno-operator-names"
Do not treat the operator name keywords \f(CW\*(C`and\*(C'\fR, \f(CW\*(C`bitand\*(C'\fR,
of the language, you can save some space by using this flag. Note that
exception handling uses the same information, but it will generate it as
needed.
+.Ip "\fB\-fstats\fR" 4
+.IX Item "-fstats"
+Emit statistics about front-end processing at the end of the compilation.
+This information is generally only useful to the G++ development team.
.Ip "\fB\-ftemplate-depth-\fR\fIn\fR" 4
.IX Item "-ftemplate-depth-n"
Set the maximum instantiation depth for template classes to \fIn\fR.
.Sp
Like all options that change the \s-1ABI\s0, all \*(C+ code, \fIincluding
libgcc.a\fR must be built with the same setting of this option.
+.Ip "\fB\-fno-weak\fR" 4
+.IX Item "-fno-weak"
+Do not use weak symbol support, even if it is provied by the linker.
+By default, G++ will use weak symbols if they are available. This
+option exists only for testing, and should not be used by end-users;
+it will result in inferior code and has no benefits. This option may
+be removed in a future release of G++.
.Ip "\fB\-nostdinc++\fR" 4
.IX Item "-nostdinc++"
Do not search for header files in the standard directories specific to
.Ve
In this example, g++ will synthesize a default \fBA& operator =
(const A&);\fR, while cfront will use the user-defined \fBoperator =\fR.
+.Sh "Options Controlling Objective-C Dialect"
+.IX Subsection "Options Controlling Objective-C Dialect"
+This section describes the command-line options that are only meaningful
+for Objective-C programs; but you can also use most of the \s-1GNU\s0 compiler
+options regardless of what language your program is in. For example,
+you might compile a file \f(CW\*(C`some_class.m\*(C'\fR like this:
+.PP
+.Vb 1
+\& gcc -g -fgnu-runtime -O -c some_class.m
+.Ve
+In this example, only \fB\-fgnu-runtime\fR is an option meant only for
+Objective-C programs; you can use the other options with any language
+supported by \s-1GCC\s0.
+.PP
+Here is a list of options that are \fIonly\fR for compiling Objective-C
+programs:
+.Ip "\fB\-fconstant-string-class=\fR\fIclass name\fR" 4
+.IX Item "-fconstant-string-class=class name"
+Use \fIclass name\fR as the name of the class to instantiate for each
+literal string specified with the syntax \f(CW\*(C`@"..."\*(C'\fR. The default
+class name is \f(CW\*(C`NXConstantString\*(C'\fR.
+.Ip "\fB\-fgnu-runtime\fR" 4
+.IX Item "-fgnu-runtime"
+Generate object code compatible with the standard \s-1GNU\s0 Objective-C
+runtime. This is the default for most types of systems.
+.Ip "\fB\-fnext-runtime\fR" 4
+.IX Item "-fnext-runtime"
+Generate output compatible with the NeXT runtime. This is the default
+for NeXT-based systems, including Darwin and Mac \s-1OS\s0 X.
+.Ip "\fB\-gen-decls\fR" 4
+.IX Item "-gen-decls"
+Dump interface declarations for all classes seen in the source file to a
+file named \fI\fIsourcename\fI.decl\fR.
+.Ip "\fB\-Wno-protocol\fR" 4
+.IX Item "-Wno-protocol"
+Do not warn if methods required by a protocol are not implemented
+in the class adopting it.
+.Ip "\fB\-Wselector\fR" 4
+.IX Item "-Wselector"
+Warn if a selector has multiple methods of different types defined.
.Sh "Options to Control Diagnostic Messages Formatting"
.IX Subsection "Options to Control Diagnostic Messages Formatting"
Traditionally, diagnostic messages have been formatted irrespective of
algorithm, e.g. how many characters per line, how often source location
information should be reported. Right now, only the \*(C+ front-end can
honor these options. However it is expected, in the near future, that
-the remaining front-ends would be able to digest them correctly.
+the remaining front-ends would be able to digest them correctly.
.Ip "\fB\-fmessage-length=\fR\fIn\fR" 4
.IX Item "-fmessage-length=n"
Try to format error messages so that they fit on lines of about \fIn\fR
characters. The default is 72 characters for g++ and 0 for the rest of
the front-ends supported by \s-1GCC\s0. If \fIn\fR is zero, then no
-line-wrapping will be done; each error message will appear on a single
+line-wrapping will be done; each error message will appear on a single
line.
.Ip "\fB\-fdiagnostics-show-location=once\fR" 4
.IX Item "-fdiagnostics-show-location=once"
case the message is too long to fit on a single physical line and has to
be wrapped, the source location won't be emitted (as prefix) again,
over and over, in subsequent continuation lines. This is the default
-behaviour.
+behaviour.
.Ip "\fB\-fdiagnostics-show-location=every-line\fR" 4
.IX Item "-fdiagnostics-show-location=every-line"
Only meaningful in line-wrapping mode. Instructs the diagnostic
some instances, but would require considerable additional work and would
be quite different from \fB\-pedantic\fR. We don't have plans to
support such a feature in the near future.
+.Sp
+Where the standard specified with \fB\-std\fR represents a \s-1GNU\s0
+extended dialect of C, such as \fBgnu89\fR or \fBgnu99\fR, there is a
+corresponding \fIbase standard\fR, the version of \s-1ISO\s0 C on which the \s-1GNU\s0
+extended dialect is based. Warnings from \fB\-pedantic\fR are given
+where they are required by the base standard. (It would not make sense
+for such warnings to be given only for features not in the specified \s-1GNU\s0
+C dialect, since by definition the \s-1GNU\s0 dialects of C include all
+features the compiler supports with the given option, and there would be
+nothing to warn about.)
.Ip "\fB\-pedantic-errors\fR" 4
.IX Item "-pedantic-errors"
Like \fB\-pedantic\fR, except that errors are produced rather than
.IX Item "-Wreturn-type"
Warn whenever a function is defined with a return-type that defaults to
\&\f(CW\*(C`int\*(C'\fR. Also warn about any \f(CW\*(C`return\*(C'\fR statement with no
-return-value in a function whose return-type is not \f(CW\*(C`void\*(C'\fR.
+return-value in a function whose return-type is not \f(CW\*(C`void\*(C'\fR.
.Sp
For \*(C+, a function without return type always produces a diagnostic
message, even when \fB\-Wno-return-type\fR is specified. The only
.Ip "\fB\-Wpacked\fR" 4
.IX Item "-Wpacked"
Warn if a structure is given the packed attribute, but the packed
-attribute has no effect on the layout or size of the structure.
+attribute has no effect on the layout or size of the structure.
Such structures may be mis-aligned for little benefit. For
instance, in this code, the variable \f(CW\*(C`f.x\*(C'\fR in \f(CW\*(C`struct bar\*(C'\fR
will be misaligned even though \f(CW\*(C`struct bar\*(C'\fR does not itself
so care should be taken when removing apparently-unreachable code.
.Sp
For instance, when a function is inlined, a warning may mean that the
-line is unreachable in only one inlined copy of the function.
+line is unreachable in only one inlined copy of the function.
.Sp
This option is not made part of \fB\-Wall\fR because in a debugging
version of a program there is often substantial code which checks
Says to make debugging dumps during compilation at times specified by
\&\fIletters\fR. This is used for debugging the compiler. The file names
for most of the dumps are made by appending a pass number and a word to
-the source file name (e.g. \fIfoo.c.00.rtl\fR or \fIfoo.c.01.sibling\fR).
+the source file name (e.g. \fIfoo.c.00.rtl\fR or \fIfoo.c.01.sibling\fR).
Here are the possible letters for use in \fIletters\fR, and their meanings:
.RS 4
.Ip "\fBA\fR" 4
.Ip "\fBM\fR" 4
.IX Item "M"
Dump after performing the machine dependent reorganisation pass, to
-\&\fI\fIfile\fI.28.mach\fR.
+\&\fI\fIfile\fI.28.mach\fR.
.Ip "\fBn\fR" 4
.IX Item "n"
Dump after register renumbering, to \fI\fIfile\fI.23.rnreg\fR.
.Ip "\fBs\fR" 4
.IX Item "s"
Dump after \s-1CSE\s0 (including the jump optimization that sometimes follows
-\&\s-1CSE\s0), to \fI\fIfile\fI.03.cse\fR.
+\&\s-1CSE\s0), to \fI\fIfile\fI.03.cse\fR.
.Ip "\fBS\fR" 4
.IX Item "S"
Dump after the first instruction scheduling pass, to
.IX Item "-finline-limit=n"
By default, gcc limits the size of functions that can be inlined. This flag
allows the control of this limit for functions that are explicitly marked as
-inline (ie marked with the inline keyword or defined within the class
-definition in c++). \fIn\fR is the size of functions that can be inlined in
+inline (ie marked with the inline keyword or defined within the class
+definition in c++). \fIn\fR is the size of functions that can be inlined in
number of pseudo instructions (not counting parameter handling). The default
value of n is 10000. Increasing this value can result in more inlined code at
the cost of compilation time and memory consumption. Decreasing usually makes
-the compilation faster and less code will be inlined (which presumably
-means slower programs). This option is particularly useful for programs that
+the compilation faster and less code will be inlined (which presumably
+means slower programs). This option is particularly useful for programs that
use inlining heavily such as those based on recursive templates with c++.
.Sp
\&\fINote:\fR pseudo instruction represents, in this particular context, an
.IX Item "-funsafe-math-optimizations"
Allow optimizations for floating-point arithmetic that (a) assume
that arguments and results are valid and (b) may violate \s-1IEEE\s0 or
-\&\s-1ANSI\s0 standards.
+\&\s-1ANSI\s0 standards.
.Sp
This option should never be turned on by any \fB\-O\fR option since
it can result in incorrect output for programs which depend on
When \-fgcse-lm is enabled, global common subexpression elimination will
attempt to move loads which are only killed by stores into themselves. This
allows a loop containing a load/store sequence to be changed to a load outside
-the loop, and a copy/store within the loop.
+the loop, and a copy/store within the loop.
.Ip "\fB\-fgcse-sm\fR" 4
.IX Item "-fgcse-sm"
-When \-fgcse-sm is enabled, A store motion pass is run after global common
+When \-fgcse-sm is enabled, A store motion pass is run after global common
subexpression elimination. This pass will attempt to move stores out of loops.
When used in conjunction with \-fgcse-lm, loops containing a load/store sequence
can be changed to a load before the loop and a store after the loop.
object of a different type, unless the types are almost the same. For
example, an \f(CW\*(C`unsigned int\*(C'\fR can alias an \f(CW\*(C`int\*(C'\fR, but not a
\&\f(CW\*(C`void*\*(C'\fR or a \f(CW\*(C`double\*(C'\fR. A character type may alias any other
-type.
+type.
.Sp
Pay special attention to code like this:
.Sp
.Vb 4
-\& union a_union {
+\& union a_union {
\& int i;
\& double d;
\& };
expected. However, this code might not:
.Sp
.Vb 7
-\& int f() {
+\& int f() {
\& a_union t;
\& int* ip;
\& t.d = 3.0;
optimization that is done. For example, \s-1GCC\s0 will not inline functions
that contain more that a certain number of instructions. You can
control some of these constants on the command-line using the
-\&\fB\*(--param\fR option.
+\&\fB\*(--param\fR option.
.Sp
In each case, the \fIvalue\fR is a integer. The allowable choices for
\&\fIname\fR are given in the following table:
.RS 4
-.Ip "\fBmax-inline-insns\fR" 4
-.IX Item "max-inline-insns"
-If an function contains more than this many instructions, it
-will not be inlined. This option is precisely equivalent to
-\&\fB\-finline-limit\fR.
+.Ip "\fBmax-delay-slot-insn-search\fR" 4
+.IX Item "max-delay-slot-insn-search"
+The maximum number of instructions to consider when looking for an
+instruction to fill a delay slot. If more than this arbitrary number of
+instructions is searched, the time savings from filling the delay slot
+will be minimal so stop searching. Increasing values mean more
+aggressive optimization, making the compile time increase with probably
+small improvement in executable run time.
+.Ip "\fBmax-delay-slot-live-search\fR" 4
+.IX Item "max-delay-slot-live-search"
+When trying to fill delay slots, the maximum number of instructions to
+consider when searching for a block with valid live register
+information. Increasing this arbitrarily chosen value means more
+aggressive optimization, increasing the compile time. This parameter
+should be removed when the delay slot code is rewritten to maintain the
+control-flow graph.
.Ip "\fBmax-gcse-memory\fR" 4
.IX Item "max-gcse-memory"
The approximate maximum amount of memory that will be allocated in
order to perform the global common subexpression elimination
optimization. If more memory than specified is required, the
optimization will not be done.
+.Ip "\fBmax-inline-insns\fR" 4
+.IX Item "max-inline-insns"
+If an function contains more than this many instructions, it
+will not be inlined. This option is precisely equivalent to
+\&\fB\-finline-limit\fR.
.RE
.RS 4
.RE
object file names should not be used as arguments.
.Ip "\fB\-l\fR\fIlibrary\fR" 4
.IX Item "-llibrary"
-Search the library named \fIlibrary\fR when linking.
+.PD 0
+.Ip "\fB\-l\fR \fIlibrary\fR" 4
+.IX Item "-l library"
+.PD
+Search the library named \fIlibrary\fR when linking. (The second
+alternative with the library as a separate argument is only for
+\&\s-1POSIX\s0 compliance and is not recommended.)
.Sp
It makes a difference where in the command you write this option; the
-linker searches processes libraries and object files in the order they
+linker searches and processes libraries and object files in the order they
are specified. Thus, \fBfoo.o \-lz bar.o\fR searches library \fBz\fR
after file \fIfoo.o\fR but before \fIbar.o\fR. If \fIbar.o\fR refers
to functions in \fBz\fR, those functions may not be loaded.
.IX Item "-shared"
Produce a shared object which can then be linked with other objects to
form an executable. Not all systems support this option. For predictable
-results, you must also specify the same set of options that were used to
+results, you must also specify the same set of options that were used to
generate code (\fB\-fpic\fR, \fB\-fPIC\fR, or model suboptions)
when you specify this option.[1]
.Ip "\fB\-shared-libgcc\fR" 4
Generate output for a 520X \*(L"coldfire\*(R" family cpu. This is the default
when the compiler is configured for 520X-based systems.
.Sp
-Use this option for microcontroller with a 5200 core, including
+Use this option for microcontroller with a 5200 core, including
the \s-1MCF5202\s0, \s-1MCF5203\s0, \s-1MCF5204\s0 and \s-1MCF5202\s0.
.Ip "\fB\-m68020\-40\fR" 4
.IX Item "-m68020-40"
.Ip "\fB\-mno-align-int\fR" 4
.IX Item "-mno-align-int"
.PD
-Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR,
+Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR,
\&\f(CW\*(C`float\*(C'\fR, \f(CW\*(C`double\*(C'\fR, and \f(CW\*(C`long double\*(C'\fR variables on a 32\-bit
boundary (\fB\-malign-int\fR) or a 16\-bit boundary (\fB\-mno-align-int\fR).
Aligning variables on 32\-bit boundaries produces code that runs somewhat
.IX Subsection "M68hc1x Options"
.PP
These are the \fB\-m\fR options defined for the 68hc11 and 68hc12
-microcontrollers. The default values for these options depends on
+microcontrollers. The default values for these options depends on
which style of microcontroller was selected when the compiler was configured;
the defaults for the most common choices are given below.
.Ip "\fB\-m6811\fR" 4
handlers.
.PP
These \fB\-m\fR switches are supported in addition to the above
-on \s-1SPARC\s0 V9 processors in 64 bit environments.
+on \s-1SPARC\s0 V9 processors in 64\-bit environments.
.Ip "\fB\-mlittle-endian\fR" 4
.IX Item "-mlittle-endian"
Generate code for a processor running in little-endian mode.
.Ip "\fB\-m64\fR" 4
.IX Item "-m64"
.PD
-Generate code for a 32 bit or 64 bit environment.
-The 32 bit environment sets int, long and pointer to 32 bits.
-The 64 bit environment sets int to 32 bits and long and pointer
+Generate code for a 32\-bit or 64\-bit environment.
+The 32\-bit environment sets int, long and pointer to 32 bits.
+The 64\-bit environment sets int to 32 bits and long and pointer
to 64 bits.
.Ip "\fB\-mcmodel=medlow\fR" 4
.IX Item "-mcmodel=medlow"
.Ip "\fB\-mcmodel=embmedany\fR" 4
.IX Item "-mcmodel=embmedany"
Generate code for the Medium/Anywhere code model for embedded systems:
-assume a 32 bit text and a 32 bit data segment, both starting anywhere
+assume a 32\-bit text and a 32\-bit data segment, both starting anywhere
(determined at link time). Register \f(CW%g4\fR points to the base of the
-data segment. Pointers still 64 bits.
+data segment. Pointers are still 64 bits.
Programs are statically linked, \s-1PIC\s0 is not supported.
.Ip "\fB\-mstack-bias\fR" 4
.IX Item "-mstack-bias"
.Sp
This option is ignored when compiling for \s-1ARM\s0 architecture 4 or later,
since these processors have instructions to directly access half-word
-objects in memory.
+objects in memory.
.Ip "\fB\-mno-alignment-traps\fR" 4
.IX Item "-mno-alignment-traps"
Generate code that assumes that the \s-1MMU\s0 will not trap unaligned
accesses. This produces better code when the target instruction set
does not have half-word memory operations (implementations prior to
-ARMv4).
+ARMv4).
.Sp
Note that you cannot use this option to access unaligned word objects,
since the processor will only fetch one 32\-bit aligned object from
-memory.
+memory.
.Sp
The default setting for most targets is \-mno-alignment-traps, since
this produces better code when there are no half-word memory
-instructions available.
+instructions available.
.Ip "\fB\-mshort-load-bytes\fR" 4
.IX Item "-mshort-load-bytes"
This is a deprecated alias for \fB\-malignment-traps\fR.
address of the function into a register and then performing a subroutine
call on this register. This switch is needed if the target function
will lie outside of the 64 megabyte addressing range of the offset based
-version of subroutine call instruction.
+version of subroutine call instruction.
.Sp
Even if this switch is enabled, not all function calls will be turned
into long calls. The heuristic is that static functions, functions
placing the function calls within the scope of a \fB#pragma
long_calls_off\fR directive. Note these switches have no effect on how
the compiler generates code to handle function calls via function
-pointers.
+pointers.
.Ip "\fB\-mnop-fun-dllimport\fR" 4
.IX Item "-mnop-fun-dllimport"
Disable the support for the \fIdllimport\fR attribute.
.IX Item "-mtpcs-frame"
Generate a stack frame that is compliant with the Thumb Procedure Call
Standard for all non-leaf functions. (A leaf function is one that does
-not call any other functions). The default is \fB\-mno-apcs-frame\fR.
+not call any other functions). The default is \fB\-mno-apcs-frame\fR.
.Ip "\fB\-mtpcs-leaf-frame\fR" 4
.IX Item "-mtpcs-leaf-frame"
Generate a stack frame that is compliant with the Thumb Procedure Call
Standard for all leaf functions. (A leaf function is one that does
-not call any other functions). The default is \fB\-mno-apcs-leaf-frame\fR.
+not call any other functions). The default is \fB\-mno-apcs-leaf-frame\fR.
.Ip "\fB\-mlittle-endian\fR" 4
.IX Item "-mlittle-endian"
Generate code for a processor running in little-endian mode. This is
to shorten branches, calls and absolute memory addresses. This option only
has an effect when used on the command line for the final link step.
.Sp
-This option makes symbolic debugging impossible.
+This option makes symbolic debugging impossible.
.PP
.I "\s-1MN10300\s0 Options"
.IX Subsection "MN10300 Options"
to shorten branches, calls and absolute memory addresses. This option only
has an effect when used on the command line for the final link step.
.Sp
-This option makes symbolic debugging impossible.
+This option makes symbolic debugging impossible.
.PP
.I "M32R/D Options"
.IX Subsection "M32R/D Options"
\&\f(CW\*(C`model\*(C'\fR attribute.
.Ip "\fB\-mcode-model=medium\fR" 4
.IX Item "-mcode-model=medium"
-Assume objects may be anywhere in the 32 bit address space (the compiler
+Assume objects may be anywhere in the 32\-bit address space (the compiler
will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and
assume all subroutines are reachable with the \f(CW\*(C`bl\*(C'\fR instruction.
.Ip "\fB\-mcode-model=large\fR" 4
.IX Item "-mcode-model=large"
-Assume objects may be anywhere in the 32 bit address space (the compiler
+Assume objects may be anywhere in the 32\-bit address space (the compiler
will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and
assume subroutines may not be reachable with the \f(CW\*(C`bl\*(C'\fR instruction
(the compiler will generate the much slower \f(CW\*(C`seth/add3/jl\*(C'\fR
and 64\-bit PowerPC architecture machine types, with an appropriate,
generic processor model assumed for scheduling purposes.
.Sp
-Specifying any of the following options:
+Specifying any of the following options:
\&\fB\-mcpu=rios1\fR, \fB\-mcpu=rios2\fR, \fB\-mcpu=rsc\fR,
-\&\fB\-mcpu=power\fR, or \fB\-mcpu=power2\fR
-enables the \fB\-mpower\fR option and disables the \fB\-mpowerpc\fR option;
+\&\fB\-mcpu=power\fR, or \fB\-mcpu=power2\fR
+enables the \fB\-mpower\fR option and disables the \fB\-mpowerpc\fR option;
\&\fB\-mcpu=601\fR enables both the \fB\-mpower\fR and \fB\-mpowerpc\fR options.
All of \fB\-mcpu=rs64a\fR, \fB\-mcpu=602\fR, \fB\-mcpu=603\fR,
\&\fB\-mcpu=603e\fR, \fB\-mcpu=604\fR, \fB\-mcpu=620\fR, \fB\-mcpu=630\fR,
\&\fB\-mcpu=740\fR, and \fB\-mcpu=750\fR
-enable the \fB\-mpowerpc\fR option and disable the \fB\-mpower\fR option.
+enable the \fB\-mpowerpc\fR option and disable the \fB\-mpower\fR option.
Exactly similarly, all of \fB\-mcpu=403\fR,
-\&\fB\-mcpu=505\fR, \fB\-mcpu=821\fR, \fB\-mcpu=860\fR and \fB\-mcpu=powerpc\fR
+\&\fB\-mcpu=505\fR, \fB\-mcpu=821\fR, \fB\-mcpu=860\fR and \fB\-mcpu=powerpc\fR
enable the \fB\-mpowerpc\fR option and disable the \fB\-mpower\fR option.
-\&\fB\-mcpu=common\fR disables both the
+\&\fB\-mcpu=common\fR disables both the
\&\fB\-mpower\fR and \fB\-mpowerpc\fR options.
.Sp
\&\s-1AIX\s0 versions 4 or greater selects \fB\-mcpu=common\fR by default, so
\&\s-1ISA\s0 level.
.Ip "\fB\-mips3\fR" 4
.IX Item "-mips3"
-Issue instructions from level 3 of the \s-1MIPS\s0 \s-1ISA\s0 (64 bit instructions).
+Issue instructions from level 3 of the \s-1MIPS\s0 \s-1ISA\s0 (64\-bit instructions).
\&\fBr4000\fR is the default \fIcpu type\fR at this \s-1ISA\s0 level.
.Ip "\fB\-mips4\fR" 4
.IX Item "-mips4"
.Ip "\fB\-march=\fR\fIcpu type\fR" 4
.IX Item "-march=cpu type"
Generate instructions for the machine type \fIcpu type\fR. The choices
-for \fIcpu type\fR are the same as for \fB\-mcpu\fR. Moreover,
+for \fIcpu type\fR are the same as for \fB\-mcpu\fR. Moreover,
specifying \fB\-march=\fR\fIcpu type\fR implies \fB\-mcpu=\fR\fIcpu type\fR.
.Ip "\fB\-m386\fR" 4
.IX Item "-m386"
\&\fBWarning:\fR if you use the \fB\-m128bit-long-double\fR switch, the
structures and arrays containing \f(CW\*(C`long double\*(C'\fR will change their size as
well as function calling convention for function taking \f(CW\*(C`long double\*(C'\fR
-will be modified.
+will be modified.
.Ip "\fB\-m96bit-long-double\fR" 4
.IX Item "-m96bit-long-double"
.PD 0
.IX Item "-mwide-multiply"
.PD
Control whether \s-1GCC\s0 uses the \f(CW\*(C`mul\*(C'\fR and \f(CW\*(C`imul\*(C'\fR that produce
-64 bit results in \f(CW\*(C`eax:edx\*(C'\fR from 32 bit operands to do \f(CW\*(C`long
+64\-bit results in \f(CW\*(C`eax:edx\*(C'\fR from 32\-bit operands to do \f(CW\*(C`long
long\*(C'\fR multiplies and 32\-bit division by constants.
.Ip "\fB\-mrtd\fR" 4
.IX Item "-mrtd"
\&\fInum\fR is nonzero, then you must build all modules with the same
value, including any libraries. This includes the system libraries and
startup modules.
-.Ip "\fB\-malign-loops=\fR\fInum\fR" 4
-.IX Item "-malign-loops=num"
-Align loops to a 2 raised to a \fInum\fR byte boundary. If
-\&\fB\-malign-loops\fR is not specified, the default is 2 unless
-gas 2.8 (or later) is being used in which case the default is
-to align the loop on a 16 byte boundary if it is less than 8
-bytes away.
-.Ip "\fB\-malign-jumps=\fR\fInum\fR" 4
-.IX Item "-malign-jumps=num"
-Align instructions that are only jumped to to a 2 raised to a \fInum\fR
-byte boundary. If \fB\-malign-jumps\fR is not specified, the default is
-2 if optimizing for a 386, and 4 if optimizing for a 486 unless
-gas 2.8 (or later) is being used in which case the default is
-to align the instruction on a 16 byte boundary if it is less
-than 8 bytes away.
-.Ip "\fB\-malign-functions=\fR\fInum\fR" 4
-.IX Item "-malign-functions=num"
-Align the start of functions to a 2 raised to \fInum\fR byte boundary.
-If \fB\-malign-functions\fR is not specified, the default is 2 if optimizing
-for a 386, and 4 if optimizing for a 486.
.Ip "\fB\-mpreferred-stack-boundary=\fR\fInum\fR" 4
.IX Item "-mpreferred-stack-boundary=num"
Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR
penalties if it is not 16 byte aligned.
.Sp
To ensure proper alignment of this values on the stack, the stack boundary
-must be as aligned as that required by any value stored on the stack.
+must be as aligned as that required by any value stored on the stack.
Further, every function must be generated such that it keeps the stack
aligned. Thus calling a function compiled with a higher preferred
stack boundary from a function compiled with a lower preferred stack
increase in code size. This switch implies \-mno-push-args.
.Ip "\fB\-mthreads\fR" 4
.IX Item "-mthreads"
-Support thread-safe exception handling on \fBMingw32\fR. Code that relies
-on thread-safe exception handling must compile and link all code with the
-\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines
-\&\fB\-D_MT\fR; when linking, it links in a special thread helper library
+Support thread-safe exception handling on \fBMingw32\fR. Code that relies
+on thread-safe exception handling must compile and link all code with the
+\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines
+\&\fB\-D_MT\fR; when linking, it links in a special thread helper library
\&\fB\-lmingwthrd\fR which cleans up per thread exception handling data.
.Ip "\fB\-mno-align-stringops\fR" 4
.IX Item "-mno-align-stringops"
aligned at least to 4 byte boundary. This enables more inlining, increase code
size, but may improve performance of code that depends on fast memcpy, strlen
and memset for short lengths.
+.Ip "\fB\-momit-leaf-frame-pointer\fR" 4
+.IX Item "-momit-leaf-frame-pointer"
+Don't keep the frame pointer in a register for leaf functions. This
+avoids the instructions to save, set up and restore frame pointers and
+makes an extra register available in leaf functions. The option
+\&\fB\-fomit-frame-pointer\fR removes the frame pointer for all functions
+which might make debugging harder.
.PP
.I "\s-1HPPA\s0 Options"
.IX Subsection "HPPA Options"
.Sp
\&\s-1PA\s0 2.0 support currently requires gas snapshot 19990413 or later. The
next release of binutils (current is 2.9.1) will probably contain \s-1PA\s0 2.0
-support.
+support.
.Ip "\fB\-mpa-risc-1\-0\fR" 4
.IX Item "-mpa-risc-1-0"
.PD 0
.Ip "\fB\-mschedule=\fR\fIcpu type\fR" 4
.IX Item "-mschedule=cpu type"
Schedule code according to the constraints for the machine type
-\&\fIcpu type\fR. The choices for \fIcpu type\fR are \fB700\fR
-\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, and \fB8000\fR. Refer to
+\&\fIcpu type\fR. The choices for \fIcpu type\fR are \fB700\fR
+\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, and \fB8000\fR. Refer to
\&\fI/usr/lib/sched.models\fR on an \s-1HP-UX\s0 system to determine the
proper scheduling option for your machine.
.Ip "\fB\-mlinker-opt\fR" 4
.PD
Use (do not use) the hardware floating-point instructions for
floating-point operations. When \fB\-msoft-float\fR is specified,
-functions in \fIlibgcc1.c\fR will be used to perform floating-point
+functions in \fIlibgcc.a\fR will be used to perform floating-point
operations. Unless they are replaced by routines that emulate the
floating-point operations, or compiled in such a way as to call such
emulations routines, these routines will issue floating-point
code to implement fully-compliant \s-1IEEE\s0 math. The option is a shorthand
for \fB\-D_IEEE_FP \-D_IEEE_FP_INEXACT\fR plus the three following:
\&\fB\-mieee-conformant\fR,
-\&\fB\-mfp-trap-mode=sui\fR,
-and \fB\-mtrap-precision=i\fR.
+\&\fB\-mfp-trap-mode=sui\fR,
+and \fB\-mtrap-precision=i\fR.
On some Alpha implementations the resulting code may execute
significantly slower than the code generated by default. Since there
is very little code that depends on the \fIinexact flag\fR, you should
Compile code for the processor in little endian mode.
.Ip "\fB\-mdalign\fR" 4
.IX Item "-mdalign"
-Align doubles at 64 bit boundaries. Note that this changes the calling
+Align doubles at 64\-bit boundaries. Note that this changes the calling
conventions, and thus some functions from the standard C library will
not work unless you recompile it first with \-mdalign.
.Ip "\fB\-mrelax\fR" 4
.IX Item "-mno-bk"
.PD
Allow (disallow) allocation of general integer operands into the block
-count register \s-1BK\s0.
+count register \s-1BK\s0.
.Ip "\fB\-mdb\fR" 4
.IX Item "-mdb"
.PD 0
.IX Subsection "MCore Options"
.PP
These are the \fB\-m\fR options defined for the Motorola M*Core
-processors.
+processors.
.Ip "\fB\-mhardlit\fR" 4
.IX Item "-mhardlit"
.PD 0
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