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Fix operands order in BMI2 patterns.
authorhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 20 Oct 2011 20:37:32 +0000 (20:37 +0000)
committerhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 20 Oct 2011 20:37:32 +0000 (20:37 +0000)
gcc/

2011-10-20  Kirill Yukhin  <kirill.yukhin@intel.com>

PR target/50766
* config/i386/i386.md (bmi_bextr_<mode>): Update register/
memory operand order.
(bmi2_bzhi_<mode>3): Ditto.
(bmi2_pdep_<mode>3): Ditto.
(bmi2_pext_<mode>3): Ditto.

gcc/testsuite/

2011-10-20  Kirill Yukhin  <kirill.yukhin@intel.com>

PR target/50766
* gcc.target/i386/pr50766.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180271 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/i386/i386.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/i386/pr50766.c [new file with mode: 0644]

index f48e2ad..30a25f9 100644 (file)
@@ -1,3 +1,12 @@
+2011-10-20  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+       PR target/50766
+       * config/i386/i386.md (bmi_bextr_<mode>): Update register/
+       memory operand order.
+       (bmi2_bzhi_<mode>3): Ditto.
+       (bmi2_pdep_<mode>3): Ditto.
+       (bmi2_pext_<mode>3): Ditto.
+
 2011-10-20  Richard Henderson  <rth@redhat.com>
 
        * target.def (vec_perm_const_ok): Rename from builtin_vec_perm_ok.
index 9c9508d..866fb05 100644 (file)
 
 (define_insn "bmi_bextr_<mode>"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
-        (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
-                       (match_operand:SWI48 2 "register_operand" "r")]
+        (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+                       (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
                        UNSPEC_BEXTR))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_BMI"
 ;; BMI2 instructions.
 (define_insn "bmi2_bzhi_<mode>3"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
-       (and:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+       (and:SWI48 (match_operand:SWI48 1 "register_operand" "r")
                   (lshiftrt:SWI48 (const_int -1)
-                                  (match_operand:SWI48 2 "register_operand" "r"))))
+                                  (match_operand:SWI48 2 "nonimmediate_operand" "rm"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_BMI2"
   "bzhi\t{%2, %1, %0|%0, %1, %2}"
 
 (define_insn "bmi2_pdep_<mode>3"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
-        (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
-                       (match_operand:SWI48 2 "register_operand" "r")]
+        (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+                       (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
                        UNSPEC_PDEP))]
   "TARGET_BMI2"
   "pdep\t{%2, %1, %0|%0, %1, %2}"
 
 (define_insn "bmi2_pext_<mode>3"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
-        (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
-                       (match_operand:SWI48 2 "register_operand" "r")]
+        (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+                       (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
                        UNSPEC_PEXT))]
   "TARGET_BMI2"
   "pext\t{%2, %1, %0|%0, %1, %2}"
index 00e95e0..f373799 100644 (file)
@@ -1,3 +1,8 @@
+2011-10-20  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+       PR target/50766
+       * gcc.target/i386/pr50766.c: New test.
+
 2011-10-20  Jason Merrill  <jason@redhat.com>
 
        PR c++/41449
diff --git a/gcc/testsuite/gcc.target/i386/pr50766.c b/gcc/testsuite/gcc.target/i386/pr50766.c
new file mode 100644 (file)
index 0000000..9923de4
--- /dev/null
@@ -0,0 +1,17 @@
+/* PR target/50766 */
+/* { dg-do assemble } */
+/* { dg-options "-mbmi2" } */
+/* { dg-require-effective-target bmi2 } */
+
+#include <x86intrin.h>
+
+unsigned z;
+
+void
+foo ()
+{
+  unsigned x = 0x23593464;
+  unsigned y = 0xF9494302;
+  z = _pext_u32(x, y);
+}
+