* arm.md (casesi): Fix test for Thumb1.

	(thumb1_casesi_internal_pic): Likewise.
	(thumb1_casesi_dispatch): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@149005 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c8bb8d2..66a48c1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2009-06-27  Richard Earnshaw  <rearnsha@arm.com>
+
+       * arm.md (casesi): Fix test for Thumb1.
+       (thumb1_casesi_internal_pic): Likewise.
+       (thumb1_casesi_dispatch): Likewise.
+
 2009-06-26  Daniel Gutson  <dgutson@codesourcery.com>
 
        * config/arm/arm-cores.def: Added core cortex-m0.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 4f8b5fa..d3609ac 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8908,7 +8908,7 @@
 
     if (TARGET_ARM)
       code = CODE_FOR_arm_casesi_internal;
-    else if (TARGET_THUMB)
+    else if (TARGET_THUMB1)
       code = CODE_FOR_thumb1_casesi_internal_pic;
     else if (flag_pic)
       code = CODE_FOR_thumb2_casesi_internal_pic;
@@ -8951,7 +8951,7 @@
    (match_operand:SI 1 "thumb1_cmp_operand" "")
    (match_operand 2 "" "")
    (match_operand 3 "" "")]
-  "TARGET_THUMB"
+  "TARGET_THUMB1"
   {
     rtx reg0;
     rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[1]);
@@ -8972,7 +8972,7 @@
                         UNSPEC_THUMB1_CASESI))
              (clobber (reg:SI IP_REGNUM))
               (clobber (reg:SI LR_REGNUM))])]
-  "TARGET_THUMB"
+  "TARGET_THUMB1"
   "* return thumb1_output_casesi(operands);"
   [(set_attr "length" "4")]
 )