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* config/i386/i386.md (mov<mode>cc): Macroize expander from movsfcc,
authoruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 21 Feb 2008 10:51:19 +0000 (10:51 +0000)
committeruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 21 Feb 2008 10:51:19 +0000 (10:51 +0000)
movdfcc and movxfcc using X87MODEF mode iterator and SSE_FLOAT_MODE_P
as insn constraint.
* config/i386/sse.md (<sse>_movup<ssemodesuffixf2c>): Macroize insn
from sse_movups adn sse2_movupd using SSEMODEF2P mode iterator and
SSE_VEC_FLOAT_MODE_P as insn constraint.
(<sse>_movmskp<ssemodesuffixf2c>): Ditto from similar patterns.
(sse4a_movnt<mode>): Macroize insn from sse4a_movntsf and
sse4a_movntdf using MODEF mode iterator.
(sse4a_vmmovnt<mode>): Macroize insn form sse4a_vmmovntv2df and
sse4a_vmmovntv4sf using SSEMODEF2P mode iterator.
(sse4_1_blendp<ssemodesuffixf2c>): Ditto from similar patterns.
(sse4_1_blendvp<ssemodesuffixf2c>): Ditto.
(sse4_1_dpp<ssemodesuffixf2c>): Ditto.
(sse4_1_roundp<ssemodesuffixf2c>): Ditto.
(sse4_1_rounds<ssemodesuffixf2c>): Ditto.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@132518 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/i386/i386.md
gcc/config/i386/sse.md

index 29576a6..b7ab324 100644 (file)
@@ -1,3 +1,22 @@
+2008-02-21  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (mov<mode>cc): Macroize expander from movsfcc,
+       movdfcc and movxfcc using X87MODEF mode iterator and SSE_FLOAT_MODE_P
+       as insn constraint.
+       * config/i386/sse.md (<sse>_movup<ssemodesuffixf2c>): Macroize insn
+       from sse_movups adn sse2_movupd using SSEMODEF2P mode iterator and
+       SSE_VEC_FLOAT_MODE_P as insn constraint.
+       (<sse>_movmskp<ssemodesuffixf2c>): Ditto from similar patterns.
+       (sse4a_movnt<mode>): Macroize insn from sse4a_movntsf and
+       sse4a_movntdf using MODEF mode iterator.
+       (sse4a_vmmovnt<mode>): Macroize insn form sse4a_vmmovntv2df and
+       sse4a_vmmovntv4sf using SSEMODEF2P mode iterator.
+       (sse4_1_blendp<ssemodesuffixf2c>): Ditto from similar patterns.
+       (sse4_1_blendvp<ssemodesuffixf2c>): Ditto.
+       (sse4_1_dpp<ssemodesuffixf2c>): Ditto.
+       (sse4_1_roundp<ssemodesuffixf2c>): Ditto.
+       (sse4_1_rounds<ssemodesuffixf2c>): Ditto.
+
 2008-02-21  Richard Guenther  <rguenther@suse.de>
 
        * tree.def (PAREN_EXPR): New tree code.
index 84911ff..92a3728 100644 (file)
                         (match_operand:DI 2 "general_operand" "")
                         (match_operand:DI 3 "general_operand" "")))]
   "TARGET_64BIT"
-  "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
 
 (define_insn "x86_movdicc_0_m1_rex64"
   [(set (match_operand:DI 0 "register_operand" "=r")
                         (match_operand:SI 2 "general_operand" "")
                         (match_operand:SI 3 "general_operand" "")))]
   ""
-  "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
 
 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
 ;; the register first winds up with `sbbl $0,reg', which is also weird.
                         (match_operand:HI 2 "general_operand" "")
                         (match_operand:HI 3 "general_operand" "")))]
   "TARGET_HIMODE_MATH"
-  "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
 
 (define_insn "*movhicc_noc"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
                         (match_operand:QI 2 "general_operand" "")
                         (match_operand:QI 3 "general_operand" "")))]
   "TARGET_QIMODE_MATH"
-  "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
 
 (define_insn_and_split "*movqicc_noc"
   [(set (match_operand:QI 0 "register_operand" "=r,r")
   [(set_attr "type" "icmov")
    (set_attr "mode" "SI")])
 
-(define_expand "movsfcc"
-  [(set (match_operand:SF 0 "register_operand" "")
-       (if_then_else:SF (match_operand 1 "comparison_operator" "")
-                        (match_operand:SF 2 "register_operand" "")
-                        (match_operand:SF 3 "register_operand" "")))]
-  "(TARGET_80387 && TARGET_CMOVE) || TARGET_SSE_MATH"
-  "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
+(define_expand "mov<mode>cc"
+  [(set (match_operand:X87MODEF 0 "register_operand" "")
+       (if_then_else:X87MODEF
+         (match_operand 1 "comparison_operator" "")
+         (match_operand:X87MODEF 2 "register_operand" "")
+         (match_operand:X87MODEF 3 "register_operand" "")))]
+  "(TARGET_80387 && TARGET_CMOVE)
+   || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+  "if (ix86_expand_fp_movcc (operands)) DONE; else FAIL;")
 
 (define_insn "*movsfcc_1_387"
   [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
   [(set_attr "type" "fcmov,fcmov,icmov,icmov")
    (set_attr "mode" "SF,SF,SI,SI")])
 
-(define_expand "movdfcc"
-  [(set (match_operand:DF 0 "register_operand" "")
-       (if_then_else:DF (match_operand 1 "comparison_operator" "")
-                        (match_operand:DF 2 "register_operand" "")
-                        (match_operand:DF 3 "register_operand" "")))]
-  "(TARGET_80387 && TARGET_CMOVE) || (TARGET_SSE2 && TARGET_SSE_MATH)"
-  "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
-
 (define_insn "*movdfcc_1"
   [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
        (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
    split_di (operands+3, 1, operands+7, operands+8);
    split_di (operands, 1, operands+2, operands+3);")
 
-(define_expand "movxfcc"
-  [(set (match_operand:XF 0 "register_operand" "")
-       (if_then_else:XF (match_operand 1 "comparison_operator" "")
-                        (match_operand:XF 2 "register_operand" "")
-                        (match_operand:XF 3 "register_operand" "")))]
-  "TARGET_80387 && TARGET_CMOVE"
-  "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
-
 (define_insn "*movxfcc_1"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
    (match_operand:QI 2 "register_operand" "")
    (match_operand:QI 3 "const_int_operand" "")]
   ""
-  "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
 
 (define_expand "addhicc"
   [(match_operand:HI 0 "register_operand" "")
    (match_operand:HI 2 "register_operand" "")
    (match_operand:HI 3 "const_int_operand" "")]
   ""
-  "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
 
 (define_expand "addsicc"
   [(match_operand:SI 0 "register_operand" "")
    (match_operand:SI 2 "register_operand" "")
    (match_operand:SI 3 "const_int_operand" "")]
   ""
-  "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
 
 (define_expand "adddicc"
   [(match_operand:DI 0 "register_operand" "")
    (match_operand:DI 2 "register_operand" "")
    (match_operand:DI 3 "const_int_operand" "")]
   "TARGET_64BIT"
-  "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+  "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
 
 \f
 ;; Misc patterns (?)
index 968fff0..97250db 100644 (file)
   DONE;
 })
 
-(define_insn "sse_movups"
-  [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
-       (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
-                    UNSPEC_MOVU))]
-  "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "movups\t{%1, %0|%0, %1}"
-  [(set_attr "type" "ssemov")
-   (set_attr "mode" "V2DF")])
-
-(define_insn "sse2_movupd"
-  [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
-       (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
-                    UNSPEC_MOVU))]
-  "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "movupd\t{%1, %0|%0, %1}"
+(define_insn "<sse>_movup<ssemodesuffixf2c>"
+  [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m")
+       (unspec:SSEMODEF2P
+         [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
+         UNSPEC_MOVU))]
+  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "movup<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
-   (set_attr "mode" "V2DF")])
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "sse2_movdqu"
   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
    (set_attr "prefix_data16" "1")
    (set_attr "mode" "TI")])
 
-(define_insn "sse_movmskps"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-       (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
-                  UNSPEC_MOVMSK))]
-  "TARGET_SSE"
-  "movmskps\t{%1, %0|%0, %1}"
-  [(set_attr "type" "ssecvt")
-   (set_attr "mode" "V4SF")])
-
-(define_insn "sse2_movmskpd"
+(define_insn "<sse>_movmskp<ssemodesuffixf2c>"
   [(set (match_operand:SI 0 "register_operand" "=r")
-       (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
-                  UNSPEC_MOVMSK))]
-  "TARGET_SSE2"
-  "movmskpd\t{%1, %0|%0, %1}"
+       (unspec:SI
+         [(match_operand:SSEMODEF2P 1 "register_operand" "x")]
+         UNSPEC_MOVMSK))]
+  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
+  "movmskp<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
-   (set_attr "mode" "V2DF")])
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "sse2_pmovmskb"
   [(set (match_operand:SI 0 "register_operand" "=r")
   "monitor"
   [(set_attr "length" "3")])
 
-;; SSSE3
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; SSSE3 instructions
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
 (define_insn "ssse3_phaddwv8hi3"
   [(set (match_operand:V8HI 0 "register_operand" "=x")
        (vec_concat:V8HI
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(define_insn "sse4a_vmmovntv2df"
-  [(set (match_operand:DF 0 "memory_operand" "=m")
-        (unspec:DF [(vec_select:DF
-                      (match_operand:V2DF 1 "register_operand" "x")
-                      (parallel [(const_int 0)]))]
-                   UNSPEC_MOVNT))]
-  "TARGET_SSE4A"
-  "movntsd\t{%1, %0|%0, %1}"
-  [(set_attr "type" "ssemov")
-   (set_attr "mode" "DF")])
-
-(define_insn "sse4a_movntdf"
-  [(set (match_operand:DF 0 "memory_operand" "=m")
-        (unspec:DF [(match_operand:DF 1 "register_operand" "x")]
-                   UNSPEC_MOVNT))]
-  "TARGET_SSE4A"
-  "movntsd\t{%1, %0|%0, %1}"
-  [(set_attr "type" "ssemov")
-   (set_attr "mode" "DF")])
-
-(define_insn "sse4a_vmmovntv4sf"
-  [(set (match_operand:SF 0 "memory_operand" "=m")
-       (unspec:SF [(vec_select:SF
-                     (match_operand:V4SF 1 "register_operand" "x")
-                     (parallel [(const_int 0)]))]
-                  UNSPEC_MOVNT))]
+(define_insn "sse4a_movnt<mode>"
+  [(set (match_operand:MODEF 0 "memory_operand" "=m")
+       (unspec:MODEF
+         [(match_operand:MODEF 1 "register_operand" "x")]
+          UNSPEC_MOVNT))]
   "TARGET_SSE4A"
-  "movntss\t{%1, %0|%0, %1}"
+  "movnts<ssemodefsuffix>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
-   (set_attr "mode" "SF")])
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "sse4a_movntsf"
-  [(set (match_operand:SF 0 "memory_operand" "=m")
-       (unspec:SF [(match_operand:SF 1 "register_operand" "x")]
-                  UNSPEC_MOVNT))]
+(define_insn "sse4a_vmmovnt<mode>"
+  [(set (match_operand:<ssescalarmode> 0 "memory_operand" "=m")
+       (unspec:<ssescalarmode>
+         [(vec_select:<ssescalarmode>
+            (match_operand:SSEMODEF2P 1 "register_operand" "x")
+            (parallel [(const_int 0)]))]
+         UNSPEC_MOVNT))]
   "TARGET_SSE4A"
-  "movntss\t{%1, %0|%0, %1}"
+  "movnts<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
-   (set_attr "mode" "SF")])
+   (set_attr "mode" "<ssescalarmode>")])
 
 (define_insn "sse4a_extrqi"
   [(set (match_operand:V2DI 0 "register_operand" "=x")
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(define_insn "sse4_1_blendpd"
-  [(set (match_operand:V2DF 0 "register_operand" "=x")
-       (vec_merge:V2DF
-         (match_operand:V2DF 2 "nonimmediate_operand" "xm")
-         (match_operand:V2DF 1 "register_operand" "0")
+(define_insn "sse4_1_blendp<ssemodesuffixf2c>"
+  [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
+       (vec_merge:SSEMODEF2P
+         (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
+         (match_operand:SSEMODEF2P 1 "register_operand" "0")
          (match_operand:SI 3 "const_0_to_3_operand" "n")))]
   "TARGET_SSE4_1"
-  "blendpd\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "ssemov")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "V2DF")])
-
-(define_insn "sse4_1_blendps"
-  [(set (match_operand:V4SF 0 "register_operand" "=x")
-       (vec_merge:V4SF
-         (match_operand:V4SF 2 "nonimmediate_operand" "xm")
-         (match_operand:V4SF 1 "register_operand" "0")
-         (match_operand:SI 3 "const_0_to_15_operand" "n")))]
-  "TARGET_SSE4_1"
-  "blendps\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "ssemov")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "V4SF")])
-
-(define_insn "sse4_1_blendvpd"
-  [(set (match_operand:V2DF 0 "reg_not_xmm0_operand" "=x")
-       (unspec:V2DF [(match_operand:V2DF 1 "reg_not_xmm0_operand"  "0")
-                     (match_operand:V2DF 2 "nonimm_not_xmm0_operand" "xm")
-                     (match_operand:V2DF 3 "register_operand" "Yz")]
-                    UNSPEC_BLENDV))]
-  "TARGET_SSE4_1"
-  "blendvpd\t{%3, %2, %0|%0, %2, %3}"
+  "blendp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
-   (set_attr "mode" "V2DF")])
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "sse4_1_blendvps"
-  [(set (match_operand:V4SF 0 "reg_not_xmm0_operand" "=x")
-       (unspec:V4SF [(match_operand:V4SF 1 "reg_not_xmm0_operand" "0")
-                     (match_operand:V4SF 2 "nonimm_not_xmm0_operand" "xm")
-                     (match_operand:V4SF 3 "register_operand" "Yz")]
-                    UNSPEC_BLENDV))]
+(define_insn "sse4_1_blendvp<ssemodesuffixf2c>"
+  [(set (match_operand:SSEMODEF2P 0 "reg_not_xmm0_operand" "=x")
+       (unspec:SSEMODEF2P
+         [(match_operand:SSEMODEF2P 1 "reg_not_xmm0_operand" "0")
+          (match_operand:SSEMODEF2P 2 "nonimm_not_xmm0_operand" "xm")
+          (match_operand:SSEMODEF2P 3 "register_operand" "Yz")]
+         UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
-  "blendvps\t{%3, %2, %0|%0, %2, %3}"
+  "blendvp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
-   (set_attr "mode" "V4SF")])
-
-(define_insn "sse4_1_dppd"
-  [(set (match_operand:V2DF 0 "register_operand" "=x")
-       (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "%0")
-                     (match_operand:V2DF 2 "nonimmediate_operand" "xm")
-                     (match_operand:SI 3 "const_0_to_255_operand" "n")]
-                     UNSPEC_DP))]
-  "TARGET_SSE4_1"
-  "dppd\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "ssemul")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "V2DF")])
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "sse4_1_dpps"
-  [(set (match_operand:V4SF 0 "register_operand" "=x")
-       (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "%0")
-                     (match_operand:V4SF 2 "nonimmediate_operand" "xm")
-                     (match_operand:SI 3 "const_0_to_255_operand" "n")]
-                    UNSPEC_DP))]
+(define_insn "sse4_1_dpp<ssemodesuffixf2c>"
+  [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
+       (unspec:SSEMODEF2P
+         [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
+          (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
+          (match_operand:SI 3 "const_0_to_255_operand" "n")]
+         UNSPEC_DP))]
   "TARGET_SSE4_1"
-  "dpps\t{%3, %2, %0|%0, %2, %3}"
+  "dpp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssemul")
    (set_attr "prefix_extra" "1")
-   (set_attr "mode" "V4SF")])
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "sse4_1_movntdqa"
   [(set (match_operand:V2DI 0 "register_operand" "=x")
    (set_attr "prefix_extra" "1")
    (set_attr "mode" "TI")])
 
-(define_insn "sse4_1_roundpd"
-  [(set (match_operand:V2DF 0 "register_operand" "=x")
-       (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm")
-                     (match_operand:SI 2 "const_0_to_15_operand" "n")]
-                    UNSPEC_ROUND))]
-  "TARGET_ROUND"
-  "roundpd\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssecvt")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "V2DF")])
-
-(define_insn "sse4_1_roundps"
-  [(set (match_operand:V4SF 0 "register_operand" "=x")
-       (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")
-                     (match_operand:SI 2 "const_0_to_15_operand" "n")]
-                    UNSPEC_ROUND))]
-  "TARGET_ROUND"
-  "roundps\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssecvt")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "V4SF")])
-
-(define_insn "sse4_1_roundsd"
-  [(set (match_operand:V2DF 0 "register_operand" "=x")
-       (vec_merge:V2DF
-         (unspec:V2DF [(match_operand:V2DF 2 "register_operand" "x")
-                       (match_operand:SI 3 "const_0_to_15_operand" "n")]
-                      UNSPEC_ROUND)
-         (match_operand:V2DF 1 "register_operand" "0")
-         (const_int 1)))]
+(define_insn "sse4_1_roundp<ssemodesuffixf2c>"
+  [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
+       (unspec:SSEMODEF2P
+         [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")
+          (match_operand:SI 2 "const_0_to_15_operand" "n")]
+         UNSPEC_ROUND))]
   "TARGET_ROUND"
-  "roundsd\t{%3, %2, %0|%0, %2, %3}"
+  "roundp<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix_extra" "1")
-   (set_attr "mode" "V2DF")])
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "sse4_1_roundss"
-  [(set (match_operand:V4SF 0 "register_operand" "=x")
-       (vec_merge:V4SF
-         (unspec:V4SF [(match_operand:V4SF 2 "register_operand" "x")
-                       (match_operand:SI 3 "const_0_to_15_operand" "n")]
-                      UNSPEC_ROUND)
-         (match_operand:V4SF 1 "register_operand" "0")
+(define_insn "sse4_1_rounds<ssemodesuffixf2c>"
+  [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
+       (vec_merge:SSEMODEF2P
+         (unspec:SSEMODEF2P
+           [(match_operand:SSEMODEF2P 2 "register_operand" "x")
+            (match_operand:SI 3 "const_0_to_15_operand" "n")]
+           UNSPEC_ROUND)
+         (match_operand:SSEMODEF2P 1 "register_operand" "0")
          (const_int 1)))]
   "TARGET_ROUND"
-  "roundss\t{%3, %2, %0|%0, %2, %3}"
+  "rounds<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix_extra" "1")
-   (set_attr "mode" "V4SF")])
+   (set_attr "mode" "<MODE>")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;