* doc/invoke.texi (-mfix-cortex-m3-ldrd): Move from ARC section to ARM.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@159073 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 26ef33b..e2c1081 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2010-05-05  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+       * doc/invoke.texi (-mfix-cortex-m3-ldrd): Move from ARC section to ARM.
+
 2010-05-05  Jason Merrill  <jason@redhat.com>
 
        PR c++/43787

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 237f894..6a60fbb 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -9742,13 +9742,6 @@ Put functions, data, and readonly data in @var{text-section},
 by default.  This can be overridden with the @code{section} attribute.
 @xref{Variable Attributes}.
 
-@item -mfix-cortex-m3-ldrd
-@opindex mfix-cortex-m3-ldrd
-Some Cortex-M3 cores can cause data corruption when @code{ldrd} instructions
-with overlapping destination and base registers are used.  This option avoids
-generating these instructions.  This option is enabled by default when
-@option{-mcpu=cortex-m3} is specified.
-
 @end table
 
 @node ARM Options
@@ -10095,6 +10088,13 @@ This is enabled by default on targets (uClinux, SymbianOS) where the runtime
 loader imposes this restriction, and when @option{-fpic} or @option{-fPIC}
 is specified.
 
+@item -mfix-cortex-m3-ldrd
+@opindex mfix-cortex-m3-ldrd
+Some Cortex-M3 cores can cause data corruption when @code{ldrd} instructions
+with overlapping destination and base registers are used.  This option avoids
+generating these instructions.  This option is enabled by default when
+@option{-mcpu=cortex-m3} is specified.
+
 @end table
 
 @node AVR Options