+2009-07-01 DJ Delorie <dj@redhat.com>
+
+ * config/mep/mep.c (mep_handle_option): Leave IVC2 control
+ registers as fixed.
+ (mep_interrupt_saved_reg): Save appropriate IVC2 control
+ registers.
+ * config/mep/mep-ivc2.cpu: Add VOLATILE to insns that make
+ unspecified accesses to control registers.
+ * config/mep/intrinsics.md: Regenerate.
+ * config/mep/intrinsics.h: Regenerate.
+ * config/mep/mep-intrin.h: Regenerate.
+
2009-07-01 Anthony Green <green@moxielogic.com>
* config/moxie/moxie.c (moxie_expand_prologue): Use dec
// default
-void mep_cpfmadila1_h (cp_v4hi, cp_v4hi, long, long);
-void mep_cpfmadiua1_h (cp_v4hi, cp_v4hi, long, long);
-void mep_cpfmadia1_b (cp_v8qi, cp_v8qi, long, long);
-void mep_cpfmadia1u_b (cp_v8uqi, cp_v8uqi, long, long);
-void mep_cpfmulila1_h (cp_v4hi, cp_v4hi, long, long);
-void mep_cpfmuliua1_h (cp_v4hi, cp_v4hi, long, long);
-void mep_cpfmulia1_b (cp_v8qi, cp_v8qi, long, long);
-void mep_cpfmulia1u_b (cp_v8uqi, cp_v8uqi, long, long);
-void mep_cpamadila1_h (cp_v4hi, cp_v4hi, long);
-void mep_cpamadiua1_h (cp_v4hi, cp_v4hi, long);
-void mep_cpamadia1_b (cp_v8qi, cp_v8qi, long);
-void mep_cpamadia1u_b (cp_v8uqi, cp_v8uqi, long);
-void mep_cpamulila1_h (cp_v4hi, cp_v4hi, long);
-void mep_cpamuliua1_h (cp_v4hi, cp_v4hi, long);
-void mep_cpamulia1_b (cp_v8qi, cp_v8qi, long);
-void mep_cpamulia1u_b (cp_v8uqi, cp_v8uqi, long);
-void mep_cpfmadila1s1_h (cp_v4hi, cp_v4hi, long);
-void mep_cpfmadiua1s1_h (cp_v4hi, cp_v4hi, long);
-void mep_cpfmadia1s1_b (cp_v8qi, cp_v8qi, long);
-void mep_cpfmadia1s1u_b (cp_v8uqi, cp_v8uqi, long);
-void mep_cpfmulila1s1_h (cp_v4hi, cp_v4hi, long);
-void mep_cpfmuliua1s1_h (cp_v4hi, cp_v4hi, long);
-void mep_cpfmulia1s1_b (cp_v8qi, cp_v8qi, long);
-void mep_cpfmulia1s1u_b (cp_v8uqi, cp_v8uqi, long);
-void mep_cpfmadila1s0_h (cp_v4hi, cp_v4hi, long);
-void mep_cpfmadiua1s0_h (cp_v4hi, cp_v4hi, long);
-void mep_cpfmadia1s0_b (cp_v8qi, cp_v8qi, long);
-void mep_cpfmadia1s0u_b (cp_v8uqi, cp_v8uqi, long);
-void mep_cpfmulila1s0_h (cp_v4hi, cp_v4hi, long);
-void mep_cpfmuliua1s0_h (cp_v4hi, cp_v4hi, long);
-void mep_cpfmulia1s0_b (cp_v8qi, cp_v8qi, long);
-void mep_cpfmulia1s0u_b (cp_v8uqi, cp_v8uqi, long);
+void mep_cpfmadila1_h (cp_v4hi, cp_v4hi, long, long); // volatile
+void mep_cpfmadiua1_h (cp_v4hi, cp_v4hi, long, long); // volatile
+void mep_cpfmadia1_b (cp_v8qi, cp_v8qi, long, long); // volatile
+void mep_cpfmadia1u_b (cp_v8uqi, cp_v8uqi, long, long); // volatile
+void mep_cpfmulila1_h (cp_v4hi, cp_v4hi, long, long); // volatile
+void mep_cpfmuliua1_h (cp_v4hi, cp_v4hi, long, long); // volatile
+void mep_cpfmulia1_b (cp_v8qi, cp_v8qi, long, long); // volatile
+void mep_cpfmulia1u_b (cp_v8uqi, cp_v8uqi, long, long); // volatile
+void mep_cpamadila1_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpamadiua1_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpamadia1_b (cp_v8qi, cp_v8qi, long); // volatile
+void mep_cpamadia1u_b (cp_v8uqi, cp_v8uqi, long); // volatile
+void mep_cpamulila1_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpamuliua1_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpamulia1_b (cp_v8qi, cp_v8qi, long); // volatile
+void mep_cpamulia1u_b (cp_v8uqi, cp_v8uqi, long); // volatile
+void mep_cpfmadila1s1_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpfmadiua1s1_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpfmadia1s1_b (cp_v8qi, cp_v8qi, long); // volatile
+void mep_cpfmadia1s1u_b (cp_v8uqi, cp_v8uqi, long); // volatile
+void mep_cpfmulila1s1_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpfmuliua1s1_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpfmulia1s1_b (cp_v8qi, cp_v8qi, long); // volatile
+void mep_cpfmulia1s1u_b (cp_v8uqi, cp_v8uqi, long); // volatile
+void mep_cpfmadila1s0_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpfmadiua1s0_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpfmadia1s0_b (cp_v8qi, cp_v8qi, long); // volatile
+void mep_cpfmadia1s0u_b (cp_v8uqi, cp_v8uqi, long); // volatile
+void mep_cpfmulila1s0_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpfmuliua1s0_h (cp_v4hi, cp_v4hi, long); // volatile
+void mep_cpfmulia1s0_b (cp_v8qi, cp_v8qi, long); // volatile
+void mep_cpfmulia1s0u_b (cp_v8uqi, cp_v8uqi, long); // volatile
void mep_cpacswp (); // volatile
-void mep_cpaccpa1 ();
-void mep_cpacsuma1 ();
+void mep_cpaccpa1 (); // volatile
+void mep_cpacsuma1 (); // volatile
void mep_c1nop (); // volatile
-void mep_cpfacla0s1_h (cp_v4hi, cp_v4hi);
-void mep_cpfacua0s1_h (cp_v4hi, cp_v4hi);
-void mep_cpfaca0s1_b (cp_v8qi, cp_v8qi);
-void mep_cpfaca0s1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpfsftbla0s1_h (cp_v4hi, cp_v4hi);
-void mep_cpfsftbua0s1_h (cp_v4hi, cp_v4hi);
-void mep_cpfsftba0s1_b (cp_v8qi, cp_v8qi);
-void mep_cpfsftba0s1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpfacla0s0_h (cp_v4hi, cp_v4hi);
-void mep_cpfacua0s0_h (cp_v4hi, cp_v4hi);
-void mep_cpfaca0s0_b (cp_v8qi, cp_v8qi);
-void mep_cpfaca0s0u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpfsftbla0s0_h (cp_v4hi, cp_v4hi);
-void mep_cpfsftbua0s0_h (cp_v4hi, cp_v4hi);
-void mep_cpfsftba0s0_b (cp_v8qi, cp_v8qi);
-void mep_cpfsftba0s0u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpsllia0 (long);
-void mep_cpsraia0 (long);
-void mep_cpsrlia0 (long);
-void mep_cpslla0 (cp_data_bus_int);
-void mep_cpsraa0 (cp_data_bus_int);
-void mep_cpsrla0 (cp_data_bus_int);
-void mep_cpaccpa0 ();
-void mep_cpacsuma0 ();
+void mep_cpfacla0s1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpfacua0s1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpfaca0s1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpfaca0s1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpfsftbla0s1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpfsftbua0s1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpfsftba0s1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpfsftba0s1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpfacla0s0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpfacua0s0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpfaca0s0_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpfaca0s0u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpfsftbla0s0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpfsftbua0s0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpfsftba0s0_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpfsftba0s0u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpsllia0 (long); // volatile
+void mep_cpsraia0 (long); // volatile
+void mep_cpsrlia0 (long); // volatile
+void mep_cpslla0 (cp_data_bus_int); // volatile
+void mep_cpsraa0 (cp_data_bus_int); // volatile
+void mep_cpsrla0 (cp_data_bus_int); // volatile
+void mep_cpaccpa0 (); // volatile
+void mep_cpacsuma0 (); // volatile
cp_v2si mep_cpmovhla0_w ();
cp_v2si mep_cpmovhua0_w ();
cp_v2si mep_cppackla0_w ();
cp_v4hi mep_cpmovla0_h ();
cp_v4hi mep_cpmovua0_h ();
cp_v8qi mep_cpmova0_b ();
-void mep_cpsetla0_w (cp_v2si, cp_v2si);
-void mep_cpsetua0_w (cp_v2si, cp_v2si);
-void mep_cpseta0_h (cp_v4hi, cp_v4hi);
-void mep_cpsadla0_h (cp_v4hi, cp_v4hi);
-void mep_cpsadua0_h (cp_v4hi, cp_v4hi);
-void mep_cpsada0_b (cp_v8qi, cp_v8qi);
-void mep_cpsada0u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpabsla0_h (cp_v4hi, cp_v4hi);
-void mep_cpabsua0_h (cp_v4hi, cp_v4hi);
-void mep_cpabsa0_b (cp_v8qi, cp_v8qi);
-void mep_cpabsa0u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpsubacla0_h (cp_v4hi, cp_v4hi);
-void mep_cpsubacua0_h (cp_v4hi, cp_v4hi);
-void mep_cpsubaca0_b (cp_v8qi, cp_v8qi);
-void mep_cpsubaca0u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpsubla0_h (cp_v4hi, cp_v4hi);
-void mep_cpsubua0_h (cp_v4hi, cp_v4hi);
-void mep_cpsuba0_b (cp_v8qi, cp_v8qi);
-void mep_cpsuba0u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpaddacla0_h (cp_v4hi, cp_v4hi);
-void mep_cpaddacua0_h (cp_v4hi, cp_v4hi);
-void mep_cpaddaca0_b (cp_v8qi, cp_v8qi);
-void mep_cpaddaca0u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpaddla0_h (cp_v4hi, cp_v4hi);
-void mep_cpaddua0_h (cp_v4hi, cp_v4hi);
-void mep_cpadda0_b (cp_v8qi, cp_v8qi);
-void mep_cpadda0u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpsetla0_w (cp_v2si, cp_v2si); // volatile
+void mep_cpsetua0_w (cp_v2si, cp_v2si); // volatile
+void mep_cpseta0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsadla0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsadua0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsada0_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpsada0u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpabsla0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpabsua0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpabsa0_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpabsa0u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpsubacla0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsubacua0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsubaca0_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpsubaca0u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpsubla0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsubua0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsuba0_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpsuba0u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpaddacla0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpaddacua0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpaddaca0_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpaddaca0u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpaddla0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpaddua0_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpadda0_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpadda0u_b (cp_v8uqi, cp_v8uqi); // volatile
void mep_c0nop (); // volatile
-void mep_cpsmsbslla1_w (cp_v2si, cp_v2si);
-void mep_cpsmsbslua1_w (cp_v2si, cp_v2si);
-void mep_cpsmsbslla1_h (cp_v4hi, cp_v4hi);
-void mep_cpsmsbslua1_h (cp_v4hi, cp_v4hi);
-void mep_cpsmadslla1_w (cp_v2si, cp_v2si);
-void mep_cpsmadslua1_w (cp_v2si, cp_v2si);
-void mep_cpsmadslla1_h (cp_v4hi, cp_v4hi);
-void mep_cpsmadslua1_h (cp_v4hi, cp_v4hi);
-void mep_cpmulslla1_w (cp_v2si, cp_v2si);
-void mep_cpmulslua1_w (cp_v2si, cp_v2si);
-void mep_cpmulslla1_h (cp_v4hi, cp_v4hi);
-void mep_cpmulslua1_h (cp_v4hi, cp_v4hi);
-void mep_cpsmsbla1_w (cp_v2si, cp_v2si);
-void mep_cpsmsbua1_w (cp_v2si, cp_v2si);
-void mep_cpsmsbla1_h (cp_v4hi, cp_v4hi);
-void mep_cpsmsbua1_h (cp_v4hi, cp_v4hi);
-void mep_cpsmadla1_w (cp_v2si, cp_v2si);
-void mep_cpsmadua1_w (cp_v2si, cp_v2si);
-void mep_cpsmadla1_h (cp_v4hi, cp_v4hi);
-void mep_cpsmadua1_h (cp_v4hi, cp_v4hi);
-void mep_cpmsbla1_w (cp_v2si, cp_v2si);
-void mep_cpmsbua1_w (cp_v2si, cp_v2si);
-void mep_cpmsbla1u_w (cp_v2usi, cp_v2usi);
-void mep_cpmsbua1u_w (cp_v2usi, cp_v2usi);
-void mep_cpmsbla1_h (cp_v4hi, cp_v4hi);
-void mep_cpmsbua1_h (cp_v4hi, cp_v4hi);
-void mep_cpmadla1_w (cp_v2si, cp_v2si);
-void mep_cpmadua1_w (cp_v2si, cp_v2si);
-void mep_cpmadla1u_w (cp_v2usi, cp_v2usi);
-void mep_cpmadua1u_w (cp_v2usi, cp_v2usi);
-void mep_cpmadla1_h (cp_v4hi, cp_v4hi);
-void mep_cpmadua1_h (cp_v4hi, cp_v4hi);
-void mep_cpmada1_b (cp_v8qi, cp_v8qi);
-void mep_cpmada1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpmulla1_w (cp_v2si, cp_v2si);
-void mep_cpmulua1_w (cp_v2si, cp_v2si);
-void mep_cpmulla1u_w (cp_v2usi, cp_v2usi);
-void mep_cpmulua1u_w (cp_v2usi, cp_v2usi);
-void mep_cpmulla1_h (cp_v4hi, cp_v4hi);
-void mep_cpmulua1_h (cp_v4hi, cp_v4hi);
-void mep_cpmula1_b (cp_v8qi, cp_v8qi);
-void mep_cpmula1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpssda1_b (cp_v8qi, cp_v8qi);
-void mep_cpssda1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpssqa1_b (cp_v8qi, cp_v8qi);
-void mep_cpssqa1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpsllia1 (long);
-void mep_cpsraia1 (long);
-void mep_cpsrlia1 (long);
-void mep_cpslla1 (cp_data_bus_int);
-void mep_cpsraa1 (cp_data_bus_int);
-void mep_cpsrla1 (cp_data_bus_int);
+void mep_cpsmsbslla1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpsmsbslua1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpsmsbslla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsmsbslua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsmadslla1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpsmadslua1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpsmadslla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsmadslua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpmulslla1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpmulslua1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpmulslla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpmulslua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsmsbla1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpsmsbua1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpsmsbla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsmsbua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsmadla1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpsmadua1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpsmadla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsmadua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpmsbla1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpmsbua1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpmsbla1u_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpmsbua1u_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpmsbla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpmsbua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpmadla1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpmadua1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpmadla1u_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpmadua1u_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpmadla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpmadua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpmada1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpmada1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpmulla1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpmulua1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpmulla1u_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpmulua1u_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpmulla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpmulua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpmula1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpmula1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpssda1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpssda1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpssqa1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpssqa1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpsllia1 (long); // volatile
+void mep_cpsraia1 (long); // volatile
+void mep_cpsrlia1 (long); // volatile
+void mep_cpslla1 (cp_data_bus_int); // volatile
+void mep_cpsraa1 (cp_data_bus_int); // volatile
+void mep_cpsrla1 (cp_data_bus_int); // volatile
cp_v2si mep_cpmovhla1_w ();
cp_v2si mep_cpmovhua1_w ();
cp_v2si mep_cppackla1_w ();
cp_v4hi mep_cpmovla1_h ();
cp_v4hi mep_cpmovua1_h ();
cp_v8qi mep_cpmova1_b ();
-void mep_cpsetla1_w (cp_v2si, cp_v2si);
-void mep_cpsetua1_w (cp_v2si, cp_v2si);
-void mep_cpseta1_h (cp_v4hi, cp_v4hi);
-void mep_cpsadla1_h (cp_v4hi, cp_v4hi);
-void mep_cpsadua1_h (cp_v4hi, cp_v4hi);
-void mep_cpsada1_b (cp_v8qi, cp_v8qi);
-void mep_cpsada1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpabsla1_h (cp_v4hi, cp_v4hi);
-void mep_cpabsua1_h (cp_v4hi, cp_v4hi);
-void mep_cpabsa1_b (cp_v8qi, cp_v8qi);
-void mep_cpabsa1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpsubacla1_h (cp_v4hi, cp_v4hi);
-void mep_cpsubacua1_h (cp_v4hi, cp_v4hi);
-void mep_cpsubaca1_b (cp_v8qi, cp_v8qi);
-void mep_cpsubaca1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpsubla1_h (cp_v4hi, cp_v4hi);
-void mep_cpsubua1_h (cp_v4hi, cp_v4hi);
-void mep_cpsuba1_b (cp_v8qi, cp_v8qi);
-void mep_cpsuba1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpaddacla1_h (cp_v4hi, cp_v4hi);
-void mep_cpaddacua1_h (cp_v4hi, cp_v4hi);
-void mep_cpaddaca1_b (cp_v8qi, cp_v8qi);
-void mep_cpaddaca1u_b (cp_v8uqi, cp_v8uqi);
-void mep_cpaddla1_h (cp_v4hi, cp_v4hi);
-void mep_cpaddua1_h (cp_v4hi, cp_v4hi);
-void mep_cpadda1_b (cp_v8qi, cp_v8qi);
-void mep_cpadda1u_b (cp_v8uqi, cp_v8uqi);
+void mep_cpsetla1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpsetua1_w (cp_v2si, cp_v2si); // volatile
+void mep_cpseta1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsadla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsadua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsada1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpsada1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpabsla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpabsua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpabsa1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpabsa1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpsubacla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsubacua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsubaca1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpsubaca1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpsubla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsubua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpsuba1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpsuba1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpaddacla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpaddacua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpaddaca1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpaddaca1u_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpaddla1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpaddua1_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpadda1_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpadda1u_b (cp_v8uqi, cp_v8uqi); // volatile
cp_data_bus_int mep_cdmovi (long);
cp_data_bus_int mep_cdmoviu (long);
cp_v2si mep_cpmovi_w (long);
void mep_cpacmpeq_w (cp_v2si, cp_v2si); // volatile
void mep_cpacmpeq_h (cp_v4hi, cp_v4hi); // volatile
void mep_cpacmpeq_b (cp_v8qi, cp_v8qi); // volatile
-void mep_cpcmpge_w (cp_v2si, cp_v2si);
-void mep_cpcmpgeu_w (cp_v2usi, cp_v2usi);
-void mep_cpcmpge_h (cp_v4hi, cp_v4hi);
-void mep_cpcmpge_b (cp_v8qi, cp_v8qi);
-void mep_cpcmpgeu_b (cp_v8uqi, cp_v8uqi);
-void mep_cpcmpgt_w (cp_v2si, cp_v2si);
-void mep_cpcmpgtu_w (cp_v2usi, cp_v2usi);
-void mep_cpcmpgt_h (cp_v4hi, cp_v4hi);
-void mep_cpcmpgt_b (cp_v8qi, cp_v8qi);
-void mep_cpcmpgtu_b (cp_v8uqi, cp_v8uqi);
-void mep_cpcmpne_w (cp_v2si, cp_v2si);
-void mep_cpcmpne_h (cp_v4hi, cp_v4hi);
-void mep_cpcmpne_b (cp_v8qi, cp_v8qi);
-void mep_cpcmpeq_w (cp_v2si, cp_v2si);
-void mep_cpcmpeq_h (cp_v4hi, cp_v4hi);
-void mep_cpcmpeq_b (cp_v8qi, cp_v8qi);
-void mep_cpcmpeqz_b (cp_v8qi, cp_v8qi);
+void mep_cpcmpge_w (cp_v2si, cp_v2si); // volatile
+void mep_cpcmpgeu_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpcmpge_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpcmpge_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpcmpgeu_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpcmpgt_w (cp_v2si, cp_v2si); // volatile
+void mep_cpcmpgtu_w (cp_v2usi, cp_v2usi); // volatile
+void mep_cpcmpgt_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpcmpgt_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpcmpgtu_b (cp_v8uqi, cp_v8uqi); // volatile
+void mep_cpcmpne_w (cp_v2si, cp_v2si); // volatile
+void mep_cpcmpne_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpcmpne_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpcmpeq_w (cp_v2si, cp_v2si); // volatile
+void mep_cpcmpeq_h (cp_v4hi, cp_v4hi); // volatile
+void mep_cpcmpeq_b (cp_v8qi, cp_v8qi); // volatile
+void mep_cpcmpeqz_b (cp_v8qi, cp_v8qi); // volatile
cp_data_bus_int mep_cdcastw (cp_data_bus_int);
cp_data_bus_int mep_cdcastuw (cp_data_bus_int);
cp_v2si mep_cpcasth_w (cp_v2si);
(define_insn "cgen_intrinsic_cpsmsbslla1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2198))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2199))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2200))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2201))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2202))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2203))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2204))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2205))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2206))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2207))]
+ ] 2206))]
"CGEN_ENABLE_INSN_P (0)"
"cpsmsbslla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbslla1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2198))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2199))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2200))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2201))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2202))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2203))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2204))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2205))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2206))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2207))]
+ ] 2206))]
"CGEN_ENABLE_INSN_P (1)"
"cpsmsbslla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbslua1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2208))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2209))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2210))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2211))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2212))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2213))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2214))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2215))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2216))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2217))]
+ ] 2216))]
"CGEN_ENABLE_INSN_P (2)"
"cpsmsbslua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbslua1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2208))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2209))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2210))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2211))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2212))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2213))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2214))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2215))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2216))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2217))]
+ ] 2216))]
"CGEN_ENABLE_INSN_P (3)"
"cpsmsbslua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbslla1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2218))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2219))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2220))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2221))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2222))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2223))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2224))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2225))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2226))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2227))]
+ ] 2226))]
"CGEN_ENABLE_INSN_P (4)"
"cpsmsbslla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbslla1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2218))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2219))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2220))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2221))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2222))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2223))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2224))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2225))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2226))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2227))]
+ ] 2226))]
"CGEN_ENABLE_INSN_P (5)"
"cpsmsbslla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbslua1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2228))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2229))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2230))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2231))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2232))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2233))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2234))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2235))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2236))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2237))]
+ ] 2236))]
"CGEN_ENABLE_INSN_P (6)"
"cpsmsbslua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbslua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2228))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2229))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2230))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2231))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2232))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2233))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2234))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2235))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2236))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2237))]
+ ] 2236))]
"CGEN_ENABLE_INSN_P (7)"
"cpsmsbslua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadslla1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2238))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2239))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2240))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2241))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2242))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2243))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2244))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2245))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2246))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2247))]
+ ] 2246))]
"CGEN_ENABLE_INSN_P (8)"
"cpsmadslla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadslla1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2238))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2239))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2240))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2241))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2242))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2243))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2244))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2245))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2246))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2247))]
+ ] 2246))]
"CGEN_ENABLE_INSN_P (9)"
"cpsmadslla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadslua1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2248))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2249))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2250))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2251))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2252))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2253))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2254))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2255))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2256))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2257))]
+ ] 2256))]
"CGEN_ENABLE_INSN_P (10)"
"cpsmadslua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadslua1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2248))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2249))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2250))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2251))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2252))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2253))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2254))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2255))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2256))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2257))]
+ ] 2256))]
"CGEN_ENABLE_INSN_P (11)"
"cpsmadslua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadslla1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2258))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2259))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2260))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2261))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2262))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2263))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2264))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2265))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2266))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2267))]
+ ] 2266))]
"CGEN_ENABLE_INSN_P (12)"
"cpsmadslla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadslla1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2258))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2259))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2260))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2261))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2262))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2263))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2264))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2265))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2266))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2267))]
+ ] 2266))]
"CGEN_ENABLE_INSN_P (13)"
"cpsmadslla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadslua1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2268))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2269))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2270))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2271))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2272))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2273))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2274))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2275))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2276))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2277))]
+ ] 2276))]
"CGEN_ENABLE_INSN_P (14)"
"cpsmadslua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadslua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2268))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2269))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2270))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2271))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2272))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2273))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2274))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2275))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2276))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2277))]
+ ] 2276))]
"CGEN_ENABLE_INSN_P (15)"
"cpsmadslua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulslla1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2278))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2279))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2280))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2281))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2282))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2283))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2284))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2285))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2286))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2287))]
+ ] 2286))]
"CGEN_ENABLE_INSN_P (16)"
"cpmulslla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulslla1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2278))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2279))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2280))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2281))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2282))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2283))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2284))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2285))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2286))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2287))]
+ ] 2286))]
"CGEN_ENABLE_INSN_P (17)"
"cpmulslla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulslua1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2288))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2289))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2290))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2291))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2292))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2293))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2294))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2295))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2296))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2297))]
+ ] 2296))]
"CGEN_ENABLE_INSN_P (18)"
"cpmulslua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulslua1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2288))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2289))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2290))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2291))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2292))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2293))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2294))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2295))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2296))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2297))]
+ ] 2296))]
"CGEN_ENABLE_INSN_P (19)"
"cpmulslua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulslla1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2298))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2299))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2300))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2301))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2302))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2303))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2304))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2305))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2306))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2307))]
+ ] 2306))]
"CGEN_ENABLE_INSN_P (20)"
"cpmulslla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulslla1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2298))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2299))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2300))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2301))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2302))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2303))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2304))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2305))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2306))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2307))]
+ ] 2306))]
"CGEN_ENABLE_INSN_P (21)"
"cpmulslla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulslua1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2308))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2309))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2310))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2311))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2312))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2313))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2314))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2315))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2316))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2317))]
+ ] 2316))]
"CGEN_ENABLE_INSN_P (22)"
"cpmulslua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulslua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2308))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2309))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2310))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2311))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2312))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2313))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2314))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2315))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2316))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2317))]
+ ] 2316))]
"CGEN_ENABLE_INSN_P (23)"
"cpmulslua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbla1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2318))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2319))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2320))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2321))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2322))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2323))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2324))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2325))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2326))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2327))]
+ ] 2326))]
"CGEN_ENABLE_INSN_P (24)"
"cpsmsbla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbla1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2318))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2319))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2320))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2321))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2322))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2323))
- (set (reg:SI 105)
- (unspec:SI [
+ (set (reg:SI 105)
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2324))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2325))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2326))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2327))]
+ ] 2326))]
"CGEN_ENABLE_INSN_P (25)"
"cpsmsbla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbua1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2328))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2329))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2330))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2331))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2332))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2333))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2334))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2335))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2336))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2337))]
+ ] 2336))]
"CGEN_ENABLE_INSN_P (26)"
"cpsmsbua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbua1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2328))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2329))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2330))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2331))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2332))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2333))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2334))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2335))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2336))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2337))]
+ ] 2336))]
"CGEN_ENABLE_INSN_P (27)"
"cpsmsbua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbla1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2338))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2339))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2340))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2341))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2342))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2343))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2344))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2345))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2346))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2347))]
+ ] 2346))]
"CGEN_ENABLE_INSN_P (28)"
"cpsmsbla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbla1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2338))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2339))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2340))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2341))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2342))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2343))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2344))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2345))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2346))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2347))]
+ ] 2346))]
"CGEN_ENABLE_INSN_P (29)"
"cpsmsbla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbua1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2348))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2349))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2350))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2351))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2352))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2353))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2354))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2355))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2356))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2357))]
+ ] 2356))]
"CGEN_ENABLE_INSN_P (30)"
"cpsmsbua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmsbua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2348))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2349))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2350))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2351))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2352))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2353))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2354))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2355))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2356))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2357))]
+ ] 2356))]
"CGEN_ENABLE_INSN_P (31)"
"cpsmsbua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadla1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2358))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2359))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2360))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2361))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2362))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2363))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2364))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2365))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2366))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2367))]
+ ] 2366))]
"CGEN_ENABLE_INSN_P (32)"
"cpsmadla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadla1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2358))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2359))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2360))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2361))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2362))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2363))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2364))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2365))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2366))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2367))]
+ ] 2366))]
"CGEN_ENABLE_INSN_P (33)"
"cpsmadla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadua1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2368))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2369))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2370))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2371))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2372))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2373))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2374))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2375))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2376))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2377))]
+ ] 2376))]
"CGEN_ENABLE_INSN_P (34)"
"cpsmadua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadua1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2368))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2369))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2370))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2371))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2372))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2373))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2374))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2375))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2376))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2377))]
+ ] 2376))]
"CGEN_ENABLE_INSN_P (35)"
"cpsmadua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadla1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2378))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2379))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2380))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2381))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2382))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2383))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2384))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2385))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2386))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2387))]
+ ] 2386))]
"CGEN_ENABLE_INSN_P (36)"
"cpsmadla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadla1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2378))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2379))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2380))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2381))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2382))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2383))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2384))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2385))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2386))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2387))]
+ ] 2386))]
"CGEN_ENABLE_INSN_P (37)"
"cpsmadla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadua1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2388))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2389))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2390))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2391))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2392))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2393))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2394))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2395))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2396))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2397))]
+ ] 2396))]
"CGEN_ENABLE_INSN_P (38)"
"cpsmadua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsmadua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2388))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2389))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2390))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2391))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2392))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2393))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2394))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2395))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2396))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2397))]
+ ] 2396))]
"CGEN_ENABLE_INSN_P (39)"
"cpsmadua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbla1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2398))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2399))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2400))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2401))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2402))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2403))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2404))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2405))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2406))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2407))]
+ ] 2406))]
"CGEN_ENABLE_INSN_P (40)"
"cpmsbla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbla1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2398))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2399))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2400))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2401))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2402))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2403))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2404))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2405))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2406))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2407))]
+ ] 2406))]
"CGEN_ENABLE_INSN_P (41)"
"cpmsbla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbua1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2408))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2409))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2410))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2411))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2412))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2413))
- (set (reg:SI 109)
- (unspec:SI [
+ (set (reg:SI 109)
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2414))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2415))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2416))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2417))]
+ ] 2416))]
"CGEN_ENABLE_INSN_P (42)"
"cpmsbua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbua1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2408))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2409))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2410))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2411))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2412))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2413))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2414))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2415))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2416))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2417))]
+ ] 2416))]
"CGEN_ENABLE_INSN_P (43)"
"cpmsbua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbla1u_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2418))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2419))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2420))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2421))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2422))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2423))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2424))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2425))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2426))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2427))]
+ ] 2426))]
"CGEN_ENABLE_INSN_P (44)"
"cpmsbla1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbla1u_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2418))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2419))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2420))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2421))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2422))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2423))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2424))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2425))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2426))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2427))]
+ ] 2426))]
"CGEN_ENABLE_INSN_P (45)"
"cpmsbla1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbua1u_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2428))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2429))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2430))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2431))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2432))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2433))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2434))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2435))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2436))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2437))]
+ ] 2436))]
"CGEN_ENABLE_INSN_P (46)"
"cpmsbua1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbua1u_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2428))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2429))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2430))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2431))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2432))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2433))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2434))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2435))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2436))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2437))]
+ ] 2436))]
"CGEN_ENABLE_INSN_P (47)"
"cpmsbua1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbla1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2438))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2439))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2440))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2441))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2442))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2443))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2444))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2445))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2446))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2447))]
+ ] 2446))]
"CGEN_ENABLE_INSN_P (48)"
"cpmsbla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbla1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2438))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2439))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2440))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2441))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2442))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2443))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2444))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2445))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2446))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2447))]
+ ] 2446))]
"CGEN_ENABLE_INSN_P (49)"
"cpmsbla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbua1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2448))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2449))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2450))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2451))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2452))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2453))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2454))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2455))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2456))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2457))]
+ ] 2456))]
"CGEN_ENABLE_INSN_P (50)"
"cpmsbua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmsbua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2448))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2449))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2450))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2451))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2452))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2453))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2454))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2455))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2456))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2457))]
+ ] 2456))]
"CGEN_ENABLE_INSN_P (51)"
"cpmsbua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadla1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2458))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2459))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2460))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2461))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2462))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2463))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2464))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2465))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2466))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2467))]
+ ] 2466))]
"CGEN_ENABLE_INSN_P (52)"
"cpmadla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadla1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2458))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2459))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2460))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2461))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2462))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2463))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2464))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2465))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2466))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2467))]
+ ] 2466))]
"CGEN_ENABLE_INSN_P (53)"
"cpmadla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadua1_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2468))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2469))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2470))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2471))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2472))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2473))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2474))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2475))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2476))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2477))]
+ ] 2476))]
"CGEN_ENABLE_INSN_P (54)"
"cpmadua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadua1_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2468))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2469))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2470))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2471))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2472))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2473))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2474))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2475))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2476))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2477))]
+ ] 2476))]
"CGEN_ENABLE_INSN_P (55)"
"cpmadua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadla1u_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2478))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2479))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2480))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2481))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2482))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2483))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2484))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2485))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2486))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2487))]
+ ] 2486))]
"CGEN_ENABLE_INSN_P (56)"
"cpmadla1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadla1u_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2478))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2479))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2480))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2481))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2482))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2483))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2484))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2485))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2486))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2487))]
+ ] 2486))]
"CGEN_ENABLE_INSN_P (57)"
"cpmadla1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadua1u_w_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2488))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2489))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2490))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2491))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2492))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2493))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2494))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2495))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2496))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2497))]
+ ] 2496))]
"CGEN_ENABLE_INSN_P (58)"
"cpmadua1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadua1u_w_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2488))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2489))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2490))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2491))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2492))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2493))
- (set (reg:SI 109)
- (unspec:SI [
+ (set (reg:SI 109)
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2494))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2495))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2496))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2497))]
+ ] 2496))]
"CGEN_ENABLE_INSN_P (59)"
"cpmadua1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadla1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2498))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2499))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2500))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2501))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2502))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2503))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2504))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2505))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2506))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2507))]
+ ] 2506))]
"CGEN_ENABLE_INSN_P (60)"
"cpmadla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadla1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2498))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2499))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2500))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2501))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2502))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2503))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2504))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2505))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2506))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2507))]
+ ] 2506))]
"CGEN_ENABLE_INSN_P (61)"
"cpmadla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadua1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2508))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2509))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2510))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2511))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2512))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2513))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2514))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2515))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2516))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2517))]
+ ] 2516))]
"CGEN_ENABLE_INSN_P (62)"
"cpmadua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmadua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2508))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2509))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2510))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2511))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2512))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2513))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2514))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2515))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2516))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2517))]
+ ] 2516))]
"CGEN_ENABLE_INSN_P (63)"
"cpmadua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmada1_b_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2518))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2519))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2520))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2521))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2522))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2523))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2524))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2525))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2526))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2527))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2528))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2529))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2530))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2531))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2532))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2533))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2534))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2535))]
+ ] 2534))]
"CGEN_ENABLE_INSN_P (64)"
"cpmada1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmada1_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2518))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2519))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2520))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2521))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2522))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2523))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2524))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2525))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2526))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2527))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2528))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2529))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2530))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2531))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2532))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2533))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2534))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2535))]
+ ] 2534))]
"CGEN_ENABLE_INSN_P (65)"
"cpmada1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmada1u_b_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2536))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2537))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2538))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2539))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2540))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2541))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2542))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2543))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2544))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2545))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2546))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2547))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2548))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2549))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2550))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2551))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2552))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2553))]
+ ] 2552))]
"CGEN_ENABLE_INSN_P (66)"
"cpmada1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmada1u_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2536))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2537))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2538))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2539))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2540))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2541))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2542))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2543))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2544))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2545))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2546))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2547))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2548))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2549))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2550))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2551))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2552))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2553))]
+ ] 2552))]
"CGEN_ENABLE_INSN_P (67)"
"cpmada1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulla1_w_C3"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2554))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2555))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2556))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2557))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2558))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2559))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2560))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2561))]
+ ] 2560))]
"CGEN_ENABLE_INSN_P (68)"
"cpmulla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulla1_w_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2554))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2555))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2556))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2557))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2558))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2559))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2560))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2561))]
+ ] 2560))]
"CGEN_ENABLE_INSN_P (69)"
"cpmulla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulua1_w_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2562))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2563))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2564))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2565))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2566))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2567))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2568))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2569))]
+ ] 2568))]
"CGEN_ENABLE_INSN_P (70)"
"cpmulua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulua1_w_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2562))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2563))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2564))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2565))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2566))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2567))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2568))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2569))]
+ ] 2568))]
"CGEN_ENABLE_INSN_P (71)"
"cpmulua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulla1u_w_C3"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2570))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2571))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2572))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2573))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2574))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2575))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2576))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2577))]
+ ] 2576))]
"CGEN_ENABLE_INSN_P (72)"
"cpmulla1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulla1u_w_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2570))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2571))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2572))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2573))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2574))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2575))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2576))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2577))]
+ ] 2576))]
"CGEN_ENABLE_INSN_P (73)"
"cpmulla1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulua1u_w_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2578))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2579))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2580))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2581))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2582))
- (set (reg:SI 120)
- (unspec:SI [
+ (set (reg:SI 108)
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2583))
- (set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2584))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2585))]
+ ] 2584))]
"CGEN_ENABLE_INSN_P (74)"
"cpmulua1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulua1u_w_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2578))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2579))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2580))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2581))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2582))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2583))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2584))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2585))]
+ ] 2584))]
"CGEN_ENABLE_INSN_P (75)"
"cpmulua1u.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulla1_h_C3"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2586))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2587))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2588))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2589))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2590))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2591))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2592))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2593))]
+ ] 2592))]
"CGEN_ENABLE_INSN_P (76)"
"cpmulla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulla1_h_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2586))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2587))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2588))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2589))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2590))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2591))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2592))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2593))]
+ ] 2592))]
"CGEN_ENABLE_INSN_P (77)"
"cpmulla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulua1_h_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2594))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2595))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2596))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2597))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2598))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2599))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2600))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2601))]
+ ] 2600))]
"CGEN_ENABLE_INSN_P (78)"
"cpmulua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmulua1_h_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2594))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2595))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2596))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2597))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2598))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2599))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2600))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2601))]
+ ] 2600))]
"CGEN_ENABLE_INSN_P (79)"
"cpmulua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmula1_b_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2602))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2603))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2604))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2605))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2606))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2607))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2608))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2609))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2610))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2611))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2612))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2613))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2614))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2615))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2616))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2617))]
+ ] 2616))]
"CGEN_ENABLE_INSN_P (80)"
"cpmula1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmula1_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2602))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2603))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2604))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2605))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2606))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2607))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2608))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2609))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2610))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2611))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2612))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2613))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2614))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2615))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2616))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2617))]
+ ] 2616))]
"CGEN_ENABLE_INSN_P (81)"
"cpmula1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmula1u_b_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2618))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2619))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2620))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2621))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2622))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2623))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2624))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2625))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2626))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2627))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2628))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2629))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2630))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2631))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2632))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2633))]
+ ] 2632))]
"CGEN_ENABLE_INSN_P (82)"
"cpmula1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpmula1u_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2618))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2619))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2620))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2621))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2622))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2623))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2624))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2625))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2626))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2627))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2628))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2629))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2630))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2631))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2632))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2633))]
+ ] 2632))]
"CGEN_ENABLE_INSN_P (83)"
"cpmula1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpssda1_b_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2634))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2635))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2636))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2637))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2638))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2639))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2640))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2641))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2642))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2643))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2644))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2645))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2646))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2647))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2648))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2649))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2650))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2651))]
+ ] 2650))]
"CGEN_ENABLE_INSN_P (84)"
"cpssda1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpssda1_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2634))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2635))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2636))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2637))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2638))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2639))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2640))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2641))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2642))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2643))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2644))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2645))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2646))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2647))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2648))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2649))]
+ ] 2648))]
"CGEN_ENABLE_INSN_P (85)"
"cpssda1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpssda1u_b_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2650))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2651))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2652))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2653))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2654))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2655))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2656))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2657))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2658))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2659))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2660))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2661))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2662))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2663))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2664))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2665))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2666))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2667))]
+ ] 2666))]
"CGEN_ENABLE_INSN_P (86)"
"cpssda1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpssda1u_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2650))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2651))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2652))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2653))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2654))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2655))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2656))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2657))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2658))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2659))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2660))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2661))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2662))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2663))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2664))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2665))]
+ ] 2664))]
"CGEN_ENABLE_INSN_P (87)"
"cpssda1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpssqa1_b_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2666))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2667))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2668))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2669))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2670))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2671))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2672))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2673))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2674))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2675))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2676))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2677))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2678))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2679))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2680))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2681))]
+ ] 2680))]
"CGEN_ENABLE_INSN_P (88)"
"cpssqa1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpssqa1_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2666))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2667))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2668))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2669))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2670))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2671))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2672))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2673))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2674))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2675))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2676))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2677))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2678))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2679))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2680))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2681))]
+ ] 2680))]
"CGEN_ENABLE_INSN_P (89)"
"cpssqa1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpssqa1u_b_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2682))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2683))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2684))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2685))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2686))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2687))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2688))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2689))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2690))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2691))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2692))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2693))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2694))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2695))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2696))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2697))]
+ ] 2696))]
"CGEN_ENABLE_INSN_P (90)"
"cpssqa1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpssqa1u_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2682))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2683))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2684))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2685))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2686))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2687))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2688))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2689))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2690))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2691))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2692))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2693))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2694))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2695))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2696))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2697))]
+ ] 2696))]
"CGEN_ENABLE_INSN_P (91)"
"cpssqa1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadila1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
(match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
] 1000))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1001))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1002))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1003))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1004))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1005))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1006))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1007))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1008))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 1009))]
+ ] 1008))]
"CGEN_ENABLE_INSN_P (92)"
"cpfmadila1.h\\t%0,%1,%2,%3"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadiua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
(match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
] 1010))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1011))
- (set (reg:SI 111)
- (unspec:SI [
+ (set (reg:SI 111)
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1012))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1013))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1014))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1015))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1016))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1017))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1018))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 1019))]
+ ] 1018))]
"CGEN_ENABLE_INSN_P (93)"
"cpfmadiua1.h\\t%0,%1,%2,%3"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadia1_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
(match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
] 1020))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1021))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1022))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1023))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1024))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1025))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1026))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1027))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1028))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1029))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1030))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1031))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1032))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1033))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1034))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1035))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1036))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 1037))]
+ ] 1036))]
"CGEN_ENABLE_INSN_P (94)"
"cpfmadia1.b\\t%0,%1,%2,%3"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadia1u_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
(match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
] 1038))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1039))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1040))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1041))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1042))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1043))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1044))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1045))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1046))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1047))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1048))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1049))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1050))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1051))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1052))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1053))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1054))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 1055))]
+ ] 1054))]
"CGEN_ENABLE_INSN_P (95)"
"cpfmadia1u.b\\t%0,%1,%2,%3"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmulila1_h_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
(match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
] 1056))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1057))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1058))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1059))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1060))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1061))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1062))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 1063))]
+ ] 1062))]
"CGEN_ENABLE_INSN_P (96)"
"cpfmulila1.h\\t%0,%1,%2,%3"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmuliua1_h_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
(match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
] 1064))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1065))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1066))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1067))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1068))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1069))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1070))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 1071))]
+ ] 1070))]
"CGEN_ENABLE_INSN_P (97)"
"cpfmuliua1.h\\t%0,%1,%2,%3"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmulia1_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
(match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
] 1072))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1073))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1074))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1075))
- (set (reg:SI 109)
- (unspec:SI [
+ (set (reg:SI 109)
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1076))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1077))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1078))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1079))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1080))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1081))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1082))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1083))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1084))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1085))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1086))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 1087))]
+ ] 1086))]
"CGEN_ENABLE_INSN_P (98)"
"cpfmulia1.b\\t%0,%1,%2,%3"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmulia1u_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_uint_3a1_immediate" "")
(match_operand:SI 3 "cgen_h_sint_8a1_immediate" "")
] 1088))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1089))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1090))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1091))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1092))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1093))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1094))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1095))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1096))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1097))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1098))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1099))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
] 1100))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1101))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- (match_dup 3)
- ] 1102))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
(match_dup 3)
- ] 1103))]
+ ] 1102))]
"CGEN_ENABLE_INSN_P (99)"
"cpfmulia1u.b\\t%0,%1,%2,%3"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpamadila1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1104))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1105))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1106))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1107))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1108))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1109))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1110))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1111))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1112))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1113))]
+ ] 1112))]
"CGEN_ENABLE_INSN_P (100)"
"cpamadila1.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpamadiua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1114))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1115))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1116))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1117))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1118))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1119))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1120))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1121))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1122))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1123))]
+ ] 1122))]
"CGEN_ENABLE_INSN_P (101)"
"cpamadiua1.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpamadia1_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1124))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1125))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1126))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1127))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1128))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1129))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1130))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1131))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1132))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1133))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1134))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1135))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1136))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1137))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1138))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1139))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1140))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1141))]
+ ] 1140))]
"CGEN_ENABLE_INSN_P (102)"
"cpamadia1.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpamadia1u_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1142))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1143))
- (set (reg:SI 111)
- (unspec:SI [
+ (set (reg:SI 111)
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1144))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1145))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1146))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1147))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1148))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1149))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1150))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1151))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1152))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1153))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1154))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1155))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1156))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1157))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1158))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1159))]
+ ] 1158))]
"CGEN_ENABLE_INSN_P (103)"
"cpamadia1u.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpamulila1_h_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1160))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1161))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1162))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1163))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1164))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1165))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1166))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1167))]
+ ] 1166))]
"CGEN_ENABLE_INSN_P (104)"
"cpamulila1.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpamuliua1_h_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1168))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1169))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1170))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1171))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1172))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1173))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1174))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1175))]
+ ] 1174))]
"CGEN_ENABLE_INSN_P (105)"
"cpamuliua1.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpamulia1_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1176))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1177))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1178))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1179))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1180))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1181))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1182))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1183))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1184))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1185))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1186))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1187))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1188))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1189))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1190))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1191))]
+ ] 1190))]
"CGEN_ENABLE_INSN_P (106)"
"cpamulia1.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpamulia1u_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1192))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1193))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1194))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1195))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1196))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1197))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1198))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1199))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1200))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1201))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1202))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1203))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1204))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1205))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1206))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1207))]
+ ] 1206))]
"CGEN_ENABLE_INSN_P (107)"
"cpamulia1u.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadila1s1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1208))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1209))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1210))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1211))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1212))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1213))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1214))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1215))
(set (reg:SI 104)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1216))
- (set (reg:SI 117)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1217))]
+ ] 1216))]
"CGEN_ENABLE_INSN_P (108)"
"cpfmadila1s1.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadiua1s1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1218))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1219))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1220))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1221))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1222))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1223))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1224))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1225))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1226))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1227))]
+ ] 1226))]
"CGEN_ENABLE_INSN_P (109)"
"cpfmadiua1s1.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadia1s1_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1228))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1229))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1230))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1231))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1232))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1233))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1234))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1235))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1236))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1237))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1238))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1239))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1240))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1241))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1242))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1243))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1244))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1245))]
+ ] 1244))]
"CGEN_ENABLE_INSN_P (110)"
"cpfmadia1s1.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadia1s1u_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1246))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1247))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1248))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1249))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1250))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1251))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1252))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1253))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1254))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1255))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1256))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1257))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1258))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1259))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1260))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1261))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1262))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1263))]
+ ] 1262))]
"CGEN_ENABLE_INSN_P (111)"
"cpfmadia1s1u.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmulila1s1_h_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1264))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1265))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1266))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1267))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1268))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1269))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1270))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1271))]
+ ] 1270))]
"CGEN_ENABLE_INSN_P (112)"
"cpfmulila1s1.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmuliua1s1_h_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1272))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1273))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1274))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1275))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1276))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1277))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1278))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1279))]
+ ] 1278))]
"CGEN_ENABLE_INSN_P (113)"
"cpfmuliua1s1.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmulia1s1_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1280))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1281))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1282))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1283))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1284))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1285))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1286))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1287))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1288))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1289))
- (set (reg:SI 106)
- (unspec:SI [
+ (set (reg:SI 106)
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1290))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1291))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1292))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1293))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1294))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1295))]
+ ] 1294))]
"CGEN_ENABLE_INSN_P (114)"
"cpfmulia1s1.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmulia1s1u_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1296))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1297))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1298))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1299))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1300))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1301))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1302))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1303))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1304))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1305))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1306))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1307))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1308))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1309))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1310))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1311))]
+ ] 1310))]
"CGEN_ENABLE_INSN_P (115)"
"cpfmulia1s1u.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadila1s0_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1312))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1313))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1314))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1315))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1316))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1317))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1318))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1319))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1320))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1321))]
+ ] 1320))]
"CGEN_ENABLE_INSN_P (116)"
"cpfmadila1s0.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadiua1s0_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1322))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1323))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1324))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1325))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1326))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1327))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1328))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1329))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1330))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1331))]
+ ] 1330))]
"CGEN_ENABLE_INSN_P (117)"
"cpfmadiua1s0.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadia1s0_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1332))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1333))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1334))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1335))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1336))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1337))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1338))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1339))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1340))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1341))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1342))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1343))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1344))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1345))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1346))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1347))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1348))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1349))]
+ ] 1348))]
"CGEN_ENABLE_INSN_P (118)"
"cpfmadia1s0.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmadia1s0u_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1350))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1351))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1352))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1353))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1354))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1355))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1356))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1357))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1358))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1359))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1360))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1361))
- (set (reg:SI 106)
- (unspec:SI [
+ (set (reg:SI 106)
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1362))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1363))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1364))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1365))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1366))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1367))]
+ ] 1366))]
"CGEN_ENABLE_INSN_P (119)"
"cpfmadia1s0u.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmulila1s0_h_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1368))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1369))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1370))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1371))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1372))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1373))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1374))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1375))]
+ ] 1374))]
"CGEN_ENABLE_INSN_P (120)"
"cpfmulila1s0.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmuliua1s0_h_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1376))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1377))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1378))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1379))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1380))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1381))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1382))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1383))]
+ ] 1382))]
"CGEN_ENABLE_INSN_P (121)"
"cpfmuliua1s0.h\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmulia1s0_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1384))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1385))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1386))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1387))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1388))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1389))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1390))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1391))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1392))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1393))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1394))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1395))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1396))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1397))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1398))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1399))]
+ ] 1398))]
"CGEN_ENABLE_INSN_P (122)"
"cpfmulia1s0.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfmulia1s0u_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
(match_operand:SI 2 "cgen_h_sint_8a1_immediate" "")
] 1400))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1401))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1402))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1403))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1404))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1405))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1406))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1407))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1408))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1409))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1410))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1411))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
] 1412))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1413))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- (match_dup 2)
- ] 1414))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
(match_dup 2)
- ] 1415))]
+ ] 1414))]
"CGEN_ENABLE_INSN_P (123)"
"cpfmulia1s0u.b\\t%0,%1,%2"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsllia1_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
] 2698))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2699))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2700))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2701))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2702))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2703))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2704))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2705))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2706))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2707))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2708))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2709))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2710))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2711))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2712))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2713))]
+ ] 2712))]
"CGEN_ENABLE_INSN_P (124)"
"cpsllia1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsllia1_1_p1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
] 2698))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2699))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2700))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2701))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2702))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2703))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2704))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2705))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2706))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2707))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2708))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2709))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2710))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2711))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2712))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2713))]
+ ] 2712))]
"CGEN_ENABLE_INSN_P (125)"
"cpsllia1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsraia1_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
] 2714))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2715))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2716))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2717))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2718))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2719))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2720))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2721))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2722))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2723))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2724))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2725))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2726))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2727))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2728))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2729))]
+ ] 2728))]
"CGEN_ENABLE_INSN_P (126)"
"cpsraia1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsraia1_1_p1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
] 2714))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2715))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2716))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2717))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2718))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2719))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2720))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2721))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2722))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2723))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2724))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2725))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2726))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2727))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2728))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2729))]
+ ] 2728))]
"CGEN_ENABLE_INSN_P (127)"
"cpsraia1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsrlia1_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
] 2730))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2731))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2732))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2733))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2734))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2735))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2736))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2737))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2738))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2739))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2740))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2741))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2742))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2743))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2744))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2745))]
+ ] 2744))]
"CGEN_ENABLE_INSN_P (128)"
"cpsrlia1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsrlia1_1_p1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
] 2730))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2731))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2732))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2733))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2734))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2735))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2736))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2737))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2738))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2739))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2740))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2741))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2742))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2743))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2744))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2745))]
+ ] 2744))]
"CGEN_ENABLE_INSN_P (129)"
"cpsrlia1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpslla1_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
] 2746))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2747))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2748))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2749))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2750))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2751))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2752))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2753))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2754))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2755))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2756))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2757))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2758))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2759))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2760))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2761))]
+ ] 2760))]
"CGEN_ENABLE_INSN_P (130)"
"cpslla1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpslla1_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
] 2746))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2747))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2748))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2749))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2750))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2751))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2752))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2753))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2754))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2755))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2756))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2757))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2758))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2759))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2760))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2761))]
+ ] 2760))]
"CGEN_ENABLE_INSN_P (131)"
"cpslla1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsraa1_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
] 2762))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2763))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2764))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2765))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2766))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2767))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2768))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2769))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2770))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2771))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2772))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2773))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2774))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2775))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2776))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2777))]
+ ] 2776))]
"CGEN_ENABLE_INSN_P (132)"
"cpsraa1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsraa1_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
] 2762))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2763))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2764))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2765))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2766))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2767))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2768))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2769))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2770))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2771))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2772))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2773))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2774))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2775))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2776))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2777))]
+ ] 2776))]
"CGEN_ENABLE_INSN_P (133)"
"cpsraa1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsrla1_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
] 2778))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2779))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2780))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2781))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2782))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2783))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2784))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2785))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2786))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2787))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2788))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2789))
(set (reg:SI 105)
- (unspec:SI [
- (match_dup 0)
- ] 2790))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2791))
- (set (reg:SI 104)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2792))
- (set (reg:SI 117)
- (unspec:SI [
+ ] 2790))
+ (set (reg:SI 104)
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2793))]
+ ] 2792))]
"CGEN_ENABLE_INSN_P (134)"
"cpsrla1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsrla1_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
] 2778))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- ] 2779))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2780))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- ] 2781))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2782))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- ] 2783))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2784))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- ] 2785))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2786))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- ] 2787))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2788))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- ] 2789))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 2790))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- ] 2791))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- ] 2792))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 2793))]
+ ] 2792))]
"CGEN_ENABLE_INSN_P (135)"
"cpsrla1\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaccpa1_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1448))
- (set (reg:SI 118)
- (unspec:SI [
- (const_int 0)
- ] 1449))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1450))
- (set (reg:SI 119)
- (unspec:SI [
- (const_int 0)
- ] 1451))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1452))
- (set (reg:SI 120)
- (unspec:SI [
- (const_int 0)
- ] 1453))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1454))
- (set (reg:SI 121)
- (unspec:SI [
- (const_int 0)
- ] 1455))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1456))
- (set (reg:SI 114)
- (unspec:SI [
- (const_int 0)
- ] 1457))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1458))
- (set (reg:SI 115)
- (unspec:SI [
- (const_int 0)
- ] 1459))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1460))
- (set (reg:SI 116)
- (unspec:SI [
- (const_int 0)
- ] 1461))
(set (reg:SI 104)
- (unspec:SI [
- (const_int 0)
- ] 1462))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
- ] 1463))]
+ ] 1462))]
"CGEN_ENABLE_INSN_P (137)"
"cpaccpa1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpacsuma1_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1464))
- (set (reg:SI 113)
- (unspec:SI [
- (const_int 0)
- ] 1465))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1466))
- (set (reg:SI 118)
- (unspec:SI [
- (const_int 0)
- ] 1467))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1468))
- (set (reg:SI 119)
- (unspec:SI [
- (const_int 0)
- ] 1469))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1470))
- (set (reg:SI 120)
- (unspec:SI [
- (const_int 0)
- ] 1471))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1472))
- (set (reg:SI 121)
- (unspec:SI [
- (const_int 0)
- ] 1473))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1474))
- (set (reg:SI 114)
- (unspec:SI [
- (const_int 0)
- ] 1475))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1476))
- (set (reg:SI 115)
- (unspec:SI [
- (const_int 0)
- ] 1477))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1478))
- (set (reg:SI 116)
- (unspec:SI [
- (const_int 0)
- ] 1479))
(set (reg:SI 104)
- (unspec:SI [
- (const_int 0)
- ] 1480))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
- ] 1481))]
+ ] 1480))]
"CGEN_ENABLE_INSN_P (138)"
"cpacsuma1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsetla1_w_C3"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2824))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2825))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2826))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2827))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2828))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2829))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2830))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2831))]
+ ] 2830))]
"CGEN_ENABLE_INSN_P (169)"
"cpsetla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsetla1_w_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2824))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2825))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2826))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2827))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2828))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2829))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2830))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2831))]
+ ] 2830))]
"CGEN_ENABLE_INSN_P (170)"
"cpsetla1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsetua1_w_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2832))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2833))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2834))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2835))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2836))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2837))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2838))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2839))]
+ ] 2838))]
"CGEN_ENABLE_INSN_P (171)"
"cpsetua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsetua1_w_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2832))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2833))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2834))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2835))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2836))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2837))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2838))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2839))]
+ ] 2838))]
"CGEN_ENABLE_INSN_P (172)"
"cpsetua1.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpseta1_h_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2840))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2841))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2842))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2843))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2844))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2845))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2846))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2847))
(set (reg:SI 107)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2848))
- (set (reg:SI 114)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2849))
+ ] 2848))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2850))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2851))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2852))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2853))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2854))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2855))]
+ ] 2854))]
"CGEN_ENABLE_INSN_P (173)"
"cpseta1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpseta1_h_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2840))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2841))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2842))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2843))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2844))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2845))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2846))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2847))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2848))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2849))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2850))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2851))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2852))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2853))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2854))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2855))]
+ ] 2854))]
"CGEN_ENABLE_INSN_P (174)"
"cpseta1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsadla1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2856))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2857))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2858))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2859))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2860))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2861))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2862))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2863))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2864))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2865))]
+ ] 2864))]
"CGEN_ENABLE_INSN_P (175)"
"cpsadla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsadla1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2856))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2857))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2858))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2859))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2860))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2861))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2862))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2863))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2864))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2865))]
+ ] 2864))]
"CGEN_ENABLE_INSN_P (176)"
"cpsadla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsadua1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2866))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2867))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2868))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2869))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2870))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2871))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2872))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2873))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2874))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2875))]
+ ] 2874))]
"CGEN_ENABLE_INSN_P (177)"
"cpsadua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsadua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2866))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2867))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2868))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2869))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2870))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2871))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2872))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2873))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2874))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2875))]
+ ] 2874))]
"CGEN_ENABLE_INSN_P (178)"
"cpsadua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsada1_b_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2876))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2877))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2878))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2879))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2880))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2881))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2882))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2883))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2884))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2885))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2886))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2887))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2888))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2889))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2890))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2891))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2892))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2893))]
+ ] 2892))]
"CGEN_ENABLE_INSN_P (179)"
"cpsada1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsada1_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2876))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2877))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2878))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2879))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2880))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2881))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2882))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2883))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2884))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2885))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2886))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2887))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2888))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2889))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2890))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2891))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2892))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2893))]
+ ] 2892))]
"CGEN_ENABLE_INSN_P (180)"
"cpsada1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsada1u_b_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2894))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2895))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2896))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2897))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2898))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2899))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2900))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2901))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2902))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2903))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2904))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2905))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2906))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2907))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2908))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2909))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2910))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2911))]
+ ] 2910))]
"CGEN_ENABLE_INSN_P (181)"
"cpsada1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsada1u_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2894))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2895))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2896))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2897))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2898))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2899))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2900))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2901))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2902))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2903))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2904))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2905))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2906))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2907))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2908))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2909))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2910))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2911))]
+ ] 2910))]
"CGEN_ENABLE_INSN_P (182)"
"cpsada1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsla1_h_C3"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2912))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2913))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2914))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2915))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2916))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2917))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2918))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2919))]
+ ] 2918))]
"CGEN_ENABLE_INSN_P (183)"
"cpabsla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsla1_h_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2912))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2913))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2914))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2915))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2916))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2917))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2918))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2919))]
+ ] 2918))]
"CGEN_ENABLE_INSN_P (184)"
"cpabsla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsua1_h_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2920))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2921))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2922))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2923))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2924))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2925))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2926))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2927))]
+ ] 2926))]
"CGEN_ENABLE_INSN_P (185)"
"cpabsua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsua1_h_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2920))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2921))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2922))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2923))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2924))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2925))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2926))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2927))]
+ ] 2926))]
"CGEN_ENABLE_INSN_P (186)"
"cpabsua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsa1_b_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2928))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2929))
(set (reg:SI 110)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2930))
- (set (reg:SI 119)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2931))
+ ] 2930))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2932))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2933))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2934))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2935))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2936))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2937))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2938))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2939))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2940))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2941))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2942))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2943))]
+ ] 2942))]
"CGEN_ENABLE_INSN_P (187)"
"cpabsa1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsa1_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2928))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2929))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2930))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2931))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2932))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2933))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2934))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2935))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2936))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2937))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2938))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2939))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2940))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2941))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2942))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2943))]
+ ] 2942))]
"CGEN_ENABLE_INSN_P (188)"
"cpabsa1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsa1u_b_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2944))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2945))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2946))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2947))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2948))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2949))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2950))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2951))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2952))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2953))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2954))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2955))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2956))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2957))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2958))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2959))]
+ ] 2958))]
"CGEN_ENABLE_INSN_P (189)"
"cpabsa1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsa1u_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2944))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2945))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2946))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2947))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2948))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2949))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2950))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2951))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2952))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2953))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2954))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2955))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2956))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2957))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2958))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2959))]
+ ] 2958))]
"CGEN_ENABLE_INSN_P (190)"
"cpabsa1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubacla1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2960))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2961))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2962))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2963))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2964))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2965))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2966))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2967))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2968))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2969))]
+ ] 2968))]
"CGEN_ENABLE_INSN_P (191)"
"cpsubacla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubacla1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2960))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2961))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2962))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2963))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2964))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2965))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2966))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2967))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2968))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2969))]
+ ] 2968))]
"CGEN_ENABLE_INSN_P (192)"
"cpsubacla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubacua1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2970))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2971))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2972))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2973))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2974))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2975))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2976))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2977))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2978))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2979))]
+ ] 2978))]
"CGEN_ENABLE_INSN_P (193)"
"cpsubacua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubacua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2970))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2971))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2972))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2973))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2974))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2975))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2976))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2977))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2978))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2979))]
+ ] 2978))]
"CGEN_ENABLE_INSN_P (194)"
"cpsubacua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubaca1_b_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2980))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2981))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2982))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2983))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2984))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2985))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2986))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2987))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2988))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2989))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2990))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2991))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2992))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2993))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2994))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2995))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2996))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2997))]
+ ] 2996))]
"CGEN_ENABLE_INSN_P (195)"
"cpsubaca1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubaca1_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2980))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2981))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2982))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2983))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2984))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2985))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2986))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2987))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2988))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2989))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2990))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2991))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2992))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2993))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2994))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2995))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2996))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2997))]
+ ] 2996))]
"CGEN_ENABLE_INSN_P (196)"
"cpsubaca1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubaca1u_b_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2998))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2999))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3000))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3001))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3002))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3003))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3004))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3005))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3006))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3007))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3008))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3009))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3010))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3011))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3012))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3013))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3014))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3015))]
+ ] 3014))]
"CGEN_ENABLE_INSN_P (197)"
"cpsubaca1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubaca1u_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2998))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2999))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3000))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3001))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3002))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3003))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3004))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3005))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3006))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3007))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3008))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3009))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3010))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3011))
(set (reg:SI 105)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3012))
- (set (reg:SI 116)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3013))
+ ] 3012))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3014))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3015))]
+ ] 3014))]
"CGEN_ENABLE_INSN_P (198)"
"cpsubaca1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubla1_h_C3"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3016))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3017))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3018))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3019))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3020))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3021))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3022))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3023))]
+ ] 3022))]
"CGEN_ENABLE_INSN_P (199)"
"cpsubla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubla1_h_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3016))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3017))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3018))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3019))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3020))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3021))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3022))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3023))]
+ ] 3022))]
"CGEN_ENABLE_INSN_P (200)"
"cpsubla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubua1_h_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3024))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3025))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3026))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3027))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3028))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3029))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3030))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3031))]
+ ] 3030))]
"CGEN_ENABLE_INSN_P (201)"
"cpsubua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubua1_h_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3024))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3025))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3026))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3027))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3028))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3029))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3030))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3031))]
+ ] 3030))]
"CGEN_ENABLE_INSN_P (202)"
"cpsubua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsuba1_b_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3032))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3033))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3034))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3035))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3036))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3037))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3038))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3039))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3040))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3041))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3042))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3043))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3044))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3045))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3046))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3047))]
+ ] 3046))]
"CGEN_ENABLE_INSN_P (203)"
"cpsuba1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsuba1_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3032))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3033))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3034))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3035))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3036))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3037))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3038))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3039))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3040))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3041))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3042))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3043))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3044))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3045))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3046))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3047))]
+ ] 3046))]
"CGEN_ENABLE_INSN_P (204)"
"cpsuba1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsuba1u_b_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3048))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3049))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3050))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3051))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3052))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3053))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3054))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3055))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3056))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3057))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3058))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3059))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3060))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3061))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3062))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3063))]
+ ] 3062))]
"CGEN_ENABLE_INSN_P (205)"
"cpsuba1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsuba1u_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
- (match_operand:DI 1 "general_operand" "x")
- ] 3048))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3049))
+ (match_operand:DI 1 "general_operand" "x")
+ ] 3048))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3050))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3051))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3052))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3053))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3054))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3055))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3056))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3057))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3058))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3059))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3060))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3061))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3062))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3063))]
+ ] 3062))]
"CGEN_ENABLE_INSN_P (206)"
"cpsuba1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddacla1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3064))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3065))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3066))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3067))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3068))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3069))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3070))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3071))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3072))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3073))]
+ ] 3072))]
"CGEN_ENABLE_INSN_P (207)"
"cpaddacla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddacla1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3064))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3065))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3066))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3067))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3068))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3069))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3070))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3071))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3072))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3073))]
+ ] 3072))]
"CGEN_ENABLE_INSN_P (208)"
"cpaddacla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddacua1_h_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3074))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3075))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3076))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3077))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3078))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3079))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3080))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3081))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3082))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3083))]
+ ] 3082))]
"CGEN_ENABLE_INSN_P (209)"
"cpaddacua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddacua1_h_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3074))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3075))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3076))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3077))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3078))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3079))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3080))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3081))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3082))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3083))]
+ ] 3082))]
"CGEN_ENABLE_INSN_P (210)"
"cpaddacua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddaca1_b_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3084))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3085))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3086))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3087))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3088))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3089))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3090))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3091))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3092))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3093))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3094))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3095))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3096))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3097))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3098))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3099))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3100))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3101))]
+ ] 3100))]
"CGEN_ENABLE_INSN_P (211)"
"cpaddaca1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddaca1_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3084))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3085))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3086))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3087))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3088))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3089))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3090))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3091))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3092))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3093))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3094))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3095))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3096))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3097))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3098))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3099))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3100))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3101))]
+ ] 3100))]
"CGEN_ENABLE_INSN_P (212)"
"cpaddaca1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddaca1u_b_C3"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3102))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3103))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3104))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3105))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3106))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3107))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3108))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3109))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3110))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3111))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3112))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3113))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3114))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3115))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3116))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3117))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3118))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3119))]
+ ] 3118))]
"CGEN_ENABLE_INSN_P (213)"
"cpaddaca1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddaca1u_b_P1"
[(set (reg:SI 87)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3102))
- (set (reg:SI 113)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3103))
(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3104))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3105))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3106))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3107))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3108))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3109))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3110))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3111))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3112))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3113))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3114))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3115))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3116))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3117))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3118))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3119))]
+ ] 3118))]
"CGEN_ENABLE_INSN_P (214)"
"cpaddaca1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddla1_h_C3"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3120))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3121))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3122))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3123))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3124))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3125))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3126))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3127))]
+ ] 3126))]
"CGEN_ENABLE_INSN_P (215)"
"cpaddla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddla1_h_P1"
[(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3120))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3121))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3122))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3123))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3124))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3125))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3126))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3127))]
+ ] 3126))]
"CGEN_ENABLE_INSN_P (216)"
"cpaddla1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddua1_h_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3128))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3129))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3130))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3131))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3132))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3133))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3134))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3135))]
+ ] 3134))]
"CGEN_ENABLE_INSN_P (217)"
"cpaddua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddua1_h_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3128))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3129))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3130))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3131))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3132))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3133))
(set (reg:SI 108)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3134))
- (set (reg:SI 121)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3135))]
+ ] 3134))]
"CGEN_ENABLE_INSN_P (218)"
"cpaddua1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpadda1_b_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3136))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3137))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3138))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3139))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3140))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3141))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3142))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3143))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3144))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3145))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3146))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3147))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3148))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3149))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3150))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3151))]
+ ] 3150))]
"CGEN_ENABLE_INSN_P (219)"
"cpadda1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpadda1_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3136))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3137))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3138))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3139))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3140))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3141))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3142))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3143))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3144))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3145))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3146))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3147))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3148))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3149))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3150))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3151))]
+ ] 3150))]
"CGEN_ENABLE_INSN_P (220)"
"cpadda1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpadda1u_b_C3"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3152))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3153))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3154))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3155))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3156))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3157))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3158))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3159))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3160))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3161))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3162))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3163))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3164))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3165))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3166))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3167))]
+ ] 3166))]
"CGEN_ENABLE_INSN_P (221)"
"cpadda1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpadda1u_b_P1"
[(set (reg:SI 111)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3152))
- (set (reg:SI 118)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3153))
(set (reg:SI 110)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3154))
- (set (reg:SI 119)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3155))
(set (reg:SI 109)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3156))
- (set (reg:SI 120)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3157))
(set (reg:SI 108)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3158))
- (set (reg:SI 121)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3159))
(set (reg:SI 107)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3160))
- (set (reg:SI 114)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3161))
(set (reg:SI 106)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3162))
- (set (reg:SI 115)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3163))
(set (reg:SI 105)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 3164))
- (set (reg:SI 116)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3165))
(set (reg:SI 104)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3166))
- (set (reg:SI 117)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 3167))]
+ ] 3166))]
"CGEN_ENABLE_INSN_P (222)"
"cpadda1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(match_dup 1)
(match_dup 2)
] 3450))
- (set (reg:SI 122)
+ (set (reg:SI 113)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_dup 1)
(match_dup 2)
] 3450))
- (set (reg:SI 122)
+ (set (reg:SI 113)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_dup 1)
(match_dup 2)
] 3454))
- (set (reg:SI 122)
+ (set (reg:SI 113)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_dup 1)
(match_dup 2)
] 3454))
- (set (reg:SI 122)
+ (set (reg:SI 113)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3218))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3220))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3222))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3224))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3226))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3228))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3230))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3232))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3234))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3236))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3238))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3240))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3242))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3244))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3246))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3248))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3250))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3252))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3254))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3256))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3258))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3260))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3262))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3264))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3266))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3268))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3270))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3272))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3274))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3276))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3278))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 3280))
- (set (reg:SI 123)
+ (set (reg:SI 114)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(define_insn "cgen_intrinsic_cpfacla0s1_h_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1484))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1485))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1486))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1487))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1488))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1489))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1490))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1491))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1492))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1493))]
+ ] 1492))]
"CGEN_ENABLE_INSN_P (474)"
"cpfacla0s1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfacua0s1_h_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1494))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1495))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1496))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1497))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1498))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1499))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1500))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1501))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1502))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1503))]
+ ] 1502))]
"CGEN_ENABLE_INSN_P (475)"
"cpfacua0s1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfaca0s1_b_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1504))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1505))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1506))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1507))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1508))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1509))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1510))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1511))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1512))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1513))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1514))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1515))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1516))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1517))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1518))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1519))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1520))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1521))]
+ ] 1520))]
"CGEN_ENABLE_INSN_P (476)"
"cpfaca0s1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfaca0s1u_b_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1522))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1523))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1524))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1525))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1526))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1527))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1528))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1529))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1530))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1531))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1532))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1533))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1534))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1535))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1536))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1537))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1538))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1539))]
+ ] 1538))]
"CGEN_ENABLE_INSN_P (477)"
"cpfaca0s1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfsftbla0s1_h_P0S"
[(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1540))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1541))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1542))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1543))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1544))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1545))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1546))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1547))]
+ ] 1546))]
"CGEN_ENABLE_INSN_P (478)"
"cpfsftbla0s1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfsftbua0s1_h_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1548))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1549))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1550))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1551))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1552))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1553))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1554))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1555))]
+ ] 1554))]
"CGEN_ENABLE_INSN_P (479)"
"cpfsftbua0s1.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfsftba0s1_b_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1556))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1557))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1558))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1559))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1560))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1561))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1562))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1563))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1564))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1565))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1566))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1567))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1568))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1569))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1570))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1571))]
+ ] 1570))]
"CGEN_ENABLE_INSN_P (480)"
"cpfsftba0s1.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfsftba0s1u_b_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1572))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1573))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1574))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1575))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1576))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1577))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1578))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1579))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1580))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1581))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1582))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1583))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1584))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1585))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1586))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1587))]
+ ] 1586))]
"CGEN_ENABLE_INSN_P (481)"
"cpfsftba0s1u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfacla0s0_h_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1588))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1589))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1590))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1591))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1592))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1593))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1594))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1595))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1596))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1597))]
+ ] 1596))]
"CGEN_ENABLE_INSN_P (482)"
"cpfacla0s0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfacua0s0_h_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1598))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1599))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1600))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1601))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1602))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1603))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1604))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1605))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1606))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1607))]
+ ] 1606))]
"CGEN_ENABLE_INSN_P (483)"
"cpfacua0s0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfaca0s0_b_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 1608))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1609))
+ ] 1608))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1610))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1611))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1612))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1613))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1614))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1615))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1616))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1617))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1618))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1619))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1620))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1621))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1622))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1623))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1624))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1625))]
+ ] 1624))]
"CGEN_ENABLE_INSN_P (484)"
"cpfaca0s0.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfaca0s0u_b_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1626))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1627))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1628))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1629))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1630))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1631))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1632))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1633))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1634))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1635))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1636))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1637))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1638))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1639))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1640))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1641))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1642))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1643))]
+ ] 1642))]
"CGEN_ENABLE_INSN_P (485)"
"cpfaca0s0u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfsftbla0s0_h_P0S"
[(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1644))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1645))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1646))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1647))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1648))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1649))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1650))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1651))]
+ ] 1650))]
"CGEN_ENABLE_INSN_P (486)"
"cpfsftbla0s0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfsftbua0s0_h_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1652))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1653))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1654))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1655))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1656))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1657))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1658))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1659))]
+ ] 1658))]
"CGEN_ENABLE_INSN_P (487)"
"cpfsftbua0s0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfsftba0s0_b_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1660))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1661))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1662))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1663))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1664))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1665))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1666))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1667))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1668))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1669))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1670))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1671))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1672))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1673))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1674))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1675))]
+ ] 1674))]
"CGEN_ENABLE_INSN_P (488)"
"cpfsftba0s0.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpfsftba0s0u_b_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1676))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1677))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1678))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1679))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1680))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1681))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1682))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1683))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1684))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1685))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1686))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1687))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1688))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1689))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1690))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1691))]
+ ] 1690))]
"CGEN_ENABLE_INSN_P (489)"
"cpfsftba0s0u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsllia0_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
] 1692))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- ] 1693))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1694))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- ] 1695))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1696))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- ] 1697))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1698))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- ] 1699))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1700))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- ] 1701))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1702))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- ] 1703))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1704))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- ] 1705))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- ] 1706))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 1707))]
+ ] 1706))]
"CGEN_ENABLE_INSN_P (490)"
"cpsllia0\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsraia0_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
] 1708))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- ] 1709))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1710))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- ] 1711))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1712))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- ] 1713))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1714))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- ] 1715))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1716))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- ] 1717))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1718))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- ] 1719))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1720))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- ] 1721))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- ] 1722))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 1723))]
+ ] 1722))]
"CGEN_ENABLE_INSN_P (491)"
"cpsraia0\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsrlia0_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:SI 0 "cgen_h_uint_5a1_immediate" "")
] 1724))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- ] 1725))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1726))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- ] 1727))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1728))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- ] 1729))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1730))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- ] 1731))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1732))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- ] 1733))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1734))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- ] 1735))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1736))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- ] 1737))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- ] 1738))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 1739))]
+ ] 1738))]
"CGEN_ENABLE_INSN_P (492)"
"cpsrlia0\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpslla0_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
] 1740))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- ] 1741))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1742))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- ] 1743))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1744))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- ] 1745))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1746))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- ] 1747))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1748))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- ] 1749))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1750))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- ] 1751))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1752))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- ] 1753))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- ] 1754))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 1755))]
+ ] 1754))]
"CGEN_ENABLE_INSN_P (493)"
"cpslla0\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsraa0_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
] 1756))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- ] 1757))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1758))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- ] 1759))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1760))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- ] 1761))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1762))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- ] 1763))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1764))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- ] 1765))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1766))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- ] 1767))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1768))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- ] 1769))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- ] 1770))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 1771))]
+ ] 1770))]
"CGEN_ENABLE_INSN_P (494)"
"cpsraa0\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsrla0_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
] 1772))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- ] 1773))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1774))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- ] 1775))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1776))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- ] 1777))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1778))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- ] 1779))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1780))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- ] 1781))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1782))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- ] 1783))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
] 1784))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- ] 1785))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- ] 1786))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
- ] 1787))]
+ ] 1786))]
"CGEN_ENABLE_INSN_P (495)"
"cpsrla0\\t%0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaccpa0_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1788))
- (set (reg:SI 129)
- (unspec:SI [
- (const_int 0)
- ] 1789))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1790))
- (set (reg:SI 130)
- (unspec:SI [
- (const_int 0)
- ] 1791))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1792))
- (set (reg:SI 131)
- (unspec:SI [
- (const_int 0)
- ] 1793))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1794))
- (set (reg:SI 132)
- (unspec:SI [
- (const_int 0)
- ] 1795))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1796))
- (set (reg:SI 125)
- (unspec:SI [
- (const_int 0)
- ] 1797))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1798))
- (set (reg:SI 126)
- (unspec:SI [
- (const_int 0)
- ] 1799))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1800))
- (set (reg:SI 127)
- (unspec:SI [
- (const_int 0)
- ] 1801))
(set (reg:SI 96)
- (unspec:SI [
- (const_int 0)
- ] 1802))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
- ] 1803))]
+ ] 1802))]
"CGEN_ENABLE_INSN_P (496)"
"cpaccpa0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpacsuma0_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1804))
- (set (reg:SI 124)
- (unspec:SI [
- (const_int 0)
- ] 1805))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1806))
- (set (reg:SI 129)
- (unspec:SI [
- (const_int 0)
- ] 1807))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1808))
- (set (reg:SI 130)
- (unspec:SI [
- (const_int 0)
- ] 1809))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1810))
- (set (reg:SI 131)
- (unspec:SI [
- (const_int 0)
- ] 1811))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1812))
- (set (reg:SI 132)
- (unspec:SI [
- (const_int 0)
- ] 1813))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1814))
- (set (reg:SI 125)
- (unspec:SI [
- (const_int 0)
- ] 1815))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1816))
- (set (reg:SI 126)
- (unspec:SI [
- (const_int 0)
- ] 1817))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
] 1818))
- (set (reg:SI 127)
- (unspec:SI [
- (const_int 0)
- ] 1819))
(set (reg:SI 96)
- (unspec:SI [
- (const_int 0)
- ] 1820))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(const_int 0)
- ] 1821))]
+ ] 1820))]
"CGEN_ENABLE_INSN_P (497)"
"cpacsuma0"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsetla0_w_P0S"
[(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1852))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1853))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1854))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1855))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1856))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1857))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1858))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1859))]
+ ] 1858))]
"CGEN_ENABLE_INSN_P (513)"
"cpsetla0.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsetua0_w_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1860))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1861))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1862))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1863))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1864))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1865))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1866))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1867))]
+ ] 1866))]
"CGEN_ENABLE_INSN_P (514)"
"cpsetua0.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpseta0_h_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 1868))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1869))
+ ] 1868))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1870))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1871))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1872))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1873))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1874))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1875))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1876))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1877))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1878))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1879))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1880))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1881))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1882))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1883))]
+ ] 1882))]
"CGEN_ENABLE_INSN_P (515)"
"cpseta0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsadla0_h_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1884))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1885))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1886))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1887))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1888))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1889))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1890))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1891))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1892))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1893))]
+ ] 1892))]
"CGEN_ENABLE_INSN_P (516)"
"cpsadla0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsadua0_h_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1894))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1895))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1896))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1897))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1898))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1899))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1900))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1901))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1902))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1903))]
+ ] 1902))]
"CGEN_ENABLE_INSN_P (517)"
"cpsadua0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsada0_b_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1904))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1905))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1906))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1907))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1908))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1909))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1910))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1911))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1912))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1913))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1914))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1915))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1916))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1917))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1918))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1919))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1920))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1921))]
+ ] 1920))]
"CGEN_ENABLE_INSN_P (518)"
"cpsada0.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsada0u_b_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1922))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1923))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1924))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1925))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1926))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1927))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1928))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1929))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1930))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1931))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1932))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1933))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1934))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1935))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1936))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1937))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1938))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1939))]
+ ] 1938))]
"CGEN_ENABLE_INSN_P (519)"
"cpsada0u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsla0_h_P0S"
[(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1940))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1941))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1942))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1943))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1944))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1945))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1946))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1947))]
+ ] 1946))]
"CGEN_ENABLE_INSN_P (520)"
"cpabsla0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsua0_h_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1948))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1949))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1950))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1951))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1952))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1953))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1954))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1955))]
+ ] 1954))]
"CGEN_ENABLE_INSN_P (521)"
"cpabsua0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsa0_b_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1956))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1957))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1958))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1959))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1960))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1961))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1962))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1963))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1964))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1965))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1966))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1967))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1968))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1969))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1970))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1971))]
+ ] 1970))]
"CGEN_ENABLE_INSN_P (522)"
"cpabsa0.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpabsa0u_b_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1972))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1973))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1974))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1975))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1976))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1977))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1978))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1979))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1980))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1981))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1982))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1983))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1984))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1985))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1986))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1987))]
+ ] 1986))]
"CGEN_ENABLE_INSN_P (523)"
"cpabsa0u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubacla0_h_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1988))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1989))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1990))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1991))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1992))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1993))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 1994))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1995))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1996))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 1997))]
+ ] 1996))]
"CGEN_ENABLE_INSN_P (524)"
"cpsubacla0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubacua0_h_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 1998))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 1999))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2000))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2001))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2002))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2003))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2004))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2005))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2006))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2007))]
+ ] 2006))]
"CGEN_ENABLE_INSN_P (525)"
"cpsubacua0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubaca0_b_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2008))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2009))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2010))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2011))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2012))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2013))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2014))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2015))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2016))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2017))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2018))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2019))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2020))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2021))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2022))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2023))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2024))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2025))]
+ ] 2024))]
"CGEN_ENABLE_INSN_P (526)"
"cpsubaca0.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubaca0u_b_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2026))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2027))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2028))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2029))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2030))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2031))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2032))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2033))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2034))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2035))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2036))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2037))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2038))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2039))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2040))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2041))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2042))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2043))]
+ ] 2042))]
"CGEN_ENABLE_INSN_P (527)"
"cpsubaca0u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubla0_h_P0S"
[(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2044))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2045))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2046))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2047))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2048))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2049))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2050))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2051))]
+ ] 2050))]
"CGEN_ENABLE_INSN_P (528)"
"cpsubla0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsubua0_h_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2052))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2053))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2054))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2055))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2056))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2057))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2058))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2059))]
+ ] 2058))]
"CGEN_ENABLE_INSN_P (529)"
"cpsubua0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsuba0_b_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2060))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2061))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2062))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2063))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2064))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2065))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2066))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2067))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2068))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2069))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2070))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2071))
(set (reg:SI 97)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2072))
- (set (reg:SI 127)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2073))
+ ] 2072))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2074))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2075))]
+ ] 2074))]
"CGEN_ENABLE_INSN_P (530)"
"cpsuba0.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpsuba0u_b_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2076))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2077))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2078))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2079))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2080))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2081))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2082))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2083))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2084))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2085))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2086))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2087))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2088))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2089))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2090))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2091))]
+ ] 2090))]
"CGEN_ENABLE_INSN_P (531)"
"cpsuba0u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddacla0_h_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2092))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2093))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2094))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2095))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2096))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2097))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2098))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2099))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2100))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2101))]
+ ] 2100))]
"CGEN_ENABLE_INSN_P (532)"
"cpaddacla0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddacua0_h_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2102))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2103))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2104))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2105))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2106))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2107))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2108))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2109))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2110))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2111))]
+ ] 2110))]
"CGEN_ENABLE_INSN_P (533)"
"cpaddacua0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddaca0_b_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2112))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2113))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2114))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2115))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2116))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2117))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2118))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2119))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2120))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2121))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2122))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2123))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2124))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2125))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2126))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2127))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2128))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2129))]
+ ] 2128))]
"CGEN_ENABLE_INSN_P (534)"
"cpaddaca0.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddaca0u_b_P0S"
[(set (reg:SI 86)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2130))
- (set (reg:SI 124)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2131))
(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2132))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2133))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2134))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2135))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2136))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2137))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2138))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2139))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2140))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2141))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2142))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2143))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2144))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2145))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2146))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2147))]
+ ] 2146))]
"CGEN_ENABLE_INSN_P (535)"
"cpaddaca0u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddla0_h_P0S"
[(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2148))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2149))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2150))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2151))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2152))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2153))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2154))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2155))]
+ ] 2154))]
"CGEN_ENABLE_INSN_P (536)"
"cpaddla0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpaddua0_h_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2156))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2157))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2158))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2159))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2160))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2161))
(set (reg:SI 100)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2162))
- (set (reg:SI 132)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2163))]
+ ] 2162))]
"CGEN_ENABLE_INSN_P (537)"
"cpaddua0.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpadda0_b_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2164))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2165))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2166))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2167))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2168))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2169))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2170))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2171))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2172))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2173))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2174))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2175))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2176))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2177))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2178))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2179))]
+ ] 2178))]
"CGEN_ENABLE_INSN_P (538)"
"cpadda0.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpadda0u_b_P0S"
[(set (reg:SI 103)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
] 2180))
- (set (reg:SI 129)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2181))
(set (reg:SI 102)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2182))
- (set (reg:SI 130)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2183))
(set (reg:SI 101)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2184))
- (set (reg:SI 131)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2185))
(set (reg:SI 100)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2186))
- (set (reg:SI 132)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2187))
(set (reg:SI 99)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2188))
- (set (reg:SI 125)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2189))
(set (reg:SI 98)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2190))
- (set (reg:SI 126)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2191))
(set (reg:SI 97)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
] 2192))
- (set (reg:SI 127)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2193))
(set (reg:SI 96)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 2194))
- (set (reg:SI 128)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_dup 0)
(match_dup 1)
- ] 2195))]
+ ] 2194))]
"CGEN_ENABLE_INSN_P (539)"
"cpadda0u.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpge_w_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3282))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3283))]
+ ] 3282))]
"CGEN_ENABLE_INSN_P (540)"
"cpcmpge.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpge_w_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3282))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3283))]
+ ] 3282))]
"CGEN_ENABLE_INSN_P (541)"
"cpcmpge.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgeu_w_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3284))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3285))]
+ ] 3284))]
"CGEN_ENABLE_INSN_P (542)"
"cpcmpgeu.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgeu_w_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3284))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3285))]
+ ] 3284))]
"CGEN_ENABLE_INSN_P (543)"
"cpcmpgeu.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpge_h_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3286))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3287))]
+ ] 3286))]
"CGEN_ENABLE_INSN_P (544)"
"cpcmpge.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpge_h_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3286))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3287))]
+ ] 3286))]
"CGEN_ENABLE_INSN_P (545)"
"cpcmpge.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpge_b_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3288))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3289))]
+ ] 3288))]
"CGEN_ENABLE_INSN_P (546)"
"cpcmpge.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpge_b_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3288))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3289))]
+ ] 3288))]
"CGEN_ENABLE_INSN_P (547)"
"cpcmpge.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgeu_b_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3290))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3291))]
+ ] 3290))]
"CGEN_ENABLE_INSN_P (548)"
"cpcmpgeu.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgeu_b_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3290))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3291))]
+ ] 3290))]
"CGEN_ENABLE_INSN_P (549)"
"cpcmpgeu.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgt_w_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3292))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3293))]
+ ] 3292))]
"CGEN_ENABLE_INSN_P (550)"
"cpcmpgt.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgt_w_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3292))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3293))]
+ ] 3292))]
"CGEN_ENABLE_INSN_P (551)"
"cpcmpgt.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgtu_w_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3294))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3295))]
+ ] 3294))]
"CGEN_ENABLE_INSN_P (552)"
"cpcmpgtu.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgtu_w_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3294))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3295))]
+ ] 3294))]
"CGEN_ENABLE_INSN_P (553)"
"cpcmpgtu.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgt_h_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3296))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3297))]
+ ] 3296))]
"CGEN_ENABLE_INSN_P (554)"
"cpcmpgt.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgt_h_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3296))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3297))]
+ ] 3296))]
"CGEN_ENABLE_INSN_P (555)"
"cpcmpgt.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgt_b_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3298))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3299))]
+ ] 3298))]
"CGEN_ENABLE_INSN_P (556)"
"cpcmpgt.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgt_b_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3298))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3299))]
+ ] 3298))]
"CGEN_ENABLE_INSN_P (557)"
"cpcmpgt.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgtu_b_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3300))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3301))]
+ ] 3300))]
"CGEN_ENABLE_INSN_P (558)"
"cpcmpgtu.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpgtu_b_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3300))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3301))]
+ ] 3300))]
"CGEN_ENABLE_INSN_P (559)"
"cpcmpgtu.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpne_w_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3302))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3303))]
+ ] 3302))]
"CGEN_ENABLE_INSN_P (560)"
"cpcmpne.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpne_w_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3302))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3303))]
+ ] 3302))]
"CGEN_ENABLE_INSN_P (561)"
"cpcmpne.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpne_h_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3304))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3305))]
+ ] 3304))]
"CGEN_ENABLE_INSN_P (562)"
"cpcmpne.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpne_h_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3304))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3305))]
+ ] 3304))]
"CGEN_ENABLE_INSN_P (563)"
"cpcmpne.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpne_b_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3306))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3307))]
+ ] 3306))]
"CGEN_ENABLE_INSN_P (564)"
"cpcmpne.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpne_b_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3306))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3307))]
+ ] 3306))]
"CGEN_ENABLE_INSN_P (565)"
"cpcmpne.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpeq_w_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3308))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3309))]
+ ] 3308))]
"CGEN_ENABLE_INSN_P (566)"
"cpcmpeq.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpeq_w_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3308))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3309))]
+ ] 3308))]
"CGEN_ENABLE_INSN_P (567)"
"cpcmpeq.w\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpeq_h_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3310))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3311))]
+ ] 3310))]
"CGEN_ENABLE_INSN_P (568)"
"cpcmpeq.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpeq_h_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3310))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3311))]
+ ] 3310))]
"CGEN_ENABLE_INSN_P (569)"
"cpcmpeq.h\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpeq_b_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3312))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3313))]
+ ] 3312))]
"CGEN_ENABLE_INSN_P (570)"
"cpcmpeq.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpeq_b_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3312))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3313))]
+ ] 3312))]
"CGEN_ENABLE_INSN_P (571)"
"cpcmpeq.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpeqz_b_C3"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3314))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3315))]
+ ] 3314))]
"CGEN_ENABLE_INSN_P (572)"
"cpcmpeqz.b\\t%0,%1"
[(set_attr "may_trap" "no")
(define_insn "cgen_intrinsic_cpcmpeqz_b_P0S_P1"
[(set (reg:SI 81)
- (unspec:SI [
+ (unspec_volatile:SI [
(match_operand:DI 0 "general_operand" "x")
(match_operand:DI 1 "general_operand" "x")
- ] 3314))
- (set (reg:SI 123)
- (unspec:SI [
- (match_dup 0)
- (match_dup 1)
- ] 3315))]
+ ] 3314))]
"CGEN_ENABLE_INSN_P (573)"
"cpcmpeqz.b\\t%0,%1"
[(set_attr "may_trap" "no")
(reg:SI 32)
(reg:SI 42)
] 3558))
- (set (reg:SI 133)
+ (set (reg:SI 115)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 32)
(reg:SI 42)
] 3562))
- (set (reg:SI 133)
+ (set (reg:SI 115)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 41)
(reg:SI 40)
] 3724))
- (set (reg:SI 134)
+ (set (reg:SI 116)
(unspec:SI [
(reg:SI 41)
(reg:SI 40)
(match_dup 0)
(match_dup 1)
] 3728))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_dup 0)
(match_dup 1)
] 3730))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_dup 0)
(match_dup 1)
] 3734))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_dup 0)
(match_dup 1)
] 3736))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 24)
(reg:SI 23)
] 3740))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
] 3742))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
] 3746))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
] 3748))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(reg:SI 24)
(reg:SI 23)
] 3750))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 24)
(reg:SI 23)
] 3752))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 24)
(reg:SI 23)
] 3754))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 24)
(reg:SI 23)
] 3756))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_dup 1)
(match_dup 2)
] 3760))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_dup 1)
(match_dup 2)
] 3762))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_dup 1)
(match_dup 2)
] 3766))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_dup 1)
(match_dup 2)
] 3768))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 1)
(match_dup 2)
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "general_operand" "r")
] 3770))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_dup 0)
(match_dup 1)
] 3772))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_operand:SI 0 "general_operand" "r")
(match_operand:SI 1 "general_operand" "r")
] 3774))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(match_dup 0)
(match_dup 1)
] 3776))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
] 3822))
- (set (reg:SI 135)
+ (set (reg:SI 117)
(unspec:SI [
(match_dup 0)
] 3823))]
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
] 3824))
- (set (reg:SI 136)
+ (set (reg:SI 118)
(unspec:SI [
(match_dup 0)
] 3825))]
(unspec:SI [
(match_operand:SI 0 "general_operand" "r")
] 3826))
- (set (reg:SI 133)
+ (set (reg:SI 115)
(unspec:SI [
(match_dup 0)
] 3827))]
(reg:SI 32)
(reg:SI 42)
] 3828))
- (set (reg:SI 137)
+ (set (reg:SI 119)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 32)
(reg:SI 42)
] 3830))
- (set (reg:SI 138)
+ (set (reg:SI 120)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 32)
(reg:SI 42)
] 3832))
- (set (reg:SI 139)
+ (set (reg:SI 121)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 32)
(reg:SI 42)
] 3834))
- (set (reg:SI 137)
+ (set (reg:SI 119)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 32)
(reg:SI 42)
] 3836))
- (set (reg:SI 138)
+ (set (reg:SI 120)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 32)
(reg:SI 42)
] 3838))
- (set (reg:SI 139)
+ (set (reg:SI 121)
(unspec:SI [
(match_dup 0)
(match_dup 1)
(reg:SI 32)
(reg:SI 42)
] 3844))
- (set (reg:SI 133)
+ (set (reg:SI 115)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 32)
(reg:SI 42)
] 3856))
- (set (reg:SI 133)
+ (set (reg:SI 115)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(reg:SI 32)
(reg:SI 42)
] 3852))
- (set (reg:SI 133)
+ (set (reg:SI 115)
(unspec:SI [
(match_dup 0)
(reg:SI 32)
(match_operand:SI 0 "cgen_h_sint_2a1_immediate" "")
(match_operand:SI 1 "general_operand" "r")
] 3950))
- (set (reg:SI 140)
+ (set (reg:SI 122)
(unspec:SI [
(match_dup 0)
(match_dup 1)
#ifdef WANT_GCC_DECLARATIONS
#define FIRST_SHADOW_REGISTER 113
-#define LAST_SHADOW_REGISTER 140
+#define LAST_SHADOW_REGISTER 122
#define FIXED_SHADOW_REGISTERS \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
#define CALL_USED_SHADOW_REGISTERS FIXED_SHADOW_REGISTERS
#define SHADOW_REG_ALLOC_ORDER \
- 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140
+ 113, 114, 115, 116, 117, 118, 119, 120, 121, 122
#define SHADOW_REGISTER_NAMES \
- "$shadow87", "$shadow107", "$shadow106", "$shadow105", "$shadow104", "$shadow111", "$shadow110", "$shadow109", "$shadow108", "$shadow84", "$shadow81", "$shadow86", "$shadow99", "$shadow98", "$shadow97", "$shadow96", "$shadow103", "$shadow102", "$shadow101", "$shadow100", "$shadow17", "$shadow40", "$shadow24", "$shadow23", "$shadow22", "$shadow21", "$shadow20", "$shadow18"
+ "$shadow84", "$shadow81", "$shadow17", "$shadow40", "$shadow24", "$shadow23", "$shadow22", "$shadow21", "$shadow20", "$shadow18"
; 1111 0000 0000 0111 10010 qqqqq ppppp 0 cpcmpeqz.b crqc,crpc (c3_1)
(dni cpcmpeqz_b_C3 "cpcmpeqz.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI) VOLATILE)
"cpcmpeqz.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0000 0001 0111 10010 qqqqq ppppp 0 cpcmpeq.b crqc,crpc (c3_1)
(dni cpcmpeq_b_C3 "cpcmpeq.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI) VOLATILE)
"cpcmpeq.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0000 0011 0111 10010 qqqqq ppppp 0 cpcmpeq.h crqc,crpc (c3_1)
(dni cpcmpeq_h_C3 "cpcmpeq.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI) VOLATILE)
"cpcmpeq.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x3) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0000 0101 0111 10010 qqqqq ppppp 0 cpcmpeq.w crqc,crpc (c3_1)
(dni cpcmpeq_w_C3 "cpcmpeq.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI) VOLATILE)
"cpcmpeq.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0000 1001 0111 10010 qqqqq ppppp 0 cpcmpne.b crqc,crpc (c3_1)
(dni cpcmpne_b_C3 "cpcmpne.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI) VOLATILE)
"cpcmpne.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0000 1011 0111 10010 qqqqq ppppp 0 cpcmpne.h crqc,crpc (c3_1)
(dni cpcmpne_h_C3 "cpcmpne.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI) VOLATILE)
"cpcmpne.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0000 1101 0111 10010 qqqqq ppppp 0 cpcmpne.w crqc,crpc (c3_1)
(dni cpcmpne_w_C3 "cpcmpne.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI) VOLATILE)
"cpcmpne.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0001 0000 0111 10010 qqqqq ppppp 0 cpcmpgtu.b crqc,crpc (c3_1)
(dni cpcmpgtu_b_C3 "cpcmpgtu.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI) VOLATILE)
"cpcmpgtu.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0001 0001 0111 10010 qqqqq ppppp 0 cpcmpgt.b crqc,crpc (c3_1)
(dni cpcmpgt_b_C3 "cpcmpgt.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI) VOLATILE)
"cpcmpgt.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0001 0011 0111 10010 qqqqq ppppp 0 cpcmpgt.h crqc,crpc (c3_1)
(dni cpcmpgt_h_C3 "cpcmpgt.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI) VOLATILE)
"cpcmpgt.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0001 0100 0111 10010 qqqqq ppppp 0 cpcmpgtu.w crqc,crpc (c3_1)
(dni cpcmpgtu_w_C3 "cpcmpgtu.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI) VOLATILE)
"cpcmpgtu.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0001 0101 0111 10010 qqqqq ppppp 0 cpcmpgt.w crqc,crpc (c3_1)
(dni cpcmpgt_w_C3 "cpcmpgt.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI) VOLATILE)
"cpcmpgt.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0001 1000 0111 10010 qqqqq ppppp 0 cpcmpgeu.b crqc,crpc (c3_1)
(dni cpcmpgeu_b_C3 "cpcmpgeu.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI) VOLATILE)
"cpcmpgeu.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x18) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0001 1001 0111 10010 qqqqq ppppp 0 cpcmpge.b crqc,crpc (c3_1)
(dni cpcmpge_b_C3 "cpcmpge.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI) VOLATILE)
"cpcmpge.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x19) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0001 1011 0111 10010 qqqqq ppppp 0 cpcmpge.h crqc,crpc (c3_1)
(dni cpcmpge_h_C3 "cpcmpge.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI) VOLATILE)
"cpcmpge.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1b) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0001 1100 0111 10010 qqqqq ppppp 0 cpcmpgeu.w crqc,crpc (c3_1)
(dni cpcmpgeu_w_C3 "cpcmpgeu.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI) VOLATILE)
"cpcmpgeu.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1c) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0001 1101 0111 10010 qqqqq ppppp 0 cpcmpge.w crqc,crpc (c3_1)
(dni cpcmpge_w_C3 "cpcmpge.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI) VOLATILE)
"cpcmpge.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1d) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
; 1111 0000 0000 0111 00000 qqqqq ppppp 1 cpadda1u.b crqc,crpc (c3_1)
(dni cpadda1u_b_C3 "cpadda1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI) VOLATILE)
"cpadda1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0001 0111 00000 qqqqq ppppp 1 cpadda1.b crqc,crpc (c3_1)
(dni cpadda1_b_C3 "cpadda1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1_b") (CPTYPE V8QI) VOLATILE)
"cpadda1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0010 0111 00000 qqqqq ppppp 1 cpaddua1.h crqc,crpc (c3_1)
(dni cpaddua1_h_C3 "cpaddua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI) VOLATILE)
"cpaddua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x2) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0011 0111 00000 qqqqq ppppp 1 cpaddla1.h crqc,crpc (c3_1)
(dni cpaddla1_h_C3 "cpaddla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI) VOLATILE)
"cpaddla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x3) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0100 0111 00000 qqqqq ppppp 1 cpaddaca1u.b crqc,crpc (c3_1)
(dni cpaddaca1u_b_C3 "cpaddaca1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI) VOLATILE)
"cpaddaca1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x4) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0101 0111 00000 qqqqq ppppp 1 cpaddaca1.b crqc,crpc (c3_1)
(dni cpaddaca1_b_C3 "cpaddaca1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI) VOLATILE)
"cpaddaca1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0110 0111 00000 qqqqq ppppp 1 cpaddacua1.h crqc,crpc (c3_1)
(dni cpaddacua1_h_C3 "cpaddacua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI) VOLATILE)
"cpaddacua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x6) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0111 0111 00000 qqqqq ppppp 1 cpaddacla1.h crqc,crpc (c3_1)
(dni cpaddacla1_h_C3 "cpaddacla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI) VOLATILE)
"cpaddacla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x7) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1000 0111 00000 qqqqq ppppp 1 cpsuba1u.b crqc,crpc (c3_1)
(dni cpsuba1u_b_C3 "cpsuba1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI) VOLATILE)
"cpsuba1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x8) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1001 0111 00000 qqqqq ppppp 1 cpsuba1.b crqc,crpc (c3_1)
(dni cpsuba1_b_C3 "cpsuba1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI) VOLATILE)
"cpsuba1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1010 0111 00000 qqqqq ppppp 1 cpsubua1.h crqc,crpc (c3_1)
(dni cpsubua1_h_C3 "cpsubua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI) VOLATILE)
"cpsubua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xa) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1011 0111 00000 qqqqq ppppp 1 cpsubla1.h crqc,crpc (c3_1)
(dni cpsubla1_h_C3 "cpsubla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI) VOLATILE)
"cpsubla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1100 0111 00000 qqqqq ppppp 1 cpsubaca1u.b crqc,crpc (c3_1)
(dni cpsubaca1u_b_C3 "cpsubaca1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI) VOLATILE)
"cpsubaca1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xc) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1101 0111 00000 qqqqq ppppp 1 cpsubaca1.b crqc,crpc (c3_1)
(dni cpsubaca1_b_C3 "cpsubaca1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI) VOLATILE)
"cpsubaca1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1110 0111 00000 qqqqq ppppp 1 cpsubacua1.h crqc,crpc (c3_1)
(dni cpsubacua1_h_C3 "cpsubacua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI) VOLATILE)
"cpsubacua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xe) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1111 0111 00000 qqqqq ppppp 1 cpsubacla1.h crqc,crpc (c3_1)
(dni cpsubacla1_h_C3 "cpsubacla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI) VOLATILE)
"cpsubacla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xf) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0000 0111 00000 qqqqq ppppp 1 cpabsa1u.b crqc,crpc (c3_1)
(dni cpabsa1u_b_C3 "cpabsa1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI) VOLATILE)
"cpabsa1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0001 0111 00000 qqqqq ppppp 1 cpabsa1.b crqc,crpc (c3_1)
(dni cpabsa1_b_C3 "cpabsa1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI) VOLATILE)
"cpabsa1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0010 0111 00000 qqqqq ppppp 1 cpabsua1.h crqc,crpc (c3_1)
(dni cpabsua1_h_C3 "cpabsua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI) VOLATILE)
"cpabsua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x12) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0011 0111 00000 qqqqq ppppp 1 cpabsla1.h crqc,crpc (c3_1)
(dni cpabsla1_h_C3 "cpabsla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI) VOLATILE)
"cpabsla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0100 0111 00000 qqqqq ppppp 1 cpsada1u.b crqc,crpc (c3_1)
(dni cpsada1u_b_C3 "cpsada1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI) VOLATILE)
"cpsada1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0101 0111 00000 qqqqq ppppp 1 cpsada1.b crqc,crpc (c3_1)
(dni cpsada1_b_C3 "cpsada1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1_b") (CPTYPE V8QI) VOLATILE)
"cpsada1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0110 0111 00000 qqqqq ppppp 1 cpsadua1.h crqc,crpc (c3_1)
(dni cpsadua1_h_C3 "cpsadua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI) VOLATILE)
"cpsadua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x16) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0111 0111 00000 qqqqq ppppp 1 cpsadla1.h crqc,crpc (c3_1)
(dni cpsadla1_h_C3 "cpsadla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI) VOLATILE)
"cpsadla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x17) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0010 0000 0111 00000 qqqqq ppppp 1 cpseta1.h crqc,crpc (c3_1)
(dni cpseta1_h_C3 "cpseta1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpseta1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpseta1_h") (CPTYPE V4HI) VOLATILE)
"cpseta1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0010 0010 0111 00000 qqqqq ppppp 1 cpsetua1.w crqc,crpc (c3_1)
(dni cpsetua1_w_C3 "cpsetua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI) VOLATILE)
"cpsetua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x2) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0010 0011 0111 00000 qqqqq ppppp 1 cpsetla1.w crqc,crpc (c3_1)
(dni cpsetla1_w_C3 "cpsetla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI) VOLATILE)
"cpsetla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x3) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0000 0111 00010 qqqqq 00000 1 cpsrla1 crqc (c3_1)
(dni cpsrla1_C3 "cpsrla1 $crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrla1"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrla1") VOLATILE)
"cpsrla1 $crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
; 1111 0000 0001 0111 00010 qqqqq 00000 1 cpsraa1 crqc (c3_1)
(dni cpsraa1_C3 "cpsraa1 $crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsraa1"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsraa1") VOLATILE)
"cpsraa1 $crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
(f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
; 1111 0000 0010 0111 00010 qqqqq 00000 1 cpslla1 crqc (c3_1)
(dni cpslla1_C3 "cpslla1 $crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslla1"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslla1") VOLATILE)
"cpslla1 $crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x2) (f-sub4 7)
(f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
; 1111 00xi iiii 0111 00011 00000 00000 1 cpsrlia1 imm5p7 (c3_imm)
(dni cpsrlia1_P1 "cpsrlia1 imm5p7 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrlia1"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrlia1") VOLATILE)
"cpsrlia1 $imm5p7"
(+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x0) imm5p7 (f-sub4 7)
(f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
; 1111 01xi iiii 0111 00011 00000 00000 1 cpsraia1 imm5p7 (c3_imm)
(dni cpsraia1_P1 "cpsraia1 imm5p7 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsraia1"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsraia1") VOLATILE)
"cpsraia1 $imm5p7"
(+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x1) imm5p7 (f-sub4 7)
(f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
; 1111 10xi iiii 0111 00011 00000 00000 1 cpsllia1 imm5p7 (c3_imm)
(dni cpsllia1_P1 "cpsllia1 imm5p7 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsllia1"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsllia1") VOLATILE)
"cpsllia1 $imm5p7"
(+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7)
(f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
; 1111 0000 0000 0111 00001 qqqqq ppppp 1 cpssqa1u.b crqc,crpc (c3_1)
(dni cpssqa1u_b_C3 "cpssqa1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI) VOLATILE)
"cpssqa1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0001 0111 00001 qqqqq ppppp 1 cpssqa1.b crqc,crpc (c3_1)
(dni cpssqa1_b_C3 "cpssqa1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI) VOLATILE)
"cpssqa1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0100 0111 00001 qqqqq ppppp 1 cpssda1u.b crqc,crpc (c3_1)
(dni cpssda1u_b_C3 "cpssda1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI) VOLATILE)
"cpssda1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x4) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 0101 0111 00001 qqqqq ppppp 1 cpssda1.b crqc,crpc (c3_1)
(dni cpssda1_b_C3 "cpssda1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1_b") (CPTYPE V8QI) VOLATILE)
"cpssda1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1000 0111 00001 qqqqq ppppp 1 cpmula1u.b crqc,crpc (c3_1)
(dni cpmula1u_b_C3 "cpmula1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI) VOLATILE)
"cpmula1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x8) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1001 0111 00001 qqqqq ppppp 1 cpmula1.b crqc,crpc (c3_1)
(dni cpmula1_b_C3 "cpmula1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1_b") (CPTYPE V8QI) VOLATILE)
"cpmula1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1010 0111 00001 qqqqq ppppp 1 cpmulua1.h crqc,crpc (c3_1)
(dni cpmulua1_h_C3 "cpmulua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI) VOLATILE)
"cpmulua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xa) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1011 0111 00001 qqqqq ppppp 1 cpmulla1.h crqc,crpc (c3_1)
(dni cpmulla1_h_C3 "cpmulla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI) VOLATILE)
"cpmulla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1100 0111 00001 qqqqq ppppp 1 cpmulua1u.w crqc,crpc (c3_1)
(dni cpmulua1u_w_C3 "cpmulua1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI) VOLATILE)
"cpmulua1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xc) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1101 0111 00001 qqqqq ppppp 1 cpmulla1u.w crqc,crpc (c3_1)
(dni cpmulla1u_w_C3 "cpmulla1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI) VOLATILE)
"cpmulla1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1110 0111 00001 qqqqq ppppp 1 cpmulua1.w crqc,crpc (c3_1)
(dni cpmulua1_w_C3 "cpmulua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI) VOLATILE)
"cpmulua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xe) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0000 1111 0111 00001 qqqqq ppppp 1 cpmulla1.w crqc,crpc (c3_1)
(dni cpmulla1_w_C3 "cpmulla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI) VOLATILE)
"cpmulla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xf) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0000 0111 00001 qqqqq ppppp 1 cpmada1u.b crqc,crpc (c3_1)
(dni cpmada1u_b_C3 "cpmada1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI) VOLATILE)
"cpmada1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0001 0111 00001 qqqqq ppppp 1 cpmada1.b crqc,crpc (c3_1)
(dni cpmada1_b_C3 "cpmada1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1_b") (CPTYPE V8QI) VOLATILE)
"cpmada1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0010 0111 00001 qqqqq ppppp 1 cpmadua1.h crqc,crpc (c3_1)
(dni cpmadua1_h_C3 "cpmadua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI) VOLATILE)
"cpmadua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x12) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0011 0111 00001 qqqqq ppppp 1 cpmadla1.h crqc,crpc (c3_1)
(dni cpmadla1_h_C3 "cpmadla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI) VOLATILE)
"cpmadla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0100 0111 00001 qqqqq ppppp 1 cpmadua1u.w crqc,crpc (c3_1)
(dni cpmadua1u_w_C3 "cpmadua1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI) VOLATILE)
"cpmadua1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0101 0111 00001 qqqqq ppppp 1 cpmadla1u.w crqc,crpc (c3_1)
(dni cpmadla1u_w_C3 "cpmadla1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI) VOLATILE)
"cpmadla1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0110 0111 00001 qqqqq ppppp 1 cpmadua1.w crqc,crpc (c3_1)
(dni cpmadua1_w_C3 "cpmadua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI) VOLATILE)
"cpmadua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x16) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 0111 0111 00001 qqqqq ppppp 1 cpmadla1.w crqc,crpc (c3_1)
(dni cpmadla1_w_C3 "cpmadla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI) VOLATILE)
"cpmadla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x17) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 1010 0111 00001 qqqqq ppppp 1 cpmsbua1.h crqc,crpc (c3_1)
(dni cpmsbua1_h_C3 "cpmsbua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI) VOLATILE)
"cpmsbua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1a) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 1011 0111 00001 qqqqq ppppp 1 cpmsbla1.h crqc,crpc (c3_1)
(dni cpmsbla1_h_C3 "cpmsbla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI) VOLATILE)
"cpmsbla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1b) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 1100 0111 00001 qqqqq ppppp 1 cpmsbua1u.w crqc,crpc (c3_1)
(dni cpmsbua1u_w_C3 "cpmsbua1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI) VOLATILE)
"cpmsbua1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1c) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 1101 0111 00001 qqqqq ppppp 1 cpmsbla1u.w crqc,crpc (c3_1)
(dni cpmsbla1u_w_C3 "cpmsbla1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI) VOLATILE)
"cpmsbla1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1d) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 1110 0111 00001 qqqqq ppppp 1 cpmsbua1.w crqc,crpc (c3_1)
(dni cpmsbua1_w_C3 "cpmsbua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI) VOLATILE)
"cpmsbua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1e) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0001 1111 0111 00001 qqqqq ppppp 1 cpmsbla1.w crqc,crpc (c3_1)
(dni cpmsbla1_w_C3 "cpmsbla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI) VOLATILE)
"cpmsbla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1f) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0011 0010 0111 00001 qqqqq ppppp 1 cpsmadua1.h crqc,crpc (c3_1)
(dni cpsmadua1_h_C3 "cpsmadua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI) VOLATILE)
"cpsmadua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x12) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0011 0011 0111 00001 qqqqq ppppp 1 cpsmadla1.h crqc,crpc (c3_1)
(dni cpsmadla1_h_C3 "cpsmadla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI) VOLATILE)
"cpsmadla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0011 0110 0111 00001 qqqqq ppppp 1 cpsmadua1.w crqc,crpc (c3_1)
(dni cpsmadua1_w_C3 "cpsmadua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI) VOLATILE)
"cpsmadua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x16) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0011 0111 0111 00001 qqqqq ppppp 1 cpsmadla1.w crqc,crpc (c3_1)
(dni cpsmadla1_w_C3 "cpsmadla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI) VOLATILE)
"cpsmadla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x17) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0011 1010 0111 00001 qqqqq ppppp 1 cpsmsbua1.h crqc,crpc (c3_1)
(dni cpsmsbua1_h_C3 "cpsmsbua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI) VOLATILE)
"cpsmsbua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1a) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0011 1011 0111 00001 qqqqq ppppp 1 cpsmsbla1.h crqc,crpc (c3_1)
(dni cpsmsbla1_h_C3 "cpsmsbla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI) VOLATILE)
"cpsmsbla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1b) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0011 1110 0111 00001 qqqqq ppppp 1 cpsmsbua1.w crqc,crpc (c3_1)
(dni cpsmsbua1_w_C3 "cpsmsbua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI) VOLATILE)
"cpsmsbua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1e) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0011 1111 0111 00001 qqqqq ppppp 1 cpsmsbla1.w crqc,crpc (c3_1)
(dni cpsmsbla1_w_C3 "cpsmsbla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI) VOLATILE)
"cpsmsbla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1f) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0100 1010 0111 00001 qqqqq ppppp 1 cpmulslua1.h crqc,crpc (c3_1)
(dni cpmulslua1_h_C3 "cpmulslua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI) VOLATILE)
"cpmulslua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xa) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0100 1011 0111 00001 qqqqq ppppp 1 cpmulslla1.h crqc,crpc (c3_1)
(dni cpmulslla1_h_C3 "cpmulslla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI) VOLATILE)
"cpmulslla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xb) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0100 1110 0111 00001 qqqqq ppppp 1 cpmulslua1.w crqc,crpc (c3_1)
(dni cpmulslua1_w_C3 "cpmulslua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI) VOLATILE)
"cpmulslua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xe) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0100 1111 0111 00001 qqqqq ppppp 1 cpmulslla1.w crqc,crpc (c3_1)
(dni cpmulslla1_w_C3 "cpmulslla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI) VOLATILE)
"cpmulslla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xf) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0111 0010 0111 00001 qqqqq ppppp 1 cpsmadslua1.h crqc,crpc (c3_1)
(dni cpsmadslua1_h_C3 "cpsmadslua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI) VOLATILE)
"cpsmadslua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x12) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0111 0011 0111 00001 qqqqq ppppp 1 cpsmadslla1.h crqc,crpc (c3_1)
(dni cpsmadslla1_h_C3 "cpsmadslla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI) VOLATILE)
"cpsmadslla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0111 0110 0111 00001 qqqqq ppppp 1 cpsmadslua1.w crqc,crpc (c3_1)
(dni cpsmadslua1_w_C3 "cpsmadslua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI) VOLATILE)
"cpsmadslua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x16) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0111 0111 0111 00001 qqqqq ppppp 1 cpsmadslla1.w crqc,crpc (c3_1)
(dni cpsmadslla1_w_C3 "cpsmadslla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI) VOLATILE)
"cpsmadslla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x17) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0111 1010 0111 00001 qqqqq ppppp 1 cpsmsbslua1.h crqc,crpc (c3_1)
(dni cpsmsbslua1_h_C3 "cpsmsbslua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI) VOLATILE)
"cpsmsbslua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1a) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0111 1011 0111 00001 qqqqq ppppp 1 cpsmsbslla1.h crqc,crpc (c3_1)
(dni cpsmsbslla1_h_C3 "cpsmsbslla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI) VOLATILE)
"cpsmsbslla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1b) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0111 1110 0111 00001 qqqqq ppppp 1 cpsmsbslua1.w crqc,crpc (c3_1)
(dni cpsmsbslua1_w_C3 "cpsmsbslua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI) VOLATILE)
"cpsmsbslua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1e) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 1111 0111 1111 0111 00001 qqqqq ppppp 1 cpsmsbslla1.w crqc,crpc (c3_1)
(dni cpsmsbslla1_w_C3 "cpsmsbslla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI) VOLATILE)
"cpsmsbslla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1f) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
; 10010 qqqqq ppppp 00000 cpcmpeqz.b crqp,crpp (p0_1)
(dni cpcmpeqz_b_P0S_P1 "cpcmpeqz.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI) VOLATILE)
"cpcmpeqz.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 00001 cpcmpeq.b crqp,crpp (p0_1)
(dni cpcmpeq_b_P0S_P1 "cpcmpeq.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI) VOLATILE)
"cpcmpeq.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 00011 cpcmpeq.h crqp,crpp (p0_1)
(dni cpcmpeq_h_P0S_P1 "cpcmpeq.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI) VOLATILE)
"cpcmpeq.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 00101 cpcmpeq.w crqp,crpp (p0_1)
(dni cpcmpeq_w_P0S_P1 "cpcmpeq.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI) VOLATILE)
"cpcmpeq.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 01001 cpcmpne.b crqp,crpp (p0_1)
(dni cpcmpne_b_P0S_P1 "cpcmpne.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI) VOLATILE)
"cpcmpne.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 01011 cpcmpne.h crqp,crpp (p0_1)
(dni cpcmpne_h_P0S_P1 "cpcmpne.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI) VOLATILE)
"cpcmpne.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 01101 cpcmpne.w crqp,crpp (p0_1)
(dni cpcmpne_w_P0S_P1 "cpcmpne.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI) VOLATILE)
"cpcmpne.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 10000 cpcmpgtu.b crqp,crpp (p0_1)
(dni cpcmpgtu_b_P0S_P1 "cpcmpgtu.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI) VOLATILE)
"cpcmpgtu.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 10001 cpcmpgt.b crqp,crpp (p0_1)
(dni cpcmpgt_b_P0S_P1 "cpcmpgt.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI) VOLATILE)
"cpcmpgt.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 10011 cpcmpgt.h crqp,crpp (p0_1)
(dni cpcmpgt_h_P0S_P1 "cpcmpgt.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI) VOLATILE)
"cpcmpgt.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 10100 cpcmpgtu.w crqp,crpp (p0_1)
(dni cpcmpgtu_w_P0S_P1 "cpcmpgtu.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI) VOLATILE)
"cpcmpgtu.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 10101 cpcmpgt.w crqp,crpp (p0_1)
(dni cpcmpgt_w_P0S_P1 "cpcmpgt.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI) VOLATILE)
"cpcmpgt.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 11000 cpcmpgeu.b crqp,crpp (p0_1)
(dni cpcmpgeu_b_P0S_P1 "cpcmpgeu.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI) VOLATILE)
"cpcmpgeu.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 11001 cpcmpge.b crqp,crpp (p0_1)
(dni cpcmpge_b_P0S_P1 "cpcmpge.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI) VOLATILE)
"cpcmpge.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 11011 cpcmpge.h crqp,crpp (p0_1)
(dni cpcmpge_h_P0S_P1 "cpcmpge.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI) VOLATILE)
"cpcmpge.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 11100 cpcmpgeu.w crqp,crpp (p0_1)
(dni cpcmpgeu_w_P0S_P1 "cpcmpgeu.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI) VOLATILE)
"cpcmpgeu.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
(sequence ()
; 10010 qqqqq ppppp 11101 cpcmpge.w crqp,crpp (p0_1)
(dni cpcmpge_w_P0S_P1 "cpcmpge.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI) VOLATILE)
"cpcmpge.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 00000 cpadda0u.b crqp,crpp (p0_1)
(dni cpadda0u_b_P0S "cpadda0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0u_b") (CPTYPE V8UQI) VOLATILE)
"cpadda0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 00001 cpadda0.b crqp,crpp (p0_1)
(dni cpadda0_b_P0S "cpadda0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0_b") (CPTYPE V8QI) VOLATILE)
"cpadda0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 00010 cpaddua0.h crqp,crpp (p0_1)
(dni cpaddua0_h_P0S "cpaddua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddua0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddua0_h") (CPTYPE V4HI) VOLATILE)
"cpaddua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 00011 cpaddla0.h crqp,crpp (p0_1)
(dni cpaddla0_h_P0S "cpaddla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddla0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddla0_h") (CPTYPE V4HI) VOLATILE)
"cpaddla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 00100 cpaddaca0u.b crqp,crpp (p0_1)
(dni cpaddaca0u_b_P0S "cpaddaca0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0u_b") (CPTYPE V8UQI) VOLATILE)
"cpaddaca0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 00101 cpaddaca0.b crqp,crpp (p0_1)
(dni cpaddaca0_b_P0S "cpaddaca0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0_b") (CPTYPE V8QI) VOLATILE)
"cpaddaca0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 00110 cpaddacua0.h crqp,crpp (p0_1)
(dni cpaddacua0_h_P0S "cpaddacua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacua0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacua0_h") (CPTYPE V4HI) VOLATILE)
"cpaddacua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 00111 cpaddacla0.h crqp,crpp (p0_1)
(dni cpaddacla0_h_P0S "cpaddacla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacla0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacla0_h") (CPTYPE V4HI) VOLATILE)
"cpaddacla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 01000 cpsuba0u.b crqp,crpp (p0_1)
(dni cpsuba0u_b_P0S "cpsuba0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0u_b") (CPTYPE V8UQI) VOLATILE)
"cpsuba0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 01001 cpsuba0.b crqp,crpp (p0_1)
(dni cpsuba0_b_P0S "cpsuba0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0_b") (CPTYPE V8QI) VOLATILE)
"cpsuba0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 01010 cpsubua0.h crqp,crpp (p0_1)
(dni cpsubua0_h_P0S "cpsubua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubua0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubua0_h") (CPTYPE V4HI) VOLATILE)
"cpsubua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 01011 cpsubla0.h crqp,crpp (p0_1)
(dni cpsubla0_h_P0S "cpsubla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubla0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubla0_h") (CPTYPE V4HI) VOLATILE)
"cpsubla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 01100 cpsubaca0u.b crqp,crpp (p0_1)
(dni cpsubaca0u_b_P0S "cpsubaca0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0u_b") (CPTYPE V8UQI) VOLATILE)
"cpsubaca0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 01101 cpsubaca0.b crqp,crpp (p0_1)
(dni cpsubaca0_b_P0S "cpsubaca0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0_b") (CPTYPE V8QI) VOLATILE)
"cpsubaca0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 01110 cpsubacua0.h crqp,crpp (p0_1)
(dni cpsubacua0_h_P0S "cpsubacua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacua0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacua0_h") (CPTYPE V4HI) VOLATILE)
"cpsubacua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 01111 cpsubacla0.h crqp,crpp (p0_1)
(dni cpsubacla0_h_P0S "cpsubacla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacla0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacla0_h") (CPTYPE V4HI) VOLATILE)
"cpsubacla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 10000 cpabsa0u.b crqp,crpp (p0_1)
(dni cpabsa0u_b_P0S "cpabsa0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0u_b") (CPTYPE V8UQI) VOLATILE)
"cpabsa0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 10001 cpabsa0.b crqp,crpp (p0_1)
(dni cpabsa0_b_P0S "cpabsa0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0_b") (CPTYPE V8QI) VOLATILE)
"cpabsa0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 10010 cpabsua0.h crqp,crpp (p0_1)
(dni cpabsua0_h_P0S "cpabsua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsua0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsua0_h") (CPTYPE V4HI) VOLATILE)
"cpabsua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 10011 cpabsla0.h crqp,crpp (p0_1)
(dni cpabsla0_h_P0S "cpabsla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsla0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsla0_h") (CPTYPE V4HI) VOLATILE)
"cpabsla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 10100 cpsada0u.b crqp,crpp (p0_1)
(dni cpsada0u_b_P0S "cpsada0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0u_b") (CPTYPE V8UQI) VOLATILE)
"cpsada0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 10101 cpsada0.b crqp,crpp (p0_1)
(dni cpsada0_b_P0S "cpsada0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0_b") (CPTYPE V8QI) VOLATILE)
"cpsada0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 10110 cpsadua0.h crqp,crpp (p0_1)
(dni cpsadua0_h_P0S "cpsadua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadua0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadua0_h") (CPTYPE V4HI) VOLATILE)
"cpsadua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 10111 cpsadla0.h crqp,crpp (p0_1)
(dni cpsadla0_h_P0S "cpsadla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadla0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadla0_h") (CPTYPE V4HI) VOLATILE)
"cpsadla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 11011 cpseta0.h crqp,crpp (p0_1)
(dni cpseta0_h_P0S "cpseta0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpseta0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpseta0_h") (CPTYPE V4HI) VOLATILE)
"cpseta0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 11100 cpsetua0.w crqp,crpp (p0_1)
(dni cpsetua0_w_P0S "cpsetua0.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetua0_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetua0_w") (CPTYPE V2SI) VOLATILE)
"cpsetua0.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
(sequence ()
; 11000 qqqqq ppppp 11101 cpsetla0.w crqp,crpp (p0_1)
(dni cpsetla0_w_P0S "cpsetla0.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetla0_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetla0_w") (CPTYPE V2SI) VOLATILE)
"cpsetla0.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
(sequence ()
; 11001 00000 10000 00000 cpacsuma0 (p0_1)
(dni cpacsuma0_P0S "cpacsuma0 Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpacsuma0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpacsuma0") VOLATILE)
"cpacsuma0"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 11001 00000 10001 00000 cpaccpa0 (p0_1)
(dni cpaccpa0_P0S "cpaccpa0 Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaccpa0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaccpa0") VOLATILE)
"cpaccpa0"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 11001 qqqqq 11000 00000 cpsrla0 crqp (p0_1)
(dni cpsrla0_P0S "cpsrla0 $crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsrla0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsrla0") VOLATILE)
"cpsrla0 $crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x18) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 11001 qqqqq 11001 00000 cpsraa0 crqp (p0_1)
(dni cpsraa0_P0S "cpsraa0 $crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsraa0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsraa0") VOLATILE)
"cpsraa0 $crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x19) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 11001 qqqqq 11010 00000 cpslla0 crqp (p0_1)
(dni cpslla0_P0S "cpslla0 $crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpslla0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpslla0") VOLATILE)
"cpslla0 $crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x1a) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 11001 00000 11100 iiiii cpsrlia0 imm5p23 (p0_1)
(dni cpsrlia0_P0S "cpsrlia0 imm5p23 Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsrlia0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsrlia0") VOLATILE)
"cpsrlia0 $imm5p23"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1c) imm5p23 (f-ivc2-4u28 0))
(sequence ()
; 11001 00000 11101 iiiii cpsraia0 imm5p23 (p0_1)
(dni cpsraia0_P0S "cpsraia0 imm5p23 Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsraia0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsraia0") VOLATILE)
"cpsraia0 $imm5p23"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1d) imm5p23 (f-ivc2-4u28 0))
(sequence ()
; 11001 00000 11110 iiiii cpsllia0 imm5p23 (p0_1)
(dni cpsllia0_P0S "cpsllia0 imm5p23 Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsllia0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsllia0") VOLATILE)
"cpsllia0 $imm5p23"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1e) imm5p23 (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 00000 cpfsftba0s0u.b crqp,crpp (p0_1)
(dni cpfsftba0s0u_b_P0S "cpfsftba0s0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0u_b") (CPTYPE V8UQI) VOLATILE)
"cpfsftba0s0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 00001 cpfsftba0s0.b crqp,crpp (p0_1)
(dni cpfsftba0s0_b_P0S "cpfsftba0s0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0_b") (CPTYPE V8QI) VOLATILE)
"cpfsftba0s0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 00010 cpfsftbua0s0.h crqp,crpp (p0_1)
(dni cpfsftbua0s0_h_P0S "cpfsftbua0s0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s0_h") (CPTYPE V4HI) VOLATILE)
"cpfsftbua0s0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 00011 cpfsftbla0s0.h crqp,crpp (p0_1)
(dni cpfsftbla0s0_h_P0S "cpfsftbla0s0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s0_h") (CPTYPE V4HI) VOLATILE)
"cpfsftbla0s0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 00100 cpfaca0s0u.b crqp,crpp (p0_1)
(dni cpfaca0s0u_b_P0S "cpfaca0s0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0u_b") (CPTYPE V8UQI) VOLATILE)
"cpfaca0s0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 00101 cpfaca0s0.b crqp,crpp (p0_1)
(dni cpfaca0s0_b_P0S "cpfaca0s0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0_b") (CPTYPE V8QI) VOLATILE)
"cpfaca0s0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 00110 cpfacua0s0.h crqp,crpp (p0_1)
(dni cpfacua0s0_h_P0S "cpfacua0s0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s0_h") (CPTYPE V4HI) VOLATILE)
"cpfacua0s0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 00111 cpfacla0s0.h crqp,crpp (p0_1)
(dni cpfacla0s0_h_P0S "cpfacla0s0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s0_h") (CPTYPE V4HI) VOLATILE)
"cpfacla0s0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 01000 cpfsftba0s1u.b crqp,crpp (p0_1)
(dni cpfsftba0s1u_b_P0S "cpfsftba0s1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1u_b") (CPTYPE V8UQI) VOLATILE)
"cpfsftba0s1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 01001 cpfsftba0s1.b crqp,crpp (p0_1)
(dni cpfsftba0s1_b_P0S "cpfsftba0s1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1_b") (CPTYPE V8QI) VOLATILE)
"cpfsftba0s1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 01010 cpfsftbua0s1.h crqp,crpp (p0_1)
(dni cpfsftbua0s1_h_P0S "cpfsftbua0s1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s1_h") (CPTYPE V4HI) VOLATILE)
"cpfsftbua0s1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 01011 cpfsftbla0s1.h crqp,crpp (p0_1)
(dni cpfsftbla0s1_h_P0S "cpfsftbla0s1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s1_h") (CPTYPE V4HI) VOLATILE)
"cpfsftbla0s1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 01100 cpfaca0s1u.b crqp,crpp (p0_1)
(dni cpfaca0s1u_b_P0S "cpfaca0s1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1u_b") (CPTYPE V8UQI) VOLATILE)
"cpfaca0s1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 01101 cpfaca0s1.b crqp,crpp (p0_1)
(dni cpfaca0s1_b_P0S "cpfaca0s1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1_b") (CPTYPE V8QI) VOLATILE)
"cpfaca0s1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 01110 cpfacua0s1.h crqp,crpp (p0_1)
(dni cpfacua0s1_h_P0S "cpfacua0s1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s1_h") (CPTYPE V4HI) VOLATILE)
"cpfacua0s1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
; 11111 qqqqq ppppp 01111 cpfacla0s1.h crqp,crpp (p0_1)
(dni cpfacla0s1_h_P0S "cpfacla0s1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s1_h") (CPTYPE V4HI) VOLATILE)
"cpfacla0s1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 00000 cpadda1u.b crqp,crpp (p0_1)
(dni cpadda1u_b_P1 "cpadda1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI) VOLATILE)
"cpadda1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 00001 cpadda1.b crqp,crpp (p0_1)
(dni cpadda1_b_P1 "cpadda1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1_b") (CPTYPE V8QI) VOLATILE)
"cpadda1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 00010 cpaddua1.h crqp,crpp (p0_1)
(dni cpaddua1_h_P1 "cpaddua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI) VOLATILE)
"cpaddua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 00011 cpaddla1.h crqp,crpp (p0_1)
(dni cpaddla1_h_P1 "cpaddla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI) VOLATILE)
"cpaddla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 00100 cpaddaca1u.b crqp,crpp (p0_1)
(dni cpaddaca1u_b_P1 "cpaddaca1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI) VOLATILE)
"cpaddaca1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 00101 cpaddaca1.b crqp,crpp (p0_1)
(dni cpaddaca1_b_P1 "cpaddaca1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI) VOLATILE)
"cpaddaca1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 00110 cpaddacua1.h crqp,crpp (p0_1)
(dni cpaddacua1_h_P1 "cpaddacua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI) VOLATILE)
"cpaddacua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 00111 cpaddacla1.h crqp,crpp (p0_1)
(dni cpaddacla1_h_P1 "cpaddacla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI) VOLATILE)
"cpaddacla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 01000 cpsuba1u.b crqp,crpp (p0_1)
(dni cpsuba1u_b_P1 "cpsuba1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI) VOLATILE)
"cpsuba1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 01001 cpsuba1.b crqp,crpp (p0_1)
(dni cpsuba1_b_P1 "cpsuba1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI) VOLATILE)
"cpsuba1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 01010 cpsubua1.h crqp,crpp (p0_1)
(dni cpsubua1_h_P1 "cpsubua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI) VOLATILE)
"cpsubua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 01011 cpsubla1.h crqp,crpp (p0_1)
(dni cpsubla1_h_P1 "cpsubla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI) VOLATILE)
"cpsubla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 01100 cpsubaca1u.b crqp,crpp (p0_1)
(dni cpsubaca1u_b_P1 "cpsubaca1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI) VOLATILE)
"cpsubaca1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 01101 cpsubaca1.b crqp,crpp (p0_1)
(dni cpsubaca1_b_P1 "cpsubaca1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI) VOLATILE)
"cpsubaca1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 01110 cpsubacua1.h crqp,crpp (p0_1)
(dni cpsubacua1_h_P1 "cpsubacua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI) VOLATILE)
"cpsubacua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 01111 cpsubacla1.h crqp,crpp (p0_1)
(dni cpsubacla1_h_P1 "cpsubacla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI) VOLATILE)
"cpsubacla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 10000 cpabsa1u.b crqp,crpp (p0_1)
(dni cpabsa1u_b_P1 "cpabsa1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI) VOLATILE)
"cpabsa1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 10001 cpabsa1.b crqp,crpp (p0_1)
(dni cpabsa1_b_P1 "cpabsa1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI) VOLATILE)
"cpabsa1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 10010 cpabsua1.h crqp,crpp (p0_1)
(dni cpabsua1_h_P1 "cpabsua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI) VOLATILE)
"cpabsua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 10011 cpabsla1.h crqp,crpp (p0_1)
(dni cpabsla1_h_P1 "cpabsla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI) VOLATILE)
"cpabsla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 10100 cpsada1u.b crqp,crpp (p0_1)
(dni cpsada1u_b_P1 "cpsada1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI) VOLATILE)
"cpsada1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 10101 cpsada1.b crqp,crpp (p0_1)
(dni cpsada1_b_P1 "cpsada1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1_b") (CPTYPE V8QI) VOLATILE)
"cpsada1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 10110 cpsadua1.h crqp,crpp (p0_1)
(dni cpsadua1_h_P1 "cpsadua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI) VOLATILE)
"cpsadua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 10111 cpsadla1.h crqp,crpp (p0_1)
(dni cpsadla1_h_P1 "cpsadla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI) VOLATILE)
"cpsadla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 11011 cpseta1.h crqp,crpp (p0_1)
(dni cpseta1_h_P1 "cpseta1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpseta1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpseta1_h") (CPTYPE V4HI) VOLATILE)
"cpseta1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 11100 cpsetua1.w crqp,crpp (p0_1)
(dni cpsetua1_w_P1 "cpsetua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI) VOLATILE)
"cpsetua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11000 qqqqq ppppp 11101 cpsetla1.w crqp,crpp (p0_1)
(dni cpsetla1_w_P1 "cpsetla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI) VOLATILE)
"cpsetla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11001 00000 10000 00000 cpacsuma1 (p0_1)
(dni cpacsuma1_P1 "cpacsuma1 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpacsuma1"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpacsuma1") VOLATILE)
"cpacsuma1"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11001 00000 10001 00000 cpaccpa1 (p0_1)
(dni cpaccpa1_P1 "cpaccpa1 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaccpa1"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaccpa1") VOLATILE)
"cpaccpa1"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11001 qqqqq 11000 00000 cpsrla1 crqp (p0_1)
(dni cpsrla1_P1 "cpsrla1 $crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsrla1"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsrla1") VOLATILE)
"cpsrla1 $crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x18) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11001 qqqqq 11001 00000 cpsraa1 crqp (p0_1)
(dni cpsraa1_P1 "cpsraa1 $crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsraa1"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsraa1") VOLATILE)
"cpsraa1 $crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x19) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11001 qqqqq 11010 00000 cpslla1 crqp (p0_1)
(dni cpslla1_P1 "cpslla1 $crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpslla1"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpslla1") VOLATILE)
"cpslla1 $crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x1a) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11001 00000 11100 iiiii cpsrlia1 imm5p23 (p0_1)
(dni cpsrlia1_1_p1 "cpsrlia1 imm5p23 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsrlia1"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsrlia1") VOLATILE)
"cpsrlia1 $imm5p23"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1c) imm5p23 (f-ivc2-4u28 0))
(sequence ()
; 00000000 11001 00000 11101 iiiii cpsraia1 imm5p23 (p0_1)
(dni cpsraia1_1_p1 "cpsraia1 imm5p23 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsraia1"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsraia1") VOLATILE)
"cpsraia1 $imm5p23"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1d) imm5p23 (f-ivc2-4u28 0))
(sequence ()
; 00000000 11001 00000 11110 iiiii cpsllia1 imm5p23 (p0_1)
(dni cpsllia1_1_p1 "cpsllia1 imm5p23 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsllia1"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsllia1") VOLATILE)
"cpsllia1 $imm5p23"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1e) imm5p23 (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 00000 cpfmulia1s0u.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmulia1s0u_b_P1 "cpfmulia1s0u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0u_b") (CPTYPE V8UQI) VOLATILE)
"cpfmulia1s0u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 00001 cpfmulia1s0.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmulia1s0_b_P1 "cpfmulia1s0.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0_b") (CPTYPE V8QI) VOLATILE)
"cpfmulia1s0.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 00010 cpfmuliua1s0.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmuliua1s0_h_P1 "cpfmuliua1s0.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s0_h") (CPTYPE V4HI) VOLATILE)
"cpfmuliua1s0.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 00011 cpfmulila1s0.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmulila1s0_h_P1 "cpfmulila1s0.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s0_h") (CPTYPE V4HI) VOLATILE)
"cpfmulila1s0.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 00100 cpfmadia1s0u.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmadia1s0u_b_P1 "cpfmadia1s0u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0u_b") (CPTYPE V8UQI) VOLATILE)
"cpfmadia1s0u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 00101 cpfmadia1s0.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmadia1s0_b_P1 "cpfmadia1s0.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0_b") (CPTYPE V8QI) VOLATILE)
"cpfmadia1s0.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 00110 cpfmadiua1s0.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmadiua1s0_h_P1 "cpfmadiua1s0.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s0_h") (CPTYPE V4HI) VOLATILE)
"cpfmadiua1s0.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 00111 cpfmadila1s0.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmadila1s0_h_P1 "cpfmadila1s0.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s0_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s0_h") (CPTYPE V4HI) VOLATILE)
"cpfmadila1s0.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 01000 cpfmulia1s1u.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmulia1s1u_b_P1 "cpfmulia1s1u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1u_b") (CPTYPE V8UQI) VOLATILE)
"cpfmulia1s1u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 01001 cpfmulia1s1.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmulia1s1_b_P1 "cpfmulia1s1.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1_b") (CPTYPE V8QI) VOLATILE)
"cpfmulia1s1.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 01010 cpfmuliua1s1.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmuliua1s1_h_P1 "cpfmuliua1s1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s1_h") (CPTYPE V4HI) VOLATILE)
"cpfmuliua1s1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 01011 cpfmulila1s1.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmulila1s1_h_P1 "cpfmulila1s1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s1_h") (CPTYPE V4HI) VOLATILE)
"cpfmulila1s1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 01100 cpfmadia1s1u.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmadia1s1u_b_P1 "cpfmadia1s1u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1u_b") (CPTYPE V8UQI) VOLATILE)
"cpfmadia1s1u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 01101 cpfmadia1s1.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmadia1s1_b_P1 "cpfmadia1s1.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1_b") (CPTYPE V8QI) VOLATILE)
"cpfmadia1s1.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 01110 cpfmadiua1s1.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmadiua1s1_h_P1 "cpfmadiua1s1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s1_h") (CPTYPE V4HI) VOLATILE)
"cpfmadiua1s1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 01111 cpfmadila1s1.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmadila1s1_h_P1 "cpfmadila1s1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s1_h") (CPTYPE V4HI) VOLATILE)
"cpfmadila1s1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 10000 cpamulia1u.b crqp,crpp,simm8p0 (p0_1)
(dni cpamulia1u_b_P1 "cpamulia1u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1u_b") (CPTYPE V8UQI) VOLATILE)
"cpamulia1u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 10001 cpamulia1.b crqp,crpp,simm8p0 (p0_1)
(dni cpamulia1_b_P1 "cpamulia1.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1_b") (CPTYPE V8QI) VOLATILE)
"cpamulia1.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 10010 cpamuliua1.h crqp,crpp,simm8p0 (p0_1)
(dni cpamuliua1_h_P1 "cpamuliua1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamuliua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamuliua1_h") (CPTYPE V4HI) VOLATILE)
"cpamuliua1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 10011 cpamulila1.h crqp,crpp,simm8p0 (p0_1)
(dni cpamulila1_h_P1 "cpamulila1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulila1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulila1_h") (CPTYPE V4HI) VOLATILE)
"cpamulila1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 10100 cpamadia1u.b crqp,crpp,simm8p0 (p0_1)
(dni cpamadia1u_b_P1 "cpamadia1u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1u_b") (CPTYPE V8UQI) VOLATILE)
"cpamadia1u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 10101 cpamadia1.b crqp,crpp,simm8p0 (p0_1)
(dni cpamadia1_b_P1 "cpamadia1.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1_b") (CPTYPE V8QI) VOLATILE)
"cpamadia1.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 10110 cpamadiua1.h crqp,crpp,simm8p0 (p0_1)
(dni cpamadiua1_h_P1 "cpamadiua1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadiua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadiua1_h") (CPTYPE V4HI) VOLATILE)
"cpamadiua1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11111 qqqqq ppppp 10111 cpamadila1.h crqp,crpp,simm8p0 (p0_1)
(dni cpamadila1_h_P1 "cpamadila1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadila1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadila1_h") (CPTYPE V4HI) VOLATILE)
"cpamadila1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11100 qqqqq ppppp 00 III cpfmulia1u.b crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmulia1u_b_P1 "cpfmulia1u.b $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1u_b") (CPTYPE V8UQI) VOLATILE)
"cpfmulia1u.b $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x0) imm3p25 (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11100 qqqqq ppppp 01 III cpfmulia1.b crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmulia1_b_P1 "cpfmulia1.b $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1_b") (CPTYPE V8QI) VOLATILE)
"cpfmulia1.b $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x1) imm3p25 (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11100 qqqqq ppppp 10 III cpfmuliua1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmuliua1_h_P1 "cpfmuliua1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1_h") (CPTYPE V4HI) VOLATILE)
"cpfmuliua1.h $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x2) imm3p25 (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11100 qqqqq ppppp 11 III cpfmulila1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmulila1_h_P1 "cpfmulila1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1_h") (CPTYPE V4HI) VOLATILE)
"cpfmulila1.h $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x3) imm3p25 (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11101 qqqqq ppppp 00 III cpfmadia1u.b crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmadia1u_b_P1 "cpfmadia1u.b $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1u_b") (CPTYPE V8UQI) VOLATILE)
"cpfmadia1u.b $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x0) imm3p25 (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11101 qqqqq ppppp 01 III cpfmadia1.b crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmadia1_b_P1 "cpfmadia1.b $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1_b") (CPTYPE V8QI) VOLATILE)
"cpfmadia1.b $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x1) imm3p25 (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11101 qqqqq ppppp 10 III cpfmadiua1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmadiua1_h_P1 "cpfmadiua1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1_h") (CPTYPE V4HI) VOLATILE)
"cpfmadiua1.h $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x2) imm3p25 (f-ivc2-4u28 0))
(sequence ()
; iiiiiiii 11101 qqqqq ppppp 11 III cpfmadila1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmadila1_h_P1 "cpfmadila1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1_h") (CPTYPE V4HI) VOLATILE)
"cpfmadila1.h $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x3) imm3p25 (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 00000 cpssqa1u.b crqp,crpp (p0_1)
(dni cpssqa1u_b_P1 "cpssqa1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI) VOLATILE)
"cpssqa1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 00001 cpssqa1.b crqp,crpp (p0_1)
(dni cpssqa1_b_P1 "cpssqa1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI) VOLATILE)
"cpssqa1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 00100 cpssda1u.b crqp,crpp (p0_1)
(dni cpssda1u_b_P1 "cpssda1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI) VOLATILE)
"cpssda1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 00101 cpssda1.b crqp,crpp (p0_1)
(dni cpssda1_b_P1 "cpssda1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1_b") (CPTYPE V8QI) VOLATILE)
"cpssda1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 01000 cpmula1u.b crqp,crpp (p0_1)
(dni cpmula1u_b_P1 "cpmula1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI) VOLATILE)
"cpmula1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 01001 cpmula1.b crqp,crpp (p0_1)
(dni cpmula1_b_P1 "cpmula1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1_b") (CPTYPE V8QI) VOLATILE)
"cpmula1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 01010 cpmulua1.h crqp,crpp (p0_1)
(dni cpmulua1_h_P1 "cpmulua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI) VOLATILE)
"cpmulua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 01011 cpmulla1.h crqp,crpp (p0_1)
(dni cpmulla1_h_P1 "cpmulla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI) VOLATILE)
"cpmulla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 01100 cpmulua1u.w crqp,crpp (p0_1)
(dni cpmulua1u_w_P1 "cpmulua1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI) VOLATILE)
"cpmulua1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 01101 cpmulla1u.w crqp,crpp (p0_1)
(dni cpmulla1u_w_P1 "cpmulla1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI) VOLATILE)
"cpmulla1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 01110 cpmulua1.w crqp,crpp (p0_1)
(dni cpmulua1_w_P1 "cpmulua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI) VOLATILE)
"cpmulua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 01111 cpmulla1.w crqp,crpp (p0_1)
(dni cpmulla1_w_P1 "cpmulla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI) VOLATILE)
"cpmulla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 10000 cpmada1u.b crqp,crpp (p0_1)
(dni cpmada1u_b_P1 "cpmada1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI) VOLATILE)
"cpmada1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 10001 cpmada1.b crqp,crpp (p0_1)
(dni cpmada1_b_P1 "cpmada1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1_b") (CPTYPE V8QI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1_b") (CPTYPE V8QI) VOLATILE)
"cpmada1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 10010 cpmadua1.h crqp,crpp (p0_1)
(dni cpmadua1_h_P1 "cpmadua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI) VOLATILE)
"cpmadua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 10011 cpmadla1.h crqp,crpp (p0_1)
(dni cpmadla1_h_P1 "cpmadla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI) VOLATILE)
"cpmadla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 10100 cpmadua1u.w crqp,crpp (p0_1)
(dni cpmadua1u_w_P1 "cpmadua1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI) VOLATILE)
"cpmadua1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 10101 cpmadla1u.w crqp,crpp (p0_1)
(dni cpmadla1u_w_P1 "cpmadla1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI) VOLATILE)
"cpmadla1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 10110 cpmadua1.w crqp,crpp (p0_1)
(dni cpmadua1_w_P1 "cpmadua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI) VOLATILE)
"cpmadua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 10111 cpmadla1.w crqp,crpp (p0_1)
(dni cpmadla1_w_P1 "cpmadla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI) VOLATILE)
"cpmadla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 11010 cpmsbua1.h crqp,crpp (p0_1)
(dni cpmsbua1_h_P1 "cpmsbua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI) VOLATILE)
"cpmsbua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 11011 cpmsbla1.h crqp,crpp (p0_1)
(dni cpmsbla1_h_P1 "cpmsbla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI) VOLATILE)
"cpmsbla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 11100 cpmsbua1u.w crqp,crpp (p0_1)
(dni cpmsbua1u_w_P1 "cpmsbua1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI) VOLATILE)
"cpmsbua1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 11101 cpmsbla1u.w crqp,crpp (p0_1)
(dni cpmsbla1u_w_P1 "cpmsbla1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI) VOLATILE)
"cpmsbla1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 11110 cpmsbua1.w crqp,crpp (p0_1)
(dni cpmsbua1_w_P1 "cpmsbua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI) VOLATILE)
"cpmsbua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0))
(sequence ()
; 00000000 11110 qqqqq ppppp 11111 cpmsbla1.w crqp,crpp (p0_1)
(dni cpmsbla1_w_P1 "cpmsbla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI) VOLATILE)
"cpmsbla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0))
(sequence ()
; 00000001 11110 qqqqq ppppp 10010 cpsmadua1.h crqp,crpp (p0_1)
(dni cpsmadua1_h_P1 "cpsmadua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI) VOLATILE)
"cpsmadua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
; 00000001 11110 qqqqq ppppp 10011 cpsmadla1.h crqp,crpp (p0_1)
(dni cpsmadla1_h_P1 "cpsmadla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI) VOLATILE)
"cpsmadla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
; 00000001 11110 qqqqq ppppp 10110 cpsmadua1.w crqp,crpp (p0_1)
(dni cpsmadua1_w_P1 "cpsmadua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI) VOLATILE)
"cpsmadua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
; 00000001 11110 qqqqq ppppp 10111 cpsmadla1.w crqp,crpp (p0_1)
(dni cpsmadla1_w_P1 "cpsmadla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI) VOLATILE)
"cpsmadla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
; 00000001 11110 qqqqq ppppp 11010 cpsmsbua1.h crqp,crpp (p0_1)
(dni cpsmsbua1_h_P1 "cpsmsbua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI) VOLATILE)
"cpsmsbua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0))
(sequence ()
; 00000001 11110 qqqqq ppppp 11011 cpsmsbla1.h crqp,crpp (p0_1)
(dni cpsmsbla1_h_P1 "cpsmsbla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI) VOLATILE)
"cpsmsbla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
; 00000001 11110 qqqqq ppppp 11110 cpsmsbua1.w crqp,crpp (p0_1)
(dni cpsmsbua1_w_P1 "cpsmsbua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI) VOLATILE)
"cpsmsbua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0))
(sequence ()
; 00000001 11110 qqqqq ppppp 11111 cpsmsbla1.w crqp,crpp (p0_1)
(dni cpsmsbla1_w_P1 "cpsmsbla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI) VOLATILE)
"cpsmsbla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0))
(sequence ()
; 00000010 11110 qqqqq ppppp 01010 cpmulslua1.h crqp,crpp (p0_1)
(dni cpmulslua1_h_P1 "cpmulslua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI) VOLATILE)
"cpmulslua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
; 00000010 11110 qqqqq ppppp 01011 cpmulslla1.h crqp,crpp (p0_1)
(dni cpmulslla1_h_P1 "cpmulslla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI) VOLATILE)
"cpmulslla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
; 00000010 11110 qqqqq ppppp 01110 cpmulslua1.w crqp,crpp (p0_1)
(dni cpmulslua1_w_P1 "cpmulslua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI) VOLATILE)
"cpmulslua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
; 00000010 11110 qqqqq ppppp 01111 cpmulslla1.w crqp,crpp (p0_1)
(dni cpmulslla1_w_P1 "cpmulslla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI) VOLATILE)
"cpmulslla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
; 00000011 11110 qqqqq ppppp 10010 cpsmadslua1.h crqp,crpp (p0_1)
(dni cpsmadslua1_h_P1 "cpsmadslua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI) VOLATILE)
"cpsmadslua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
; 00000011 11110 qqqqq ppppp 10011 cpsmadslla1.h crqp,crpp (p0_1)
(dni cpsmadslla1_h_P1 "cpsmadslla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI) VOLATILE)
"cpsmadslla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
; 00000011 11110 qqqqq ppppp 10110 cpsmadslua1.w crqp,crpp (p0_1)
(dni cpsmadslua1_w_P1 "cpsmadslua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI) VOLATILE)
"cpsmadslua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
; 00000011 11110 qqqqq ppppp 10111 cpsmadslla1.w crqp,crpp (p0_1)
(dni cpsmadslla1_w_P1 "cpsmadslla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI) VOLATILE)
"cpsmadslla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
; 00000011 11110 qqqqq ppppp 11010 cpsmsbslua1.h crqp,crpp (p0_1)
(dni cpsmsbslua1_h_P1 "cpsmsbslua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI) VOLATILE)
"cpsmsbslua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0))
(sequence ()
; 00000011 11110 qqqqq ppppp 11011 cpsmsbslla1.h crqp,crpp (p0_1)
(dni cpsmsbslla1_h_P1 "cpsmsbslla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI) VOLATILE)
"cpsmsbslla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
; 00000011 11110 qqqqq ppppp 11110 cpsmsbslua1.w crqp,crpp (p0_1)
(dni cpsmsbslua1_w_P1 "cpsmsbslua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI) VOLATILE)
"cpsmsbslua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0))
(sequence ()
; 00000011 11110 qqqqq ppppp 11111 cpsmsbslla1.w crqp,crpp (p0_1)
(dni cpsmsbslla1_w_P1 "cpsmsbslla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI) VOLATILE)
"cpsmsbslla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0))
(sequence ()
/* Functions we call might clobber these. */
if (call_used_regs[r] && !fixed_regs[r])
return true;
+ /* Additional registers that need to be saved for IVC2. */
+ if (TARGET_IVC2
+ && (r == FIRST_CCR_REGNO + 1
+ || (r >= FIRST_CCR_REGNO + 8 && r <= FIRST_CCR_REGNO + 11)
+ || (r >= FIRST_CCR_REGNO + 16 && r <= FIRST_CCR_REGNO + 31)))
+ return true;
+
return false;
}
for (i=6; i<8; i++)
call_used_regs[i+48] = 0;
- call_used_regs[FIRST_CCR_REGNO + 1] = 0;
- fixed_regs[FIRST_CCR_REGNO + 1] = 0;
- for (i=8; i<=11; i++)
- {
- call_used_regs[FIRST_CCR_REGNO + i] = 0;
- fixed_regs[FIRST_CCR_REGNO + i] = 0;
- }
- for (i=16; i<=31; i++)
- {
- call_used_regs[FIRST_CCR_REGNO + i] = 0;
- fixed_regs[FIRST_CCR_REGNO + i] = 0;
- }
-
#define RN(n,s) reg_names[FIRST_CCR_REGNO + n] = s
RN (0, "$csar0");
RN (1, "$cc");
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