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* config/i386/i386.md (*setcc_di_1): New insn_and_split pattern.
authoruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Sun, 11 Oct 2009 12:53:24 +0000 (12:53 +0000)
committeruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Sun, 11 Oct 2009 12:53:24 +0000 (12:53 +0000)
(*setcc_si_1_and): Ditto.
(*setcc_si_1_movzbl): Ditto.
(*setcc_<mode>_2): Ditto.
(*setcc_qi): Rename from *setcc_1.
(*setcc_qi_slp): Rename from *setcc_2.

(*zero_extendqihi2_movzbw_and splitter): Use ix86_expand_clear.
(*zero_extendqisi2_movzbw_and splitter): Ditto.

* config/i386/i386.c (ix86_expand_clear): Remove reload_completed from
"if" condition, there is already assert with reload_completed present.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@152642 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/i386/i386.c
gcc/config/i386/i386.md

index 97e65ae..668a756 100644 (file)
@@ -1,10 +1,24 @@
+2009-10-11  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (*setcc_di_1): New insn_and_split pattern.
+       (*setcc_si_1_and): Ditto.
+       (*setcc_si_1_movzbl): Ditto.
+       (*setcc_<mode>_2): Ditto.
+       (*setcc_qi): Rename from *setcc_1.
+       (*setcc_qi_slp): Rename from *setcc_2.
+
+       (*zero_extendqihi2_movzbw_and splitter): Use ix86_expand_clear.
+       (*zero_extendqisi2_movzbw_and splitter): Ditto.
+
+       * config/i386/i386.c (ix86_expand_clear): Remove reload_completed from
+       "if" condition, there is already assert with reload_completed present.
+
 2009-10-11  Gerald Pfeifer  <gerald@pfeifer.com>
 
-       * plugin.c (try_init_one_plugin): Improve constness of variable
-       err.
+       * plugin.c (try_init_one_plugin): Improve constness of variable err.
 
 2009-10-10  Gerald Pfeifer  <gerald@pfeifer.com>
-       
+
        * doc/install.texi (Final install): Refer to
        http://gcc.gnu.org/bugs/ for bug reporting.
 
index 0d0628b..2a1ed6d 100644 (file)
@@ -12637,7 +12637,7 @@ ix86_expand_clear (rtx dest)
   tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
 
   /* This predicate should match that for movsi_xor and movdi_xor_rex64.  */
-  if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
+  if (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ())
     {
       rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
       tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
index 61bf058..8f2afc4 100644 (file)
    && (TARGET_ZERO_EXTEND_WITH_AND
        && optimize_function_for_speed_p (cfun))
    && !reg_overlap_mentioned_p (operands[0], operands[1])"
-  [(set (match_dup 0) (const_int 0))
-   (set (strict_low_part (match_dup 2)) (match_dup 1))]
-  "operands[2] = gen_lowpart (QImode, operands[0]);")
+  [(set (strict_low_part (match_dup 2)) (match_dup 1))]
+{
+  operands[2] = gen_lowpart (QImode, operands[0]);
+  ix86_expand_clear (operands[0]);
+})
 
 ;; Rest is handled by single and.
 (define_split
   [(set_attr "type" "alu1")
    (set_attr "mode" "SI")])
 
-(define_insn "*zero_extendqisi2_movzbw_and"
+(define_insn "*zero_extendqisi2_movzbl_and"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
      (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
    (clobber (reg:CC FLAGS_REG))]
   [(set_attr "type" "imovx,alu1")
    (set_attr "mode" "SI")])
 
-(define_insn "*zero_extendqisi2_movzbw"
+(define_insn "*zero_extendqisi2_movzbl"
   [(set (match_operand:SI 0 "register_operand" "=r")
      (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
   "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))
    && (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]))
    && (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
    && !reg_overlap_mentioned_p (operands[0], operands[1])"
-  [(set (match_dup 0) (const_int 0))
-   (set (strict_low_part (match_dup 2)) (match_dup 1))]
-  "operands[2] = gen_lowpart (QImode, operands[0]);")
+  [(set (strict_low_part (match_dup 2)) (match_dup 1))]
+{
+  operands[2] = gen_lowpart (QImode, operands[0]);
+  ix86_expand_clear (operands[0]);
+})
 
 ;; Rest is handled by single and.
 (define_split
 ;; For all sCOND expanders, also expand the compare or test insn that
 ;; generates cc0.  Generate an equality comparison if `seq' or `sne'.
 
-;; %%% Do the expansion to SImode.  If PII, do things the xor+setcc way
-;; to avoid partial register stalls.  Otherwise do things the setcc+movzx
-;; way, which can later delete the movzx if only QImode is needed.
+(define_insn_and_split "*setcc_di_1"
+  [(set (match_operand:DI 0 "register_operand" "=q")
+       (match_operator:DI 1 "ix86_comparison_operator"
+         [(reg FLAGS_REG) (const_int 0)]))]
+  "TARGET_64BIT && !TARGET_PARTIAL_REG_STALL"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 2) (match_dup 1))
+   (set (match_dup 0) (zero_extend:DI (match_dup 2)))]
+{
+  PUT_MODE (operands[1], QImode);
+  operands[2] = gen_lowpart (QImode, operands[0]);
+})
+
+(define_insn_and_split "*setcc_si_1_and"
+  [(set (match_operand:SI 0 "register_operand" "=q")
+       (match_operator:SI 1 "ix86_comparison_operator"
+         [(reg FLAGS_REG) (const_int 0)]))
+   (clobber (reg:CC FLAGS_REG))]
+  "!TARGET_PARTIAL_REG_STALL
+   && TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 2) (match_dup 1))
+   (parallel [(set (match_dup 0) (zero_extend:SI (match_dup 2)))
+             (clobber (reg:CC FLAGS_REG))])]
+{
+  PUT_MODE (operands[1], QImode);
+  operands[2] = gen_lowpart (QImode, operands[0]);
+})
+
+(define_insn_and_split "*setcc_si_1_movzbl"
+  [(set (match_operand:SI 0 "register_operand" "=q")
+       (match_operator:SI 1 "ix86_comparison_operator"
+         [(reg FLAGS_REG) (const_int 0)]))]
+  "!TARGET_PARTIAL_REG_STALL
+   && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 2) (match_dup 1))
+   (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
+{
+  PUT_MODE (operands[1], QImode);
+  operands[2] = gen_lowpart (QImode, operands[0]);
+})
+
+(define_insn_and_split "*setcc_<mode>_2"
+  [(set (match_operand:SWI48 0 "register_operand" "=q")
+       (match_operator:SWI48 1 "ix86_comparison_operator"
+         [(reg FLAGS_REG) (const_int 0)]))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_PARTIAL_REG_STALL"
+  "#"
+  "&& reload_completed"
+  [(set (strict_low_part (match_dup 2)) (match_dup 1))]
+{
+  PUT_MODE (operands[1], QImode);
+  operands[2] = gen_lowpart (QImode, operands[0]);
+  ix86_expand_clear (operands[0]);
+})
 
-(define_insn "*setcc_1"
+(define_insn "*setcc_qi"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
        (match_operator:QI 1 "ix86_comparison_operator"
          [(reg FLAGS_REG) (const_int 0)]))]
   [(set_attr "type" "setcc")
    (set_attr "mode" "QI")])
 
-(define_insn "*setcc_2"
+(define_insn "*setcc_qi_slp"
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
        (match_operator:QI 1 "ix86_comparison_operator"
          [(reg FLAGS_REG) (const_int 0)]))]