PR target/44072

	* arm.md (cmpsi2_addneg): Prefer emitting adds to subs with a negative
	immediate.
	* constraints.md (Pw, Px): New constraints.
	* thumb2.md (cmpsi2_addneg peephole2): New peepholes.

	* gcc.target/arm/thumb2-cmpneg2add-1.c: New test.
	* gcc.target/arm/thumb2-cmpneg2add-2.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161040 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3e32486..d885325 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2010-06-19  Richard Earnshaw  <rearnsha@arm.com>
+
+       PR target/44072
+       * arm.md (cmpsi2_addneg): Prefer emitting adds to subs with a negative
+       immediate.
+       * constraints.md (Pw, Px): New constraints.
+       * thumb2.md (cmpsi2_addneg peephole2): New peepholes.
+
 2010-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 
        * config/i386/sse.md (fma4modesuffixf4): Removed.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 628bd62..1608929 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -737,14 +737,14 @@
   [(set (reg:CC CC_REGNUM)
        (compare:CC
         (match_operand:SI 1 "s_register_operand" "r,r")
-        (match_operand:SI 2 "arm_addimm_operand" "I,L")))
+        (match_operand:SI 2 "arm_addimm_operand" "L,I")))
    (set (match_operand:SI 0 "s_register_operand" "=r,r")
        (plus:SI (match_dup 1)
-                (match_operand:SI 3 "arm_addimm_operand" "L,I")))]
+                (match_operand:SI 3 "arm_addimm_operand" "I,L")))]
   "TARGET_32BIT && INTVAL (operands[2]) == -INTVAL (operands[3])"
   "@
-   sub%.\\t%0, %1, %2
-   add%.\\t%0, %1, #%n2"
+   add%.\\t%0, %1, %3
+   sub%.\\t%0, %1, #%n3"
   [(set_attr "conds" "set")]
 )
 

diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index 575d0ac..6d6c77d 100644 (file)
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -31,7 +31,7 @@
 ;; The following multi-letter normal constraints have been used:
 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy
 ;; in Thumb-1 state: Pa, Pb
-;; in Thumb-2 state: Ps, Pt, Pu, Pv
+;; in Thumb-2 state: Ps, Pt, Pu, Pv, Pw, Px
 
 ;; The following memory constraints have been used:
 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
@@ -168,6 +168,16 @@
   (and (match_code "const_int")
        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
 
+(define_constraint "Pw"
+  "@internal In Thumb-2 state a constant in the range -255 to -1"
+  (and (match_code "const_int")
+       (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
+
+(define_constraint "Px"
+  "@internal In Thumb-2 state a constant in the range -7 to -1"
+  (and (match_code "const_int")
+       (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
+
 (define_constraint "G"
  "In ARM/Thumb-2 state a valid FPA immediate constant."
  (and (match_code "const_double")

diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 76a3b98..7045d14 100644 (file)
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -1231,6 +1231,32 @@
    (set_attr "length" "2")]
 )
 
+(define_peephole2
+  [(set (match_operand:CC 0 "cc_register" "")
+       (compare:CC (match_operand:SI 1 "low_register_operand" "")
+                   (match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_THUMB2
+   && peep2_reg_dead_p (1, operands[1])
+   && satisfies_constraint_Pw (operands[2])"
+  [(parallel
+    [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
+     (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
+  "operands[3] = GEN_INT (- INTVAL (operands[2]));"
+)
+
+(define_peephole2
+  [(match_scratch:SI 3 "l")
+   (set (match_operand:CC 0 "cc_register" "")
+       (compare:CC (match_operand:SI 1 "low_register_operand" "")
+                   (match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_THUMB2
+   && satisfies_constraint_Px (operands[2])"
+  [(parallel
+    [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
+     (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
+  "operands[4] = GEN_INT (- INTVAL (operands[2]));"
+)
+
 (define_insn "*thumb2_addsi3_compare0"
   [(set (reg:CC_NOOV CC_REGNUM)
        (compare:CC_NOOV

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 86dcdbb..8f6ad4b 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2010-06-19  Richard Earnshaw  <rearnsha@arm.com>
+
+       PR target/44072
+       * gcc.target/arm/thumb2-cmpneg2add-1.c: New test.
+       * gcc.target/arm/thumb2-cmpneg2add-2.c: New test.
+
 2010-06-19  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
        * g++.dg/ext/label13.C: Fix typo in last change.

diff --git a/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-1.c b/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-1.c
new file mode 100644 (file)
index 0000000..d75f13a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-1.c
@@ -0,0 +1,12 @@
+/* Use ADDS clobbering source operand, rather than CMN */
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "adds" } } */
+/* { dg-final { scan-assembler-not "cmn" } } */
+
+void foo1(void);
+void bar5(int x)
+{
+  if (x == -15)
+    foo1();
+}

diff --git a/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-2.c b/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-2.c
new file mode 100644 (file)
index 0000000..358bc6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-2.c
@@ -0,0 +1,12 @@
+/* Use ADDS with a scratch, rather than CMN */
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "adds" } } */
+/* { dg-final { scan-assembler-not "cmn" } } */
+
+void foo1(int);
+void bar5(int x)
+{
+  if (x == -1)
+    foo1(x);
+}