gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
loc_ref, pc_rtx));
- cy_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (BImode));
+ cy_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, 16));
if (mode == HImode)
vec = gen_rtvec (2, branch, cy_clobber);
void
xstormy16_split_cbranch (enum machine_mode mode, rtx label, rtx comparison,
- rtx dest, rtx carry)
+ rtx dest)
{
rtx op0 = XEXP (comparison, 0);
rtx op1 = XEXP (comparison, 1);
rtx compare;
start_sequence ();
- xstormy16_expand_arith (mode, COMPARE, dest, op0, op1, carry);
+ xstormy16_expand_arith (mode, COMPARE, dest, op0, op1);
seq = get_insns ();
end_sequence ();
&& ! reg_class_subset_p (rclass, EIGHT_REGS))
return EIGHT_REGS;
- /* When reloading a PLUS, the carry register will be required
- unless the inc or dec instructions can be used. */
- if (xstormy16_carry_plus_operand (x, mode))
- return CARRY_REGS;
-
return NO_REGS;
}
#define REG_NEEDS_SAVE(REGNUM, IFUN) \
((df_regs_ever_live_p (REGNUM) && ! call_used_regs[REGNUM]) \
|| (IFUN && ! fixed_regs[REGNUM] && call_used_regs[REGNUM] \
- && (REGNO_REG_CLASS (REGNUM) != CARRY_REGS) \
+ && (REGNUM != CARRY_REGNUM) \
&& (df_regs_ever_live_p (REGNUM) || ! current_function_is_leaf)))
/* Compute the stack layout. */
(set DEST (CODE:MODE SRC0 SRC1))
- using CARRY as a temporary. When CODE is COMPARE, a branch
- template is generated (this saves duplicating code in
- xstormy16_split_cbranch). */
+ When CODE is COMPARE, a branch template is generated
+ (this saves duplicating code in xstormy16_split_cbranch). */
void
xstormy16_expand_arith (enum machine_mode mode, enum rtx_code code,
- rtx dest, rtx src0, rtx src1, rtx carry)
+ rtx dest, rtx src0, rtx src1)
{
int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD;
int i;
continue;
if (firstloop)
- insn = gen_addchi4 (w_dest, w_src0, w_src1, carry);
+ insn = gen_addchi4 (w_dest, w_src0, w_src1);
else
- insn = gen_addchi5 (w_dest, w_src0, w_src1, carry, carry);
+ insn = gen_addchi5 (w_dest, w_src0, w_src1);
break;
case NEG:
rtx branch, sub, clobber, sub_1;
sub_1 = gen_rtx_MINUS (HImode, w_src0,
- gen_rtx_ZERO_EXTEND (HImode, carry));
+ gen_rtx_ZERO_EXTEND (HImode, gen_rtx_REG (BImode, 16)));
sub = gen_rtx_SET (VOIDmode, w_dest,
gen_rtx_MINUS (HImode, sub_1, w_src1));
- clobber = gen_rtx_CLOBBER (VOIDmode, carry);
+ clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, 16));
branch = gen_rtx_SET (VOIDmode, pc_rtx,
gen_rtx_IF_THEN_ELSE (VOIDmode,
gen_rtx_EQ (HImode,
&& GET_CODE (w_src1) == CONST_INT && INTVAL (w_src1) == 0)
continue;
else if (firstloop)
- insn = gen_subchi4 (w_dest, w_src0, w_src1, carry);
+ insn = gen_subchi4 (w_dest, w_src0, w_src1);
else
- insn = gen_subchi5 (w_dest, w_src0, w_src1, carry, carry);
+ insn = gen_subchi5 (w_dest, w_src0, w_src1);
break;
case IOR:
;; d $8
;; e $0..$7
;; t $0..$1
-;; y Carry
;; z $8..$9
;; I 0..3
;; J 2**N mask
;; U -inf..1 or 16..inf
;; Z 0
+(define_constants
+ [
+ (CARRY_REG 16)
+ ]
+)
+
+
\f
;; ::::::::::::::::::::
;; ::
[(set (match_operand:HI 0 "register_operand" "=r,r,r,T,T,r,r,r")
(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,0,0")
(match_operand:HI 2 "xs_hi_nonmemory_operand" "O,P,Z,L,M,Ir,N,i")))
- (clobber (match_scratch:BI 3 "=X,X,X,y,y,y,y,y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"@
inc %0,%o2
add %0,%2"
[(set_attr "length" "2,2,0,2,2,2,2,4")])
-; Reload can generate addition operations. The SECONDARY_RELOAD_CLASS
-; macro causes it to allocate the carry register; this pattern
-; shows it how to place the register in RTL to make the addition work.
-(define_expand "reload_inhi"
- [(parallel [(set (match_operand:HI 0 "register_operand" "=r")
- (match_operand:HI 1 "xstormy16_carry_plus_operand" ""))
- (clobber (match_operand:BI 2 "" "=&y"))])]
- ""
- "if (! rtx_equal_p (operands[0], XEXP (operands[1], 0)))
- {
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], XEXP (operands[1], 0)));
- operands[1] = gen_rtx_PLUS (GET_MODE (operands[1]), operands[0],
- XEXP (operands[1], 1));
- }
- ")
+;; ; Reload can generate addition operations. The SECONDARY_RELOAD_CLASS
+;; ; macro causes it to allocate the carry register; this pattern
+;; ; shows it how to place the register in RTL to make the addition work.
+;; (define_expand "reload_inhi"
+;; [(parallel [(set (match_operand:HI 0 "register_operand" "=r")
+;; (match_operand:HI 1 "xstormy16_carry_plus_operand" ""))
+;; (clobber (reg:BI CARRY_REG))])]
+;; ""
+;; "if (! rtx_equal_p (operands[0], XEXP (operands[1], 0)))
+;; {
+;; emit_insn (gen_rtx_SET (VOIDmode, operands[0], XEXP (operands[1], 0)));
+;; operands[1] = gen_rtx_PLUS (GET_MODE (operands[1]), operands[0],
+;; XEXP (operands[1], 1));
+;; }
+;; ")
(define_insn "addchi4"
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
- (set (match_operand:BI 3 "register_operand" "=y,y,y")
+ (set (reg:BI CARRY_REG)
(truncate:BI (lshiftrt:SI (plus:SI (zero_extend:SI (match_dup 1))
(zero_extend:SI (match_dup 2)))
(const_int 16))))]
(define_insn "addchi5"
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
(plus:HI (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
- (zero_extend:HI (match_operand:BI 3
- "register_operand"
- "y,y,y")))
+ (zero_extend:HI (reg:BI CARRY_REG)))
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
- (set (match_operand:BI 4 "register_operand" "=y,y,y")
+ (set (reg:BI CARRY_REG)
(truncate:BI (lshiftrt:SI (plus:SI (plus:SI
(zero_extend:SI (match_dup 1))
- (zero_extend:SI (match_dup 3)))
+ (zero_extend:SI (reg:BI CARRY_REG)))
(zero_extend:SI (match_dup 2)))
(const_int 16))))]
""
[(set (match_operand:HI 0 "register_operand" "=r,r,T,T,r,r,r")
(minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,0,0")
(match_operand:HI 2 "xs_hi_nonmemory_operand" "O,P,L,M,rI,M,i")))
- (clobber (match_scratch:BI 3 "=X,X,&y,&y,&y,&y,&y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"@
dec %0,%o2
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
(minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
- (set (match_operand:BI 3 "register_operand" "=y,y,y")
+ (set (reg:BI CARRY_REG)
(truncate:BI (lshiftrt:SI (minus:SI (zero_extend:SI (match_dup 1))
(zero_extend:SI (match_dup 2)))
(const_int 16))))]
(define_insn "subchi5"
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
(minus:HI (minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
- (zero_extend:HI (match_operand:BI 3
- "register_operand"
- "y,y,y")))
+ (zero_extend:HI (reg:BI CARRY_REG)))
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
- (set (match_operand:BI 4 "register_operand" "=y,y,y")
+ (set (reg:BI CARRY_REG)
(truncate:BI (lshiftrt:SI (minus:SI (minus:SI
(zero_extend:SI (match_dup 1))
- (zero_extend:SI (match_dup 3)))
+ (zero_extend:SI (reg:BI CARRY_REG)))
(zero_extend:SI (match_dup 2)))
(const_int 16))))]
""
[(set (match_operand:HI 0 "register_operand" "")
(not:HI (match_operand:HI 1 "register_operand" "")))
(parallel [(set (match_dup 0) (plus:HI (match_dup 0) (const_int 1)))
- (clobber (match_scratch:BI 3 ""))])]
+ (clobber (reg:BI CARRY_REG))])]
""
"")
[(set (match_operand:HI 0 "register_operand" "=r")
(ashift:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "nonmemory_operand" "ri")))
- (clobber (match_scratch:BI 3 "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"shl %0,%2")
[(set (match_operand:HI 0 "register_operand" "=r")
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "nonmemory_operand" "ri")))
- (clobber (match_scratch:BI 3 "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"asr %0,%2")
[(set (match_operand:HI 0 "register_operand" "=r")
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "nonmemory_operand" "ri")))
- (clobber (match_scratch:BI 3 "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"shr %0,%2")
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "nonmemory_operand" "ri")))
- (clobber (match_scratch:BI 3 "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"#"
"reload_completed"
[(pc)]
"{ xstormy16_expand_arith (SImode, PLUS, operands[0], operands[1],
- operands[2], operands[3]); DONE; } "
+ operands[2]); DONE; } "
[(set_attr "length" "4")])
;; Subtraction
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "ri")))
- (clobber (match_scratch:BI 3 "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"#"
"reload_completed"
[(pc)]
"{ xstormy16_expand_arith (SImode, MINUS, operands[0], operands[1],
- operands[2], operands[3]); DONE; } "
+ operands[2]); DONE; } "
[(set_attr "length" "4")])
(define_expand "negsi2"
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(neg:SI (match_operand:SI 1 "register_operand" "")))
- (clobber (match_scratch:BI 2 ""))])]
+ (clobber (reg:BI CARRY_REG))])]
""
- "{ operands[2] = gen_reg_rtx (HImode);
- operands[3] = gen_reg_rtx (BImode); }")
+ "{ operands[2] = gen_reg_rtx (HImode); }")
(define_insn_and_split "*negsi2_internal"
[(set (match_operand:SI 0 "register_operand" "=&r")
(neg:SI (match_operand:SI 1 "register_operand" "r")))
- (clobber (match_scratch:BI 2 "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"#"
"reload_completed"
[(pc)]
"{ xstormy16_expand_arith (SImode, NEG, operands[0], operands[0],
- operands[1], operands[2]); DONE; }")
+ operands[1]); DONE; }")
;; ::::::::::::::::::::
;; ::
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(ashift:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
- (clobber (match_dup 3))
- (clobber (match_dup 4))])]
+ (clobber (reg:BI CARRY_REG))
+ (clobber (match_dup 3))])]
""
- " if (! const_int_operand (operands[2], SImode)) FAIL;
- operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
+ " if (! const_int_operand (operands[2], SImode))
+ FAIL;
+ operands[3] = gen_reg_rtx (HImode); ")
;; Arithmetic Shift Right
(define_expand "ashrsi3"
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
- (clobber (match_dup 3))
- (clobber (match_dup 4))])]
+ (clobber (reg:BI CARRY_REG))
+ (clobber (match_dup 3))])]
""
- " if (! const_int_operand (operands[2], SImode)) FAIL;
- operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
+ " if (! const_int_operand (operands[2], SImode))
+ FAIL;
+ operands[3] = gen_reg_rtx (HImode); ")
;; Logical Shift Right
(define_expand "lshrsi3"
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
- (clobber (match_dup 3))
- (clobber (match_dup 4))])]
+ (clobber (reg:BI CARRY_REG))
+ (clobber (match_dup 3))])]
""
- " if (! const_int_operand (operands[2], SImode)) FAIL;
- operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
+ " if (! const_int_operand (operands[2], SImode))
+ FAIL;
+ operands[3] = gen_reg_rtx (HImode); ")
(define_insn "*shiftsi"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (match_operator:SI 5 "shift_operator"
+ (match_operator:SI 4 "shift_operator"
[(match_operand:SI 1 "register_operand" "0,0")
(match_operand:SI 2 "const_int_operand" "U,n")]))
- (clobber (match_operand:BI 3 "register_operand" "=y,y"))
- (clobber (match_operand:HI 4 "" "=X,r"))]
+ (clobber (reg:BI CARRY_REG))
+ (clobber (match_operand:HI 3 "" "=X,r"))]
""
- "* return xstormy16_output_shift (SImode, GET_CODE (operands[5]),
- operands[0], operands[2], operands[4]);"
+ "* return xstormy16_output_shift (SImode, GET_CODE (operands[4]),
+ operands[0], operands[2], operands[3]);"
[(set_attr "length" "6,10")
(set_attr "psw_operand" "clobber,clobber")])
"r,L,e")])
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"*
{
"r,L,e")])
(pc)
(label_ref (match_operand 0 "" ""))))
- (clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"*
{
"ri")])
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:SI 5 "register_operand" "=2"))
- (clobber (match_operand:BI 4 "" "=&y"))]
+ (clobber (match_operand:SI 4 "register_operand" "=2"))
+ (clobber (reg:BI CARRY_REG))]
""
"#"
"reload_completed"
[(pc)]
- "{ xstormy16_split_cbranch (SImode, operands[0], operands[1], operands[2],
- operands[4]); DONE; }"
+ "{ xstormy16_split_cbranch (SImode, operands[0], operands[1], operands[2]); DONE; }"
[(set_attr "length" "8")])
(define_insn "*ineqbranch_1"
[(set (pc)
- (if_then_else (match_operator:HI 5 "xstormy16_ineqsi_operator"
- [(minus:HI (match_operand:HI 1 "register_operand"
- "T,r,r")
- (zero_extend:HI (match_operand:BI 4
- "register_operand"
- "y,y,y")))
+ (if_then_else (match_operator:HI 4 "xstormy16_ineqsi_operator"
+ [(minus:HI (match_operand:HI 1 "register_operand" "T,r,r")
+ (zero_extend:HI (reg:BI CARRY_REG)))
(match_operand:HI 3 "nonmemory_operand" "L,Ir,i")])
(label_ref (match_operand 0 "" ""))
(pc)))
(set (match_operand:HI 2 "register_operand" "=1,1,1")
- (minus:HI (minus:HI (match_dup 1) (zero_extend:HI (match_dup 4)))
+ (minus:HI (minus:HI (match_dup 1) (zero_extend:HI (reg:BI CARRY_REG)))
(match_dup 3)))
- (clobber (match_operand:BI 6 "" "=y,y,y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"*
{
- return xstormy16_output_cbranch_si (operands[5], \"%l0\", 0, insn);
+ return xstormy16_output_cbranch_si (operands[4], \"%l0\", 0, insn);
}"
[(set_attr "branch_class" "bcc8p2,bcc8p2,bcc8p4")
(set_attr "psw_operand" "2,2,2")])
;; Indirect jump through a register
(define_expand "indirect_jump"
[(set (match_dup 1) (const_int 0))
- (parallel [(set (pc) (match_operand:HI 0 "register_operand" "r"))
+ (parallel [(set (pc) (match_operand:HI 0 "register_operand" ""))
(use (match_dup 1))])]
""
"operands[1] = gen_reg_rtx (HImode);")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 3 "" "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"bn %1,%B2,%l0"
[(set_attr "length" "4")
(match_operand:HI 3 "immediate_operand" "i"))
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 4 "" "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"bn %1,%B2,%l0"
[(set_attr "length" "4")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 3 "" "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"bn %1,%B2,%l0"
[(set_attr "length" "4")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 2 "" "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"bn %1,#7,%l0"
[(set_attr "length" "4")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 2 "" "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"bn %1,#7,%l0"
[(set_attr "length" "4")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 3 "" "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"bp %1,%B2,%l0"
[(set_attr "length" "4")
(match_operand:HI 2 "immediate_operand" "i"))
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 3 "" "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"bp %1,%b2,%l0"
[(set_attr "length" "4")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 3 "" "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"bp %1,%B2,%l0"
[(set_attr "length" "4")
(const_int 7))
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 2 "" "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"bp %1,#7,%l0"
[(set_attr "length" "4")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
- (clobber (match_operand:BI 2 "" "=y"))]
+ (clobber (reg:BI CARRY_REG))]
""
"bp %1,#7,%l0"
[(set_attr "length" "4")