-(define_insn "*ashr<mode>3_1"
- [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
- (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "c<S>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)"
-{
- if (REG_P (operands[2]))
- return "sar{<imodesuffix>}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{<imodesuffix>}\t%0";
- else
- return "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "ishift")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*ashrsi3_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "cI"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-{
- if (REG_P (operands[2]))
- return "sar{l}\t{%b2, %k0|%k0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{l}\t%k0";
- else
- return "sar{l}\t{%2, %k0|%k0, %2}";
-}
- [(set_attr "type" "ishift")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "SI")])
-
-(define_insn "*ashrqi3_1_slp"
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
- (ashiftrt:QI (match_dup 0)
- (match_operand:QI 1 "nonmemory_operand" "cI")))
- (clobber (reg:CC FLAGS_REG))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_REG_STALL
- || (operands[1] == const1_rtx
- && TARGET_SHIFT1))"
-{
- if (REG_P (operands[1]))
- return "sar{b}\t{%b1, %0|%0, %b1}";
- else if (operands[1] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{b}\t%0";
- else
- return "sar{b}\t{%1, %0|%0, %1}";
-}
- [(set_attr "type" "ishift1")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 1 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "QI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashr<mode>3_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
- (const_int 0)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
- (ashiftrt:SWI (match_dup 1) (match_dup 2)))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && TARGET_SHIFT1))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)"
-{
- if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{<imodesuffix>}\t%0";
- else
- return "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "ishift")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*ashrsi3_cmp_zext"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT
- && (optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && TARGET_SHIFT1))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-{
- if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{l}\t%k0";
- else
- return "sar{l}\t{%2, %k0|%k0, %2}";
-}
- [(set_attr "type" "ishift")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "SI")])
-
-(define_insn "*ashr<mode>3_cconly"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
- (const_int 0)))
- (clobber (match_scratch:SWI 0 "=<r>"))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && TARGET_SHIFT1))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)"
-{
- if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{<imodesuffix>}\t%0";
- else
- return "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "ishift")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "<MODE>")])
-\f
-;; Logical shift instructions
-
-;; See comment above `ashldi3' about how this works.
-
-(define_expand "lshr<mode>3"
- [(set (match_operand:SDWIM 0 "<shift_operand>" "")
- (lshiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- ""
- "ix86_expand_binary_operator (LSHIFTRT, <MODE>mode, operands); DONE;")
-
-(define_insn_and_split "*lshr<mode>3_doubleword"
- [(set (match_operand:DWI 0 "register_operand" "=r")
- (lshiftrt:DWI (match_operand:DWI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "<S>c")))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "#"
- "(optimize && flag_peephole2) ? epilogue_completed : reload_completed"
- [(const_int 0)]
- "ix86_split_lshr (operands, NULL_RTX, <MODE>mode); DONE;"
- [(set_attr "type" "multi")])
-
-;; By default we don't ask for a scratch register, because when DWImode
-;; values are manipulated, registers are already at a premium. But if
-;; we have one handy, we won't turn it away.
-
-(define_peephole2
- [(match_scratch:DWIH 3 "r")
- (parallel [(set (match_operand:<DWI> 0 "register_operand" "")
- (lshiftrt:<DWI>
- (match_operand:<DWI> 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))])
- (match_dup 3)]
- "TARGET_CMOVE"
- [(const_int 0)]
- "ix86_split_lshr (operands, operands[3], <DWI>mode); DONE;")
-
-(define_insn "*lshr<mode>3_1"