Backport from mainline

	2012-04-23  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (*add<mode>_2): Add r/r/0 alternative.
	(*addsi_2_zext): Ditto.
	(*add<mode>_3): Ditto.
	(*addsi_3_zext): Ditto.
	(*add<mode>_5): Ditto.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@186842 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 37f23f8..4f3d3ed 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2012-04-26  Uros Bizjak  <ubizjak@gmail.com>
+
+       Backport from mainline
+       2012-04-23  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (*add<mode>_2): Add r/r/0 alternative.
+       (*addsi_2_zext): Ditto.
+       (*add<mode>_3): Ditto.
+       (*addsi_3_zext): Ditto.
+       (*add<mode>_5): Ditto.
+

 2012-04-25  Jakub Jelinek  <jakub@redhat.com>
 
        PR c/52880
 2012-04-25  Jakub Jelinek  <jakub@redhat.com>
 
        PR c/52880

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 7f5a9e0..9aa5c6c 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5811,10 +5811,10 @@
   [(set (reg FLAGS_REG)
        (compare
          (plus:SWI
   [(set (reg FLAGS_REG)
        (compare
          (plus:SWI

-           (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
-           (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))
+           (match_operand:SWI 1 "nonimmediate_operand" "%0,0,<r>")
+           (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>,0"))

          (const_int 0)))
          (const_int 0)))

-   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m")
+   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m,<r>")

        (plus:SWI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
    && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
        (plus:SWI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
    && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"


@@ -5831,6 +5831,13 @@
        }
 
     default:
        }
 
     default:

+      if (which_alternative == 2)
+       {
+         rtx tmp;
+         tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+       }
+        
+      gcc_assert (rtx_equal_p (operands[0], operands[1]));

       if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
         return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
 
       if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
         return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
 


@@ -5852,10 +5859,10 @@
 (define_insn "*addsi_2_zext"
   [(set (reg FLAGS_REG)
        (compare
 (define_insn "*addsi_2_zext"
   [(set (reg FLAGS_REG)
        (compare

-         (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-                  (match_operand:SI 2 "x86_64_general_operand" "rme"))
+         (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
+                  (match_operand:SI 2 "x86_64_general_operand" "rme,0"))

          (const_int 0)))
          (const_int 0)))

-   (set (match_operand:DI 0 "register_operand" "=r")
+   (set (match_operand:DI 0 "register_operand" "=r,r")

        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
    && ix86_binary_operator_ok (PLUS, SImode, operands)"
        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
    && ix86_binary_operator_ok (PLUS, SImode, operands)"


@@ -5872,6 +5879,12 @@
        }
 
     default:
        }
 
     default:

+      if (which_alternative == 1)
+       {
+         rtx tmp;
+         tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+       }
+

       if (x86_maybe_negate_const_int (&operands[2], SImode))
         return "sub{l}\t{%2, %k0|%k0, %2}";
 
       if (x86_maybe_negate_const_int (&operands[2], SImode))
         return "sub{l}\t{%2, %k0|%k0, %2}";
 


@@ -5892,9 +5905,9 @@
 (define_insn "*add<mode>_3"
   [(set (reg FLAGS_REG)
        (compare
 (define_insn "*add<mode>_3"
   [(set (reg FLAGS_REG)
        (compare

-         (neg:SWI (match_operand:SWI 2 "<general_operand>" "<g>"))
-         (match_operand:SWI 1 "nonimmediate_operand" "%0")))
-   (clobber (match_scratch:SWI 0 "=<r>"))]
+         (neg:SWI (match_operand:SWI 2 "<general_operand>" "<g>,0"))
+         (match_operand:SWI 1 "nonimmediate_operand" "%0,<r>")))
+   (clobber (match_scratch:SWI 0 "=<r>,<r>"))]

   "ix86_match_ccmode (insn, CCZmode)
    && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
 {
   "ix86_match_ccmode (insn, CCZmode)
    && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
 {


@@ -5910,6 +5923,13 @@
        }
 
     default:
        }
 
     default:

+      if (which_alternative == 1)
+       {
+         rtx tmp;
+         tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+       }
+
+      gcc_assert (rtx_equal_p (operands[0], operands[1]));

       if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
         return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
 
       if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
         return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
 


@@ -5931,9 +5951,9 @@
 (define_insn "*addsi_3_zext"
   [(set (reg FLAGS_REG)
        (compare
 (define_insn "*addsi_3_zext"
   [(set (reg FLAGS_REG)
        (compare

-         (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme"))
-         (match_operand:SI 1 "nonimmediate_operand" "%0")))
-   (set (match_operand:DI 0 "register_operand" "=r")
+         (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
+         (match_operand:SI 1 "nonimmediate_operand" "%0,r")))
+   (set (match_operand:DI 0 "register_operand" "=r,r")

        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
    && ix86_binary_operator_ok (PLUS, SImode, operands)"
        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
    && ix86_binary_operator_ok (PLUS, SImode, operands)"


@@ -5950,6 +5970,12 @@
        }
 
     default:
        }
 
     default:

+      if (which_alternative == 1)
+       {
+         rtx tmp;
+         tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+       }
+

       if (x86_maybe_negate_const_int (&operands[2], SImode))
         return "sub{l}\t{%2, %k0|%k0, %2}";
 
       if (x86_maybe_negate_const_int (&operands[2], SImode))
         return "sub{l}\t{%2, %k0|%k0, %2}";
 


@@ -6060,10 +6086,10 @@
   [(set (reg FLAGS_REG)
        (compare
          (plus:SWI
   [(set (reg FLAGS_REG)
        (compare
          (plus:SWI

-           (match_operand:SWI 1 "nonimmediate_operand" "%0")
-           (match_operand:SWI 2 "<general_operand>" "<g>"))
+           (match_operand:SWI 1 "nonimmediate_operand" "%0,<r>")
+           (match_operand:SWI 2 "<general_operand>" "<g>,0"))

          (const_int 0)))
          (const_int 0)))

-   (clobber (match_scratch:SWI 0 "=<r>"))]
+   (clobber (match_scratch:SWI 0 "=<r>,<r>"))]

   "ix86_match_ccmode (insn, CCGOCmode)
    && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
 {
   "ix86_match_ccmode (insn, CCGOCmode)
    && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
 {


@@ -6079,6 +6105,13 @@
        }
 
     default:
        }
 
     default:

+      if (which_alternative == 1)
+       {
+         rtx tmp;
+         tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+       }
+
+      gcc_assert (rtx_equal_p (operands[0], operands[1]));

       if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
         return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
 
       if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
         return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";