(define_code_iterator maxmin [smax smin umax umin])
;; Base name for integer and FP insn mnemonic
-(define_code_attr maxminiprefix [(smax "maxs") (smin "mins")
- (umax "maxu") (umin "minu")])
-(define_code_attr maxminfprefix [(smax "max") (smin "min")])
+(define_code_attr maxmin_int [(smax "maxs") (smin "mins")
+ (umax "maxu") (umin "minu")])
+(define_code_attr maxmin_float [(smax "max") (smin "min")])
;; Mapping of logic operators
(define_code_iterator any_logic [and ior xor])
(define_code_iterator any_or [ior xor])
;; Base name for insn mnemonic.
-(define_code_attr logicprefix [(and "and") (ior "or") (xor "xor")])
+(define_code_attr logic [(and "and") (ior "or") (xor "xor")])
;; Mapping of shift-right operators
(define_code_iterator any_shiftrt [lshiftrt ashiftrt])
(define_code_iterator absneg [abs neg])
;; Base name for x87 insn mnemonic.
-(define_code_attr absnegprefix [(abs "abs") (neg "chs")])
+(define_code_attr absneg_mnemonic [(abs "abs") (neg "chs")])
;; Used in signed and unsigned widening multiplications.
(define_code_iterator any_extend [sign_extend zero_extend])
(match_operand:SWI248 2 "<general_operand>" "<g>,r<i>")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
+ "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, QImode, operands)"
"@
- <logicprefix>{b}\t{%2, %0|%0, %2}
- <logicprefix>{b}\t{%2, %0|%0, %2}
- <logicprefix>{l}\t{%k2, %k0|%k0, %k2}"
+ <logic>{b}\t{%2, %0|%0, %2}
+ <logic>{b}\t{%2, %0|%0, %2}
+ <logic>{l}\t{%k2, %k0|%k0, %k2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI,QI,SI")])
(match_operand:SI 2 "general_operand" "g"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
+ "<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
+ "<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(clobber (reg:CC FLAGS_REG))]
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "<logicprefix>{b}\t{%1, %0|%0, %1}"
+ "<logic>{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
(any_or:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
+ "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(zero_extend:DI (any_or:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
+ "<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(any_or:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
+ "<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCNOmode)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "<logicprefix>{b}\t{%1, %0|%0, %1}"
+ "<logic>{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
(clobber (match_scratch:SWI 0 "=<r>"))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
+ "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(match_operand 2 "const_int_operand" "n")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
- "<logicprefix>{b}\t{%2, %h0|%h0, %2}"
+ "<logic>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
(set_attr "modrm" "1")
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
- "<logicprefix>{b}\t{%2, %h0|%h0, %2}"
+ "<logic>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
- "<logicprefix>{b}\t{%2, %h0|%h0, %2}"
+ "<logic>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(const_int 8))))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
- "<logicprefix>{b}\t{%h2, %h0|%h0, %h2}"
+ "<logic>{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
"TARGET_80387
&& (reload_completed
|| !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
- "f<absnegprefix>"
+ "f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "<MODE>")])
(absneg:DF (float_extend:DF
(match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
- "f<absnegprefix>"
+ "f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "DF")])
(absneg:XF (float_extend:XF
(match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387"
- "f<absnegprefix>"
+ "f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
(define_insn "*<code>extenddfxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(absneg:XF (float_extend:XF
- (match_operand:DF 1 "register_operand" "0"))))]
+ (match_operand:DF 1 "register_operand" "0"))))]
"TARGET_80387"
- "f<absnegprefix>"
+ "f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
(match_operand:MODEF 1 "nonimmediate_operand" "%x")
(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
"AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
- "v<maxminfprefix>s<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
+ "v<maxmin_float>s<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
(match_operand:MODEF 1 "nonimmediate_operand" "%0")
(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
- "<maxminfprefix>s<ssemodefsuffix>\t{%2, %0|%0, %2}"
+ "<maxmin_float>s<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
return "vmovaps\t{%1, %0|%0, %1}";
case MODE_V4DF:
case MODE_V2DF:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "vmovaps\t{%1, %0|%0, %1}";
- else
- return "vmovapd\t{%1, %0|%0, %1}";
+ return "vmovapd\t{%1, %0|%0, %1}";
default:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "vmovaps\t{%1, %0|%0, %1}";
- else
- return "vmovdqa\t{%1, %0|%0, %1}";
+ return "vmovdqa\t{%1, %0|%0, %1}";
}
default:
gcc_unreachable ();
case MODE_V4SF:
return "movaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movapd\t{%1, %0|%0, %1}";
+ return "movapd\t{%1, %0|%0, %1}";
default:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movdqa\t{%1, %0|%0, %1}";
+ return "movdqa\t{%1, %0|%0, %1}";
}
default:
gcc_unreachable ();
(set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
-(define_insn "*avx_vmmaskcmp<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (match_operator:SSEMODEF2P 3 "sse_comparison_operator"
- [(match_operand:SSEMODEF2P 1 "register_operand" "x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")])
- (match_dup 1)
- (const_int 1)))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
- "vcmp%D3s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix" "vex")
- (set_attr "mode" "<ssescalarmode>")])
-
(define_insn "<sse>_vmmaskcmp<mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(vec_merge:SSEMODEF2P
(match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
"AVX_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-{
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}";
- else
- return "v<logic>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}";
-}
+ "v<logic>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-{
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "<logic>ps\t{%2, %0|%0, %2}";
- else
- return "<logic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}";
-}
+ "<logic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<MODE>")])
(match_operand:MODEF 1 "register_operand" "x")
(match_operand:MODEF 2 "register_operand" "x")))]
"AVX_FLOAT_MODE_P (<MODE>mode)"
-{
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "v<logic>ps\t{%2, %1, %0|%0, %1, %2}";
- else
- return "v<logic>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}";
-}
+ "v<logic>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<ssevecmode>")])
(match_operand:MODEF 1 "register_operand" "0")
(match_operand:MODEF 2 "register_operand" "x")))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
-{
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "<logic>ps\t{%2, %0|%0, %2}";
- else
- return "<logic>p<ssemodefsuffix>\t{%2, %0|%0, %2}";
-}
+ "<logic>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "<ssevecmode>")])