;; Main data type used by the insn
(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
-;; # instructions (4 bytes each)
-(define_attr "length" "" (const_int 1))
+;; Length (in # of bytes). A conditional branch is allowed only to a
+;; location within a signed 18-bit offset of the delay slot. If that
+;; provides too smal a range, we use the `j' instruction. This
+;; instruction takes a 28-bit value, but that value is not an offset.
+;; Instead, it's bitwise-ored with the high-order four bits of the
+;; instruction in the delay slot, which means it cannot be used to
+;; cross a 256MB boundary. We could fall back back on the jr,
+;; instruction which allows full access to the entire address space,
+;; but we do not do so at present.
+
+(define_attr "length" ""
+ (cond [(eq_attr "type" "branch")
+ (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
+ (const_int 131072))
+ (const_int 4)]
+ (const_int 12))]
+ (const_int 4)))
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(const (symbol_ref "mips_cpu_attr")))
;; Does the instruction have a mandatory delay slot?
-;; The 3900, is (mostly) mips1, but does not have a manditory load delay
+;; The 3900, is (mostly) mips1, but does not have a mandatory load delay
;; slot.
(define_attr "dslot" "no,yes"
(if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp")
(define_delay (and (eq_attr "type" "branch")
(eq (symbol_ref "mips16") (const_int 0)))
- [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
+ [(and (eq_attr "dslot" "no") (eq_attr "length" "4"))
(nil)
- (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "1")))])
+ (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "4")))])
(define_delay (eq_attr "type" "jump")
- [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
+ [(and (eq_attr "dslot" "no") (eq_attr "length" "4"))
(nil)
(nil)])
(define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no"))
- [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
+ [(and (eq_attr "dslot" "no") (eq_attr "length" "4"))
(nil)
(nil)])
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"add.d\\t%0,%1,%2"
[(set_attr "type" "fadd")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn "addsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
"TARGET_HARD_FLOAT"
"add.s\\t%0,%1,%2"
[(set_attr "type" "fadd")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_expand "addsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
|| INTVAL (operands[2]) != -32768)"
"addu\\t%0,%z1,%2"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
;; For the mips16, we need to recognize stack pointer additions
;; explicitly, since we don't have a constraint for $sp. These insns
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set (attr "length") (if_then_else (match_operand:VOID 1 "m16_uimm8_4" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
- (const_int 1)
- (const_int 2))
+ (const_int 4)
+ (const_int 8))
(if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
- (const_int 1)
- (const_int 2))
- (const_int 1)])])
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)])])
;; On the mips16, we can sometimes split an add of a constant which is
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "4")])
+ (set_attr "length" "16")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "3,2,4")])
+ (set_attr "length" "12,8,16")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
: \"daddu\\t%0,%z1,%2\";
}"
[(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
;; For the mips16, we need to recognize stack pointer additions
;; explicitly, since we don't have a constraint for $sp. These insns
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set (attr "length") (if_then_else (match_operand:VOID 0 "m16_uimm5_4" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(if_then_else (match_operand:VOID 2 "m16_simm5_1" "")
- (const_int 1)
- (const_int 2))
+ (const_int 4)
+ (const_int 8))
(if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
- (const_int 1)
- (const_int 2))
- (const_int 1)])])
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)])])
;; On the mips16, we can sometimes split an add of a constant which is
: \"addu\\t%0,%z1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
- (const_int 1)
- (const_int 2))
+ (const_int 4)
+ (const_int 8))
(if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
- (const_int 1)
- (const_int 2))
- (const_int 1)])])
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)])])
\f
;;
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sub.d\\t%0,%1,%2"
[(set_attr "type" "fadd")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn "subsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
"TARGET_HARD_FLOAT"
"sub.s\\t%0,%1,%2"
[(set_attr "type" "fadd")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_expand "subsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
&& (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
"subu\\t%0,%z1,%2"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
;; For the mips16, we need to recognize stack pointer subtractions
;; explicitly, since we don't have a constraint for $sp. These insns
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set (attr "length") (if_then_else (match_operand:VOID 1 "m16_nuimm8_4" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
- (const_int 1)
- (const_int 2))
+ (const_int 4)
+ (const_int 8))
(if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
- (const_int 1)
- (const_int 2))
- (const_int 1)])])
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)])])
;; On the mips16, we can sometimes split an subtract of a constant
;; which is a 4 byte instruction into two adds which are both 2 byte
"sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "4")])
+ (set_attr "length" "16")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "3,2,4")])
+ (set_attr "length" "12,8,16")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
: \"dsubu\\t%0,%z1,%2\";
}"
[(set_attr "type" "darith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
;; For the mips16, we need to recognize stack pointer subtractions
;; explicitly, since we don't have a constraint for $sp. These insns
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nuimm5_4" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(if_then_else (match_operand:VOID 2 "m16_nsimm5_1" "")
- (const_int 1)
- (const_int 2))
+ (const_int 4)
+ (const_int 8))
(if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
- (const_int 1)
- (const_int 2))
- (const_int 1)])])
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)])])
;; On the mips16, we can sometimes split an add of a constant which is
;; a 4 byte instruction into two adds which are both 2 byte
: \"subu\\t%0,%z1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
- (const_int 1)
- (const_int 2))
+ (const_int 4)
+ (const_int 8))
(if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
- (const_int 1)
- (const_int 2))
- (const_int 1)])])
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)])])
\f
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300"
"mul.d\\t%0,%1,%2"
[(set_attr "type" "fmul")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn "muldf3_r4300"
[(set (match_operand:DF 0 "register_operand" "=f")
}"
[(set_attr "type" "fmul")
(set_attr "mode" "DF")
- (set_attr "length" "2")]) ;; mul.d + nop
+ (set_attr "length" "8")]) ;; mul.d + nop
(define_expand "mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
"TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300"
"mul.s\\t%0,%1,%2"
[(set_attr "type" "fmul")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn "mulsf3_r4300"
[(set (match_operand:SF 0 "register_operand" "=f")
}"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")
- (set_attr "length" "2")]) ;; mul.s + nop
+ (set_attr "length" "8")]) ;; mul.s + nop
;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
return \"mult\\t%0,%1,%2\";
}"
[(set_attr "type" "imul")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "mulsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=l")
"mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16"
"mult\\t%1,%2"
[(set_attr "type" "imul")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "mulsi3_r4000"
[(set (match_operand:SI 0 "register_operand" "=d")
}"
[(set_attr "type" "imul")
(set_attr "mode" "SI")
- (set_attr "length" "3")]) ;; mult + mflo + delay
+ (set_attr "length" "12")]) ;; mult + mflo + delay
;; Multiply-accumulate patterns
}"
[(set_attr "type" "imul,imul,multi")
(set_attr "mode" "SI")
- (set_attr "length" "1,1,2")])
+ (set_attr "length" "4,4,8")])
;; Split the above insn if we failed to get LO allocated.
(define_split
"TARGET_64BIT && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16"
"dmult\\t%1,%2"
[(set_attr "type" "imul")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn "muldi3_internal2"
[(set (match_operand:DI 0 "register_operand" "=d")
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "GENERATE_MULT3") (const_int 0))
- (const_int 1)
- (const_int 3)))]) ;; mult + mflo + delay
+ (const_int 4)
+ (const_int 12)))]) ;; mult + mflo + delay
;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
return \"multu\\t%1,%2\";
}"
[(set_attr "type" "imul")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "mulsidi3_64bit"
[(set (match_operand:DI 0 "register_operand" "=a")
return \"multu\\t%1,%2\";
}"
[(set_attr "type" "imul")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
;; _highpart patterns
(define_expand "smulsi3_highpart"
return \"multu\\t%1,%2\";
}"
[(set_attr "type" "imul")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "smuldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "=h")
"TARGET_64BIT"
"dmult\\t%1,%2"
[(set_attr "type" "imul")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn "umuldi3_highpart"
[(set (match_operand:DI 0 "register_operand" "=h")
"TARGET_64BIT"
"dmultu\\t%1,%2"
[(set_attr "type" "imul")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
;; instruction. The HI/LO registers are used as a 64 bit accumulator.
"TARGET_MAD"
"mad\\t%1,%2"
[(set_attr "type" "imul")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "*mul_acc_di"
[(set (match_operand:DI 0 "register_operand" "+x")
return \"madu\\t%1,%2\";
}"
[(set_attr "type" "imul")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "*mul_acc_64bit_di"
[(set (match_operand:DI 0 "register_operand" "+a")
return \"madu\\t%1,%2\";
}"
[(set_attr "type" "imul")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
;; Floating point multiply accumulate instructions.
"mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"madd.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT"
"madd.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"msub.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT"
"msub.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"nmadd.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT"
"nmadd.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"nmsub.d\\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT"
"nmsub.s\\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
\f
;;
;; ....................
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"div.d\\t%0,%1,%2"
[(set_attr "type" "fdiv")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn "divsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
"TARGET_HARD_FLOAT"
"div.s\\t%0,%1,%2"
[(set_attr "type" "fdiv")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
"recip.d\\t%0,%2"
[(set_attr "type" "fdiv")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
"recip.s\\t%0,%2"
[(set_attr "type" "fdiv")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
;; If optimizing, prefer the divmod functions over separate div and
;; mod functions, since this will allow using one instruction for both
"optimize"
"div\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_expand "divmoddi4"
[(set (match_operand:DI 0 "register_operand" "=d")
"TARGET_64BIT && optimize"
"ddiv\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_expand "udivmodsi4"
[(set (match_operand:SI 0 "register_operand" "=d")
"optimize"
"divu\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_expand "udivmoddi4"
[(set (match_operand:DI 0 "register_operand" "=d")
"TARGET_64BIT && optimize"
"ddivu\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
;; Division trap
return \"\";
}"
[(set_attr "type" "unknown")
- (set_attr "length" "3")])
+ (set_attr "length" "12")])
;; The mips16 bne insns is a macro which uses reg 24 as an intermediate.
return \"\";
}"
[(set_attr "type" "unknown")
- (set_attr "length" "3")])
+ (set_attr "length" "12")])
(define_expand "divsi3"
[(set (match_operand:SI 0 "register_operand" "=l")
"!optimize"
"div\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_expand "divdi3"
[(set (match_operand:DI 0 "register_operand" "=l")
"TARGET_64BIT && !optimize"
"ddiv\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_expand "modsi3"
[(set (match_operand:SI 0 "register_operand" "=h")
"!optimize"
"div\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_expand "moddi3"
[(set (match_operand:DI 0 "register_operand" "=h")
"TARGET_64BIT && !optimize"
"ddiv\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_expand "udivsi3"
[(set (match_operand:SI 0 "register_operand" "=l")
"!optimize"
"divu\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_expand "udivdi3"
[(set (match_operand:DI 0 "register_operand" "=l")
"TARGET_64BIT && !optimize"
"ddivu\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_expand "umodsi3"
[(set (match_operand:SI 0 "register_operand" "=h")
"!optimize"
"divu\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_expand "umoddi3"
[(set (match_operand:DI 0 "register_operand" "=h")
"TARGET_64BIT && !optimize"
"ddivu\\t$0,%1,%2"
[(set_attr "type" "idiv")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
\f
;;
;; ....................
"TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
"sqrt.d\\t%0,%1"
[(set_attr "type" "fsqrt")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
"TARGET_HARD_FLOAT && HAVE_SQRT_P()"
"sqrt.s\\t%0,%1"
[(set_attr "type" "fsqrt")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
"rsqrt.d\\t%0,%2"
[(set_attr "type" "fsqrt")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
"rsqrt.s\\t%0,%2"
[(set_attr "type" "fsqrt")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
\f
;;
}"
[(set_attr "type" "multi")
(set_attr "mode" "SI")
- (set_attr "length" "3")])
+ (set_attr "length" "12")])
(define_insn "absdi2"
[(set (match_operand:DI 0 "register_operand" "=d")
}"
[(set_attr "type" "multi")
(set_attr "mode" "DI")
- (set_attr "length" "3")])
+ (set_attr "length" "12")])
(define_insn "absdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"abs.d\\t%0,%1"
[(set_attr "type" "fabs")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn "abssf2"
[(set (match_operand:SF 0 "register_operand" "=f")
"TARGET_HARD_FLOAT"
"abs.s\\t%0,%1"
[(set_attr "type" "fabs")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
\f
;;
}"
[(set_attr "type" "multi")
(set_attr "mode" "SI")
- (set_attr "length" "6")])
+ (set_attr "length" "12")])
(define_insn "ffsdi2"
[(set (match_operand:DI 0 "register_operand" "=&d")
}"
[(set_attr "type" "multi")
(set_attr "mode" "DI")
- (set_attr "length" "6")])
+ (set_attr "length" "24")])
\f
;;
return \"subu\\t%0,%z2,%1\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_expand "negdi2"
[(parallel [(set (match_operand:DI 0 "register_operand" "=d")
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "4")])
+ (set_attr "length" "16")])
(define_insn "negdi2_internal_2"
[(set (match_operand:DI 0 "register_operand" "=d")
return \"dsubu\\t%0,%z2,%1\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn "negdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"neg.d\\t%0,%1"
[(set_attr "type" "fneg")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn "negsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
"TARGET_HARD_FLOAT"
"neg.s\\t%0,%1"
[(set_attr "type" "fneg")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=d")
return \"nor\\t%0,%z2,%1\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "one_cmpldi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
and\\t%0,%1,%2
andi\\t%0,%1,%x2"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
"TARGET_MIPS16"
"and\\t%0,%2"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_expand "anddi3"
[(set (match_operand:DI 0 "register_operand" "=d")
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
and\\t%0,%1,%2
andi\\t%0,%1,%x2"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_expand "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
or\\t%0,%1,%2
ori\\t%0,%1,%x2"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
"TARGET_MIPS16"
"or\\t%0,%2"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
;;; ??? There is no iordi3 pattern which accepts 'K' constants when
;;; TARGET_64BIT
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
xor\\t%0,%1,%2
xori\\t%0,%1,%x2"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,t,t")
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
- (const_int 1)
- (const_int 2))
- (const_int 1)])])
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)])])
;; ??? If delete the 32-bit long long patterns, then could merge this with
;; the following xordi3_internal pattern.
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
"xor\\t%M0,%M2\;xor\\t%L0,%L2"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,t,t")
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
- (const_int 1)
- (const_int 2))
- (const_int 1)])])
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)])])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"TARGET_64BIT && !TARGET_MIPS16"
"xori\\t%0,%1,%x2"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn "*norsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
"!TARGET_MIPS16"
"nor\\t%0,%z1,%z2"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "*nordi3"
[(set (match_operand:DI 0 "register_operand" "=d")
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"cvt.s.d\\t%0,%1"
[(set_attr "type" "fcvt")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn "truncdisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
[(set_attr "type" "darith")
(set_attr "mode" "SI")
(set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
- (const_int 2)
- (const_int 4)))])
+ (const_int 8)
+ (const_int 16)))])
(define_insn "truncdihi2"
[(set (match_operand:HI 0 "register_operand" "=d")
[(set_attr "type" "darith")
(set_attr "mode" "HI")
(set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
- (const_int 1)
- (const_int 4)))])
+ (const_int 4)
+ (const_int 16)))])
(define_insn "truncdiqi2"
[(set (match_operand:QI 0 "register_operand" "=d")
(truncate:QI (match_operand:DI 1 "se_register_operand" "d")))]
[(set_attr "type" "darith")
(set_attr "mode" "QI")
(set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
- (const_int 1)
- (const_int 4)))])
+ (const_int 4)
+ (const_int 16)))])
;; Combiner patterns to optimize shift/truncate combinations.
(define_insn ""
}"
[(set_attr "type" "darith")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
}"
[(set_attr "type" "darith")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
}"
[(set_attr "type" "darith")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
;; Combiner patterns to optimize truncate/zero_extend combinations.
"TARGET_64BIT && !TARGET_MIPS16"
"andi\\t%0,%1,0xffff"
[(set_attr "type" "darith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
"TARGET_64BIT && !TARGET_MIPS16"
"andi\\t%0,%1,0xff"
[(set_attr "type" "darith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=d")
"TARGET_64BIT && !TARGET_MIPS16"
"andi\\t%0,%1,0xff"
[(set_attr "type" "darith")
- (set_attr "mode" "HI")
- (set_attr "length" "1")])
+ (set_attr "mode" "HI")])
\f
;;
;; ....................
"* return mips_move_1word (operands, insn, TRUE);"
[(set_attr "type" "load")
(set_attr "mode" "DI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_expand "zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "")
}"
[(set_attr "type" "arith,load,load")
(set_attr "mode" "SI")
- (set_attr "length" "1,1,2")])
+ (set_attr "length" "4,4,8")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
"* return mips_move_1word (operands, insn, TRUE);"
[(set_attr "type" "load,load")
(set_attr "mode" "SI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_expand "zero_extendhidi2"
[(set (match_operand:DI 0 "register_operand" "")
}"
[(set_attr "type" "arith,load,load")
(set_attr "mode" "DI")
- (set_attr "length" "1,1,2")])
+ (set_attr "length" "4,4,8")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
"* return mips_move_1word (operands, insn, TRUE);"
[(set_attr "type" "load,load")
(set_attr "mode" "DI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_expand "zero_extendqihi2"
[(set (match_operand:HI 0 "register_operand" "")
}"
[(set_attr "type" "arith,load,load")
(set_attr "mode" "HI")
- (set_attr "length" "1,1,2")])
+ (set_attr "length" "4,4,8")])
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=d,d")
"* return mips_move_1word (operands, insn, TRUE);"
[(set_attr "type" "load,load")
(set_attr "mode" "HI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_expand "zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "")
}"
[(set_attr "type" "arith,load,load")
(set_attr "mode" "SI")
- (set_attr "length" "1,1,2")])
+ (set_attr "length" "4,4,8")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
"* return mips_move_1word (operands, insn, TRUE);"
[(set_attr "type" "load,load")
(set_attr "mode" "SI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_expand "zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "")
}"
[(set_attr "type" "arith,load,load")
(set_attr "mode" "DI")
- (set_attr "length" "1,1,2")])
+ (set_attr "length" "4,4,8")])
;; These can be created when a paradoxical subreg operand with an implicit
;; sign_extend operator is reloaded. Because of the subreg, this is really
}"
[(set_attr "type" "load,load")
(set_attr "mode" "DI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
"* return mips_move_1word (operands, insn, TRUE);"
[(set_attr "type" "load,load")
(set_attr "mode" "DI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
\f
;;
;; ....................
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,move,move,hilo,load,load")
(set_attr "mode" "DI")
- (set_attr "length" "1,1,1,1,1,2")])
+ (set_attr "length" "4,4,4,4,4,8")])
;; These patterns originally accepted general_operands, however, slightly
;; better code is generated by only accepting register_operands, and then
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "load")
(set_attr "mode" "DI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_expand "extendhisi2"
[(set (match_operand:SI 0 "register_operand" "")
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "load")
(set_attr "mode" "SI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_expand "extendqihi2"
[(set (match_operand:HI 0 "register_operand" "")
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "load")
(set_attr "mode" "SI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_expand "extendqisi2"
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "load")
(set_attr "mode" "SI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_expand "extendqidi2"
[(set (match_operand:DI 0 "register_operand" "")
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "load")
(set_attr "mode" "DI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_insn "extendsfdf2"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"cvt.d.s\\t%0,%1"
[(set_attr "type" "fcvt")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
\f
}"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "length" "11,9,10,11")])
+ (set_attr "length" "44,36,40,44")])
(define_insn "fix_truncsfsi2"
}"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "length" "11,9,10,11")])
+ (set_attr "length" "44,36,40,44")])
;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
}"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "length" "2,1,2,3")])
+ (set_attr "length" "8,4,8,12")])
;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
}"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "length" "2,1,2,3")])
+ (set_attr "length" "8,4,8,12")])
(define_insn "floatsidf2"
}"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "length" "3,4,3")])
+ (set_attr "length" "12,16,12")])
(define_insn "floatdidf2"
}"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "length" "3,4,3")])
+ (set_attr "length" "12,16,12")])
(define_insn "floatsisf2"
}"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "length" "3,4,3")])
+ (set_attr "length" "12,16,12")])
(define_insn "floatdisf2"
}"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "length" "3,4,3")])
+ (set_attr "length" "12,16,12")])
(define_expand "fixuns_truncdfsi2"
}"
[(set_attr "type" "load,load")
(set_attr "mode" "SI")
- (set_attr "length" "2,4")])
+ (set_attr "length" "8,16")])
(define_insn "movsi_usw"
[(set (match_operand:BLK 0 "memory_operand" "=R,o")
}"
[(set_attr "type" "store")
(set_attr "mode" "SI")
- (set_attr "length" "2,4")])
+ (set_attr "length" "8,16")])
;; Bit field extract patterns which use ldl/ldr.
}"
[(set_attr "type" "load,load")
(set_attr "mode" "SI")
- (set_attr "length" "2,4")])
+ (set_attr "length" "8,16")])
(define_insn "movdi_usd"
[(set (match_operand:BLK 0 "memory_operand" "=R,o")
}"
[(set_attr "type" "store")
(set_attr "mode" "SI")
- (set_attr "length" "2,4")])
+ (set_attr "length" "8,16")])
;; These two patterns support loading addresses with two instructions instead
;; of using the macro instruction la.
(high:SI (match_operand:SI 1 "immediate_operand" "")))]
"mips_split_addresses && !TARGET_MIPS16"
"lui\\t%0,%%hi(%1) # high"
- [(set_attr "type" "move")
- (set_attr "length" "1")])
+ [(set_attr "type" "move")])
(define_insn "low"
[(set (match_operand:SI 0 "register_operand" "=r")
"mips_split_addresses && !TARGET_MIPS16"
"addiu\\t%0,%1,%%lo(%2) # low"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
;; 64-bit integer moves
}"
[(set_attr "type" "store")
(set_attr "mode" "DI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
(define_insn "movdi_internal"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x,*d,*x")
"* return mips_move_2words (operands, insn); "
[(set_attr "type" "move,arith,load,load,store,store,hilo,hilo,hilo")
(set_attr "mode" "DI")
- (set_attr "length" "2,4,2,4,2,4,2,2,2")])
+ (set_attr "length" "8,16,8,16,8,16,8,8,8")])
(define_insn ""
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,To,*d")
"* return mips_move_2words (operands, insn);"
[(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
(set_attr "mode" "DI")
- (set_attr "length" "2,2,2,2,3,2,4,2,4,2")])
+ (set_attr "length" "8,8,8,8,12,8,16,8,16,8")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"* return mips_move_2words (operands, insn); "
[(set_attr "type" "move,load,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo")
(set_attr "mode" "DI")
- (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,2")])
+ (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,8")])
(define_insn ""
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d")
[(set_attr "type" "move,move,move,arith,arith,arith,load,load,store,store,hilo")
(set_attr "mode" "DI")
(set_attr_alternative "length"
- [(const_int 1)
- (const_int 1)
- (const_int 1)
+ [(const_int 4)
+ (const_int 4)
+ (const_int 4)
(if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 1)
- (const_int 2))
+ (const_int 4)
+ (const_int 8))
(if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 2)
- (const_int 3))
+ (const_int 8)
+ (const_int 12))
(if_then_else (match_operand:VOID 1 "m16_usym5_4" "")
- (const_int 1)
- (const_int 2))
- (const_int 1)
- (const_int 2)
- (const_int 1)
- (const_int 2)
- (const_int 1)])])
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)
+ (const_int 8)
+ (const_int 4)
+ (const_int 8)
+ (const_int 4)])])
;; On the mips16, we can split ld $r,N($r) into an add and a load,
;; when the original load is a 4 byte instruction but the add and the
}"
[(set_attr "type" "store")
(set_attr "mode" "SI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "4,8")])
;; The difference between these two is whether or not ints are allowed
;; in FP registers (off by default, use -mdebugh to enable).
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo")
(set_attr "mode" "SI")
- (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,2,1,2,1,1,1,1")])
+ (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,8,4,8,4,4,4,4")])
(define_insn "movsi_internal2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d")
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo")
(set_attr "mode" "SI")
- (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,1,1")])
+ (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,4,4")])
;; This is the mips16 movsi instruction. We accept a small integer as
;; the source if the destination is a GP memory reference. This is
[(set_attr "type" "move,move,move,load,arith,arith,arith,load,load,store,store,hilo,hilo")
(set_attr "mode" "SI")
(set_attr_alternative "length"
- [(const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 2)
+ [(const_int 4)
+ (const_int 4)
+ (const_int 4)
+ (const_int 8)
(if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 1)
- (const_int 2))
+ (const_int 4)
+ (const_int 8))
(if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 2)
- (const_int 3))
+ (const_int 8)
+ (const_int 12))
(if_then_else (match_operand:VOID 1 "m16_usym8_4" "")
- (const_int 1)
- (const_int 2))
- (const_int 1)
- (const_int 2)
- (const_int 1)
- (const_int 2)
- (const_int 1)
- (const_int 1)])])
+ (const_int 4)
+ (const_int 8))
+ (const_int 4)
+ (const_int 8)
+ (const_int 4)
+ (const_int 8)
+ (const_int 4)
+ (const_int 4)])])
;; On the mips16, we can split lw $r,N($r) into an add and a load,
;; when the original load is a 4 byte instruction but the add and the
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
(set_attr "mode" "SI")
- (set_attr "length" "2,1,1,2,1,2,1,1,1,1,2,1,2")])
+ (set_attr "length" "8,4,4,8,4,8,4,4,4,4,8,4,8")])
;; Reload condition code registers. These need scratch registers.
"mips_isa >= 4 && TARGET_HARD_FLOAT"
"lwxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT"
"lwxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
"mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn ""
[(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
"mips_isa >= 4 && TARGET_HARD_FLOAT"
"swxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn ""
[(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
"mips_isa >= 4 && TARGET_HARD_FLOAT"
"swxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
- (set_attr "mode" "SF")
- (set_attr "length" "1")])
+ (set_attr "mode" "SF")])
(define_insn ""
[(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
"mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
(define_insn ""
[(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
"mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
- (set_attr "mode" "DF")
- (set_attr "length" "1")])
+ (set_attr "mode" "DF")])
;; 16-bit Integer moves
"* return mips_move_1word (operands, insn, TRUE);"
[(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
(set_attr "mode" "HI")
- (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
+ (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
(define_insn "movhi_internal2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
"* return mips_move_1word (operands, insn, TRUE);"
[(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
(set_attr "mode" "HI")
- (set_attr "length" "1,1,1,2,1,2,1,1,1,1")])
+ (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
(define_insn ""
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
[(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
(set_attr "mode" "HI")
(set_attr_alternative "length"
- [(const_int 1)
- (const_int 1)
- (const_int 1)
+ [(const_int 4)
+ (const_int 4)
+ (const_int 4)
(if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 1)
- (const_int 2))
+ (const_int 4)
+ (const_int 8))
(if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 2)
- (const_int 3))
- (const_int 1)
- (const_int 2)
- (const_int 1)
- (const_int 2)
- (const_int 1)])])
+ (const_int 8)
+ (const_int 12))
+ (const_int 4)
+ (const_int 8)
+ (const_int 4)
+ (const_int 8)
+ (const_int 4)])])
;; On the mips16, we can split lh $r,N($r) into an add and a load,
"* return mips_move_1word (operands, insn, TRUE);"
[(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
(set_attr "mode" "QI")
- (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
+ (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
(define_insn "movqi_internal2"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
"* return mips_move_1word (operands, insn, TRUE);"
[(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
(set_attr "mode" "QI")
- (set_attr "length" "1,1,1,2,1,2,1,1,1,1")])
+ (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
(define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
[(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
(set_attr "mode" "QI")
(set_attr_alternative "length"
- [(const_int 1)
- (const_int 1)
- (const_int 1)
+ [(const_int 4)
+ (const_int 4)
+ (const_int 4)
(if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
- (const_int 1)
- (const_int 2))
+ (const_int 4)
+ (const_int 8))
(if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
- (const_int 2)
- (const_int 3))
- (const_int 1)
- (const_int 2)
- (const_int 1)
- (const_int 2)
- (const_int 1)])])
+ (const_int 8)
+ (const_int 12))
+ (const_int 4)
+ (const_int 8)
+ (const_int 4)
+ (const_int 8)
+ (const_int 4)])])
;; On the mips16, we can split lb $r,N($r) into an add and a load,
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
(set_attr "mode" "SF")
- (set_attr "length" "1,1,1,2,1,2,1,1,1,1,2,1,2")])
+ (set_attr "length" "4,4,4,8,4,8,4,4,4,4,8,4,8")])
(define_insn "movsf_internal2"
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,load,load,store,store")
(set_attr "mode" "SF")
- (set_attr "length" "1,1,2,1,2")])
+ (set_attr "length" "4,4,8,4,8")])
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,d,R,m")
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,move,move,load,load,store,store")
(set_attr "mode" "SF")
- (set_attr "length" "1,1,1,1,2,1,2")])
+ (set_attr "length" "4,4,4,4,8,4,8")])
;; 64-bit floating point moves
"* return mips_move_2words (operands, insn); "
[(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
(set_attr "mode" "DF")
- (set_attr "length" "1,2,4,2,4,4,2,2,2,2,4,2,4")])
+ (set_attr "length" "4,8,16,8,16,16,8,8,8,8,16,8,16")])
(define_insn "movdf_internal1a"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,To,To,f,*d,*d,*d,*To,*R")
"* return mips_move_2words (operands, insn); "
[(set_attr "type" "move,load,store,store,store,store,load,load,load,load,store,store")
(set_attr "mode" "DF")
- (set_attr "length" "1,2,1,1,2,2,2,2,2,1,2,1")])
+ (set_attr "length" "4,8,4,4,8,8,8,8,8,4,8,4")])
(define_insn "movdf_internal2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,To")
"* return mips_move_2words (operands, insn); "
[(set_attr "type" "move,load,load,store,store")
(set_attr "mode" "DF")
- (set_attr "length" "2,2,4,2,4")])
+ (set_attr "length" "8,8,16,8,16")])
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,d,R,To")
"* return mips_move_2words (operands, insn);"
[(set_attr "type" "move,move,move,load,load,store,store")
(set_attr "mode" "DF")
- (set_attr "length" "2,2,2,2,4,2,4")])
+ (set_attr "length" "8,8,8,8,16,8,16")])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
"%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,%1%]"
[(set_attr "type" "move")
(set_attr "mode" "DI")
- (set_attr "length" "3")])
+ (set_attr "length" "12")])
\f
;; Block moves, see mips.c for more details.
;; Argument 0 is the destination
"* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
[(set_attr "type" "store")
(set_attr "mode" "none")
- (set_attr "length" "20")])
+ (set_attr "length" "80")])
;; We need mips16 versions, because an offset from the stack pointer
;; is not offsettable, since the stack pointer can only handle 4 and 8
"* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
[(set_attr "type" "multi")
(set_attr "mode" "none")
- (set_attr "length" "20")])
+ (set_attr "length" "80")])
(define_insn ""
[(set (match_operand:BLK 0 "memory_operand" "=d") ;; destination
"* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
[(set_attr "type" "multi")
(set_attr "mode" "none")
- (set_attr "length" "20")])
+ (set_attr "length" "80")])
(define_insn ""
[(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
"* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
[(set_attr "type" "multi")
(set_attr "mode" "none")
- (set_attr "length" "20")])
+ (set_attr "length" "80")])
;; Split a block move into 2 parts, the first part is everything
;; except for the last move, and the second part is just the last
"* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
[(set_attr "type" "store")
(set_attr "mode" "none")
- (set_attr "length" "20")])
+ (set_attr "length" "80")])
(define_insn ""
[(set (match_operand:BLK 0 "memory_operand" "=d") ;; destination
"* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
[(set_attr "type" "multi")
(set_attr "mode" "none")
- (set_attr "length" "20")])
+ (set_attr "length" "80")])
(define_insn "movstrsi_internal3"
[(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
""
"* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
[(set_attr "type" "store")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_insn ""
[(set (match_operand:BLK 0 "memory_operand" "=d") ;; destination
"TARGET_MIPS16"
"* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
[(set_attr "type" "store")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
\f
;;
return \"sll\\t%0,%1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "ashlsi3_internal2"
[(set (match_operand:SI 0 "register_operand" "=d,d")
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 1)
- (const_int 2))])])
+ (const_int 4)
+ (const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
}"
[(set_attr "type" "darith")
(set_attr "mode" "SI")
- (set_attr "length" "12")])
+ (set_attr "length" "48")])
(define_insn "ashldi3_internal2"
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "4")])
+ (set_attr "length" "16")])
(define_split
return \"dsll\\t%0,%1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 1)
- (const_int 2))])])
+ (const_int 4)
+ (const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
return \"sra\\t%0,%1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "ashrsi3_internal2"
[(set (match_operand:SI 0 "register_operand" "=d,d")
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 1)
- (const_int 2))])])
+ (const_int 4)
+ (const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "12")])
+ (set_attr "length" "48")])
(define_insn "ashrdi3_internal2"
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "4")])
+ (set_attr "length" "16")])
(define_split
return \"dsra\\t%0,%1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 1)
- (const_int 2))])])
+ (const_int 4)
+ (const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
return \"srl\\t%0,%1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "lshrsi3_internal2"
[(set (match_operand:SI 0 "register_operand" "=d,d")
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 1)
- (const_int 2))])])
+ (const_int 4)
+ (const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 2)
- (const_int 3))
+ (const_int 8)
+ (const_int 12))
(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 3)
- (const_int 4))])])
+ (const_int 12)
+ (const_int 16))])])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "12")])
+ (set_attr "length" "48")])
(define_insn "lshrdi3_internal2"
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
- (set_attr "length" "4")])
+ (set_attr "length" "16")])
(define_split
return \"dsrl\\t%0,%1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
- (const_int 1)
- (const_int 2))])])
+ (const_int 4)
+ (const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
;;
;; ....................
-(define_insn "branch_fp_ne"
+;; Conditional branches on floating-point equality tests.
+
+(define_insn "branch_fp"
[(set (pc)
- (if_then_else (ne:CC (match_operand:CC 0 "register_operand" "z")
- (const_int 0))
- (match_operand 1 "pc_or_label_operand" "")
- (match_operand 2 "pc_or_label_operand" "")))]
+ (if_then_else
+ (match_operator:CC 0 "cmp_op"
+ [(match_operand:CC 2 "register_operand" "z")
+ (const_int 0)])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
"TARGET_HARD_FLOAT"
"*
{
- mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
- return (operands[1] != pc_rtx) ? \"%*bc1t%?\\t%Z0%1\" : \"%*bc1f%?\\t%Z0%2\";
+ return mips_output_conditional_branch (insn,
+ operands,
+ /*two_operands_p=*/0,
+ /*float_p=*/1,
+ /*inverted_p=*/0,
+ get_attr_length (insn));
}"
[(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
-(define_insn "branch_fp_eq"
+(define_insn "branch_fp_inverted"
[(set (pc)
- (if_then_else (eq:CC (match_operand:CC 0 "register_operand" "z")
- (const_int 0))
- (match_operand 1 "pc_or_label_operand" "")
- (match_operand 2 "pc_or_label_operand" "")))]
+ (if_then_else
+ (match_operator:CC 0 "cmp_op"
+ [(match_operand:CC 2 "register_operand" "z")
+ (const_int 0)])
+ (pc)
+ (label_ref (match_operand 1 "" ""))))]
"TARGET_HARD_FLOAT"
"*
{
- mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
- return (operands[1] != pc_rtx) ? \"%*bc1f%?\\t%Z0%1\" : \"%*bc1t%?\\t%Z0%2\";
+ return mips_output_conditional_branch (insn,
+ operands,
+ /*two_operands_p=*/0,
+ /*float_p=*/1,
+ /*inverted_p=*/1,
+ get_attr_length (insn));
}"
[(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
+
+;; Conditional branches on comparisons with zero.
(define_insn "branch_zero"
[(set (pc)
- (if_then_else (match_operator:SI 0 "cmp_op"
- [(match_operand:SI 1 "register_operand" "d")
- (const_int 0)])
- (match_operand 2 "pc_or_label_operand" "")
- (match_operand 3 "pc_or_label_operand" "")))]
+ (if_then_else
+ (match_operator:SI 0 "cmp_op"
+ [(match_operand:SI 2 "register_operand" "d")
+ (const_int 0)])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
"!TARGET_MIPS16"
"*
{
- mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
- if (operands[2] != pc_rtx)
- { /* normal jump */
- switch (GET_CODE (operands[0]))
- {
- case EQ: return \"%*beq%?\\t%z1,%.,%2\";
- case NE: return \"%*bne%?\\t%z1,%.,%2\";
- case GTU: return \"%*bne%?\\t%z1,%.,%2\";
- case LEU: return \"%*beq%?\\t%z1,%.,%2\";
- case GEU: return \"%*j\\t%2\";
- case LTU: return \"%*bne%?\\t%.,%.,%2\";
- default:
- break;
- }
+ return mips_output_conditional_branch (insn,
+ operands,
+ /*two_operands_p=*/0,
+ /*float_p=*/0,
+ /*inverted_p=*/0,
+ get_attr_length (insn));
+}"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
- return \"%*b%C0z%?\\t%z1,%2\";
- }
- else
- { /* inverted jump */
- switch (GET_CODE (operands[0]))
- {
- case EQ: return \"%*bne%?\\t%z1,%.,%3\";
- case NE: return \"%*beq%?\\t%z1,%.,%3\";
- case GTU: return \"%*beq%?\\t%z1,%.,%3\";
- case LEU: return \"%*bne%?\\t%z1,%.,%3\";
- case GEU: return \"%*beq%?\\t%.,%.,%3\";
- case LTU: return \"%*j\\t%3\";
- default:
- break;
- }
+(define_insn "branch_zero_inverted"
+ [(set (pc)
+ (if_then_else
+ (match_operator:SI 0 "cmp_op"
+ [(match_operand:SI 2 "register_operand" "d")
+ (const_int 0)])
+ (pc)
+ (label_ref (match_operand 1 "" ""))))]
+ "!TARGET_MIPS16"
+ "*
+{
+ return mips_output_conditional_branch (insn,
+ operands,
+ /*two_operands_p=*/0,
+ /*float_p=*/0,
+ /*inverted_p=*/1,
+ get_attr_length (insn));
+}"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
- return \"%*b%N0z%?\\t%z1,%3\";
- }
+(define_insn "branch_zero_di"
+ [(set (pc)
+ (if_then_else
+ (match_operator:DI 0 "cmp_op"
+ [(match_operand:DI 2 "se_register_operand" "d")
+ (const_int 0)])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ "!TARGET_MIPS16"
+ "*
+{
+ return mips_output_conditional_branch (insn,
+ operands,
+ /*two_operands_p=*/0,
+ /*float_p=*/0,
+ /*inverted_p=*/0,
+ get_attr_length (insn));
}"
[(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
+
+(define_insn "branch_zero_di_inverted"
+ [(set (pc)
+ (if_then_else
+ (match_operator:DI 0 "cmp_op"
+ [(match_operand:DI 2 "se_register_operand" "d")
+ (const_int 0)])
+ (pc)
+ (label_ref (match_operand 1 "" ""))))]
+ "!TARGET_MIPS16"
+ "*
+{
+ return mips_output_conditional_branch (insn,
+ operands,
+ /*two_operands_p=*/0,
+ /*float_p=*/0,
+ /*inverted_p=*/1,
+ get_attr_length (insn));
+}"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
+;; Conditional branch on equality comparision.
+
+(define_insn "branch_equality"
+ [(set (pc)
+ (if_then_else
+ (match_operator:SI 0 "equality_op"
+ [(match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ "!TARGET_MIPS16"
+ "*
+{
+ return mips_output_conditional_branch (insn,
+ operands,
+ /*two_operands_p=*/1,
+ /*float_p=*/0,
+ /*inverted_p=*/0,
+ get_attr_length (insn));
+}"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
+(define_insn "branch_equality_di"
+ [(set (pc)
+ (if_then_else
+ (match_operator:DI 0 "equality_op"
+ [(match_operand:DI 2 "se_register_operand" "d")
+ (match_operand:DI 3 "se_register_operand" "d")])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ "!TARGET_MIPS16"
+ "*
+{
+ return mips_output_conditional_branch (insn,
+ operands,
+ /*two_operands_p=*/1,
+ /*float_p=*/0,
+ /*inverted_p=*/0,
+ get_attr_length (insn));
+}"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
+(define_insn "branch_equality_inverted"
+ [(set (pc)
+ (if_then_else
+ (match_operator:SI 0 "equality_op"
+ [(match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")])
+ (pc)
+ (label_ref (match_operand 1 "" ""))))]
+ "!TARGET_MIPS16"
+ "*
+{
+ return mips_output_conditional_branch (insn,
+ operands,
+ /*two_operands_p=*/1,
+ /*float_p=*/0,
+ /*inverted_p=*/1,
+ get_attr_length (insn));
+}"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
+(define_insn "branch_equality_di_inverted"
+ [(set (pc)
+ (if_then_else
+ (match_operator:DI 0 "equality_op"
+ [(match_operand:DI 2 "se_register_operand" "d")
+ (match_operand:DI 3 "se_register_operand" "d")])
+ (pc)
+ (label_ref (match_operand 1 "" ""))))]
+ "!TARGET_MIPS16"
+ "*
+{
+ return mips_output_conditional_branch (insn,
+ operands,
+ /*two_operands_p=*/1,
+ /*float_p=*/0,
+ /*inverted_p=*/1,
+ get_attr_length (insn));
+}"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+;; MIPS16 branches
(define_insn ""
[(set (pc)
}"
[(set_attr "type" "branch")
(set_attr "mode" "none")
- (set_attr "length" "2")])
-
-(define_insn "branch_zero_di"
- [(set (pc)
- (if_then_else (match_operator:DI 0 "cmp_op"
- [(match_operand:DI 1 "se_register_operand" "d")
- (const_int 0)])
- (match_operand 2 "pc_or_label_operand" "")
- (match_operand 3 "pc_or_label_operand" "")))]
- "!TARGET_MIPS16"
- "*
-{
- mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
- if (operands[2] != pc_rtx)
- { /* normal jump */
- switch (GET_CODE (operands[0]))
- {
- case EQ: return \"%*beq%?\\t%z1,%.,%2\";
- case NE: return \"%*bne%?\\t%z1,%.,%2\";
- case GTU: return \"%*bne%?\\t%z1,%.,%2\";
- case LEU: return \"%*beq%?\\t%z1,%.,%2\";
- case GEU: return \"%*j\\t%2\";
- case LTU: return \"%*bne%?\\t%.,%.,%2\";
- default:
- break;
- }
-
- return \"%*b%C0z%?\\t%z1,%2\";
- }
- else
- { /* inverted jump */
- switch (GET_CODE (operands[0]))
- {
- case EQ: return \"%*bne%?\\t%z1,%.,%3\";
- case NE: return \"%*beq%?\\t%z1,%.,%3\";
- case GTU: return \"%*beq%?\\t%z1,%.,%3\";
- case LEU: return \"%*bne%?\\t%z1,%.,%3\";
- case GEU: return \"%*beq%?\\t%.,%.,%3\";
- case LTU: return \"%*j\\t%3\";
- default:
- break;
- }
-
- return \"%*b%N0z%?\\t%z1,%3\";
- }
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "length" "8")])
(define_insn ""
[(set (pc)
}"
[(set_attr "type" "branch")
(set_attr "mode" "none")
- (set_attr "length" "2")])
-
-
-(define_insn "branch_equality"
- [(set (pc)
- (if_then_else (match_operator:SI 0 "equality_op"
- [(match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")])
- (match_operand 3 "pc_or_label_operand" "")
- (match_operand 4 "pc_or_label_operand" "")))]
- "!TARGET_MIPS16"
- "*
-{
- mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
- return (operands[3] != pc_rtx)
- ? \"%*b%C0%?\\t%z1,%z2,%3\"
- : \"%*b%N0%?\\t%z1,%z2,%4\";
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
-
-
-(define_insn "branch_equality_di"
- [(set (pc)
- (if_then_else (match_operator:DI 0 "equality_op"
- [(match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")])
- (match_operand 3 "pc_or_label_operand" "")
- (match_operand 4 "pc_or_label_operand" "")))]
- "!TARGET_MIPS16"
- "*
-{
- mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
- return (operands[3] != pc_rtx)
- ? \"%*b%C0%?\\t%z1,%z2,%3\"
- : \"%*b%N0%?\\t%z1,%z2,%4\";
-}"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
-
+ (set_attr "length" "8")])
(define_expand "beq"
[(set (pc)
"!TARGET_MIPS16"
"sltu\\t%0,%1,1"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=t")
"TARGET_MIPS16"
"sltu\\t%1,1"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "seq_di_zero"
[(set (match_operand:DI 0 "register_operand" "=d")
"TARGET_64BIT && !TARGET_MIPS16"
"sltu\\t%0,%1,1"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=t")
"TARGET_64BIT && TARGET_MIPS16"
"sltu\\t%1,1"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn "seq_si"
[(set (match_operand:SI 0 "register_operand" "=d,d")
xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"!TARGET_MIPS16"
"sltu\\t%0,%.,%1"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "sne_di_zero"
[(set (match_operand:DI 0 "register_operand" "=d")
"TARGET_64BIT && !TARGET_MIPS16"
"sltu\\t%0,%.,%1"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn "sne_si"
[(set (match_operand:SI 0 "register_operand" "=d,d")
xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
[(set_attr "type" "arith")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"!TARGET_MIPS16"
"slt\\t%0,%z2,%1"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=t")
"TARGET_MIPS16"
"slt\\t%2,%1"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "sgt_di"
[(set (match_operand:DI 0 "register_operand" "=d")
"TARGET_64BIT && !TARGET_MIPS16"
"slt\\t%0,%z2,%1"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
"TARGET_64BIT && TARGET_MIPS16"
"slt\\t%2,%1"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_expand "sge"
[(set (match_operand:SI 0 "register_operand" "=d")
"slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
[(set_attr "type" "arith")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
"slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"!TARGET_MIPS16"
"slt\\t%0,%1,%2"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=t,t")
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
- (const_int 1)
- (const_int 2))])])
+ (const_int 4)
+ (const_int 8))])])
(define_insn "slt_di"
[(set (match_operand:DI 0 "register_operand" "=d")
"TARGET_64BIT && !TARGET_MIPS16"
"slt\\t%0,%1,%2"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=t,t")
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
- (const_int 1)
- (const_int 2))])])
+ (const_int 4)
+ (const_int 8))])])
(define_expand "sle"
[(set (match_operand:SI 0 "register_operand" "=d")
return \"slt\\t%0,%1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=t")
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn "sle_di_const"
[(set (match_operand:DI 0 "register_operand" "=d")
return \"slt\\t%0,%1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=t")
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn "sle_si_reg"
[(set (match_operand:SI 0 "register_operand" "=d")
"slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
[(set_attr "type" "arith")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
"slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
""
"sltu\\t%0,%z2,%1"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=t")
""
"sltu\\t%2,%1"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn "sgtu_di"
[(set (match_operand:DI 0 "register_operand" "=d")
"TARGET_64BIT"
"sltu\\t%0,%z2,%1"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=t")
"TARGET_64BIT"
"sltu\\t%2,%1"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_expand "sgeu"
[(set (match_operand:SI 0 "register_operand" "=d")
"sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
[(set_attr "type" "arith")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
"sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"!TARGET_MIPS16"
"sltu\\t%0,%1,%2"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=t,t")
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
- (const_int 1)
- (const_int 2))])])
+ (const_int 4)
+ (const_int 8))])])
(define_insn "sltu_di"
[(set (match_operand:DI 0 "register_operand" "=d")
"TARGET_64BIT && !TARGET_MIPS16"
"sltu\\t%0,%1,%2"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=t,t")
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set_attr_alternative "length"
- [(const_int 1)
+ [(const_int 4)
(if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
- (const_int 1)
- (const_int 2))])])
+ (const_int 4)
+ (const_int 8))])])
(define_expand "sleu"
[(set (match_operand:SI 0 "register_operand" "=d")
return \"sltu\\t%0,%1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "SI")
- (set_attr "length" "1")])
+ (set_attr "mode" "SI")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=t")
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn "sleu_di_const"
[(set (match_operand:DI 0 "register_operand" "=d")
return \"sltu\\t%0,%1,%2\";
}"
[(set_attr "type" "arith")
- (set_attr "mode" "DI")
- (set_attr "length" "1")])
+ (set_attr "mode" "DI")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=t")
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
- (const_int 1)
- (const_int 2)))])
+ (const_int 4)
+ (const_int 8)))])
(define_insn "sleu_si_reg"
[(set (match_operand:SI 0 "register_operand" "=d")
"sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
[(set_attr "type" "arith")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
"sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")
- (set_attr "length" "1")])
+ (set_attr "mode" "FPSW")])
(define_insn "slt_df"
[(set (match_operand:CC 0 "register_operand" "=z")
return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")
- (set_attr "length" "1")])
+ (set_attr "mode" "FPSW")])
(define_insn "sle_df"
[(set (match_operand:CC 0 "register_operand" "=z")
return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")
- (set_attr "length" "1")])
+ (set_attr "mode" "FPSW")])
(define_insn "sgt_df"
[(set (match_operand:CC 0 "register_operand" "=z")
return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")
- (set_attr "length" "1")])
+ (set_attr "mode" "FPSW")])
(define_insn "sge_df"
[(set (match_operand:CC 0 "register_operand" "=z")
return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")
- (set_attr "length" "1")])
+ (set_attr "mode" "FPSW")])
(define_insn "seq_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")
- (set_attr "length" "1")])
+ (set_attr "mode" "FPSW")])
(define_insn "slt_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")
- (set_attr "length" "1")])
+ (set_attr "mode" "FPSW")])
(define_insn "sle_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")
- (set_attr "length" "1")])
+ (set_attr "mode" "FPSW")])
(define_insn "sgt_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")
- (set_attr "length" "1")])
+ (set_attr "mode" "FPSW")])
(define_insn "sge_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
- (set_attr "mode" "FPSW")
- (set_attr "length" "1")])
+ (set_attr "mode" "FPSW")])
\f
;;
return \"%*j\\t%l0\";
}"
[(set_attr "type" "jump")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
;; We need a different insn for the mips16, because a mips16 branch
;; does not have a delay slot.
"b\\t%l0"
[(set_attr "type" "branch")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_expand "indirect_jump"
[(set (pc) (match_operand 0 "register_operand" "d"))]
"!(Pmode == DImode)"
"%*j\\t%0"
[(set_attr "type" "jump")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_insn "indirect_jump_internal2"
[(set (pc) (match_operand:DI 0 "se_register_operand" "d"))]
"Pmode == DImode"
"%*j\\t%0"
[(set_attr "type" "jump")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_expand "tablejump"
[(set (pc)
"!(Pmode == DImode)"
"%*j\\t%0"
[(set_attr "type" "jump")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_insn "tablejump_internal2"
[(set (pc)
"Pmode == DImode"
"%*j\\t%0"
[(set_attr "type" "jump")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_expand "tablejump_internal3"
[(parallel [(set (pc)
}"
[(set_attr "type" "jump")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_expand "tablejump_internal4"
[(parallel [(set (pc)
&& PREV_INSN (next_active_insn (insn)) == operands[1]"
"%*j\\t%0"
[(set_attr "type" "jump")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
;; Implement a switch statement when generating embedded PIC code.
;; Switches are implemented by `tablejump' when not using -membedded-pic.
}"
[(set_attr "type" "jump")
(set_attr "mode" "none")
- (set_attr "length" "6")])
+ (set_attr "length" "24")])
;; For o32/n32/n64, we save the gp in the jmp_buf as well. While it is
;; possible to either pull it off the stack (in the o32 case) or recalculate
"mips_can_use_return_insn ()"
"%*j\\t$31"
[(set_attr "type" "jump")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
;; Normal return.
;; We match any mode for the return address, so that this will work with
return \"%*j\\t%0\";
}"
[(set_attr "type" "jump")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
;; When generating embedded PIC code we need to get the address of the
;; current function. This specialized instruction does just that.
"%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31"
[(set_attr "type" "call")
(set_attr "mode" "none")
- (set_attr "length" "4")])
+ (set_attr "length" "16")])
\f
;;
"%*jal\\t%0"
[(set_attr "type" "call")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "call_internal1"
[(call (mem (match_operand 0 "call_insn_operand" "ri"))
return \"%*jal\\t%2,%0\";
}"
[(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_insn "call_internal2"
[(call (mem (match_operand 0 "call_insn_operand" "ri"))
}"
[(set_attr "type" "call")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "call_internal3a"
[(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
"!(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
"%*jal\\t%2,%0"
[(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_insn "call_internal3b"
[(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
"Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
"%*jal\\t%2,%0"
[(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_insn "call_internal4a"
[(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
}"
[(set_attr "type" "call")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "call_internal4b"
[(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
}"
[(set_attr "type" "call")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
;; calls.c now passes a fourth argument, make saber happy
"%*jal\\t%1"
[(set_attr "type" "call")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "call_value_internal1"
[(set (match_operand 0 "register_operand" "=df")
return \"%*jal\\t%3,%1\";
}"
[(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_insn "call_value_internal2"
[(set (match_operand 0 "register_operand" "=df")
}"
[(set_attr "type" "call")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "call_value_internal3a"
[(set (match_operand 0 "register_operand" "=df")
&& !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
"%*jal\\t%3,%1"
[(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_insn "call_value_internal3b"
[(set (match_operand 0 "register_operand" "=df")
&& Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
"%*jal\\t%3,%1"
[(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_insn "call_value_internal3c"
[(set (match_operand 0 "register_operand" "=df")
&& GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
"%*jal\\t%3,%1"
[(set_attr "type" "call")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
(define_insn "call_value_internal4a"
[(set (match_operand 0 "register_operand" "=df")
}"
[(set_attr "type" "call")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "call_value_internal4b"
[(set (match_operand 0 "register_operand" "=df")
}"
[(set_attr "type" "call")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_expand "call_value_multiple_internal0"
[(parallel [(set (match_operand 0 "" "")
}"
[(set_attr "type" "call")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
;; Call subroutine returning any type.
""
"%(nop%)"
[(set_attr "type" "nop")
- (set_attr "mode" "none")
- (set_attr "length" "1")])
+ (set_attr "mode" "none")])
;; The MIPS chip does not seem to require stack probes.
;;
}"
[(set_attr "type" "unknown")
(set_attr "mode" "QI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "consttable_hi"
[(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")] 11)]
}"
[(set_attr "type" "unknown")
(set_attr "mode" "HI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "consttable_si"
[(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")] 12)]
}"
[(set_attr "type" "unknown")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "consttable_di"
[(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")] 13)]
}"
[(set_attr "type" "unknown")
(set_attr "mode" "DI")
- (set_attr "length" "4")])
+ (set_attr "length" "16")])
(define_insn "consttable_sf"
[(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")] 14)]
}"
[(set_attr "type" "unknown")
(set_attr "mode" "SF")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "consttable_df"
[(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")] 15)]
}"
[(set_attr "type" "unknown")
(set_attr "mode" "DF")
- (set_attr "length" "4")])
+ (set_attr "length" "16")])
(define_insn "align_2"
[(unspec_volatile [(const_int 0)] 16)]
".align 1"
[(set_attr "type" "unknown")
(set_attr "mode" "HI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "align_4"
[(unspec_volatile [(const_int 0)] 17)]
".align 2"
[(set_attr "type" "unknown")
(set_attr "mode" "SI")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_insn "align_8"
[(unspec_volatile [(const_int 0)] 18)]
".align 3"
[(set_attr "type" "unknown")
(set_attr "mode" "DI")
- (set_attr "length" "3")])
+ (set_attr "length" "12")])
\f
;;
;; ....................
}"
[(set_attr "type" "branch")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_peephole
[(set (match_operand:DI 0 "register_operand" "=t")
}"
[(set_attr "type" "branch")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
;; We can also have the reverse reload: reload will spill $24 into
;; another register, and then do a branch on that register when it
}"
[(set_attr "type" "branch")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])
(define_peephole
[(set (match_operand:DI 0 "register_operand" "=d")
}"
[(set_attr "type" "branch")
(set_attr "mode" "none")
- (set_attr "length" "2")])
+ (set_attr "length" "8")])