2008-10-13 Andrew Pinski <andrew_pinski@playstation.sony.com>

            Kaushal Kantawala <Kaushal_Kantawala@playstation.sony.com>
            Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
            Grace Cao  <grace_cao@playstation.sony.com>

        * doc/invoke.texi (-mgen-cell-microcode): Document.
        (-mwarn-cell-microcode): Document.
        * cfglayout.c (locator_location): Export.
        * rtl.h (locator_location): Define prototype.
        * config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): New predicate.
        * rs6000/rs6000-protos.h (rs6000_final_prescan_insn): Define prototype.
        * config/rs6000/rs6000.opt (mgen-cell-microcode): New option.
        (mwarn-cell-microcode): New option.
        * rs6000/rs6000.c (rs6000_cell_dont_microcode): Delete unused variable.
        (rs6000_override_options): Set rs6000_gen_cell_microcode if tuning for
        cell and not already set.
        Turn off string instructions if not generating cell microcode.
        (rs6000_final_prescan_insn): New function that warns about microcoded
        instructions.
        * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Define.
        * config/rs6000/rs6000.md
        Replace cc_reg_not_cr0_operand with cc_reg_not_micro_cr0_operand if
        the instruction would have been microcoded on the Cell.
        Set cell_micro to always on unnamed patterns for the string instructions.
        (cell_micro): Update definition, remove load/store conditional microcoded.
        (sign_extend:DI): Define new pattern for non microcoded version.
        (sign_extend:SI): Likewise.
        (compare (div:P)): Set cell_micro to not.
        (andsi3): Define as an expand.
        (andsi3_mc): New pattern.
        (andsi3_nomc): New pattern.
        (andsi3_internal0_nomc): New pattern.
        (andsi3_internal2): Rename to ...
        (andsi3_internal2_mc): this and enable iff generating microcode.
        (andsi3_internal3): Rename to ...
        (andsi3_internal3_mc): this and enable iff generating microcode.
        (andsi3_internal4): Enable iif generating microcode.
        (andsi3_internal5): Rename to ..
        (andsi3_internal5_mc): this and enable iff generating microcode.
        (andsi3_internal5_nomc): New pattern.
        (extzvdi_internal1): Enable iff generating microcode.
        (extzvdi_internal2): Likewise.
        (rotlsi3_internal7): Set cell_micro to always if non immediate form.
        (anddi3): Change to expand.
        (anddi3_mc): Rename from anddi3.
        (anddi3_no_mc): New pattern.
        (anddi3_internal2): Rename to ..
        (anddi3_internal2_mc): this and enable iff generating microcode.
        (anddi3_internal2_nomc): New pattern.
        (anddi3_internal3): Rename to ..
        (anddi3_internal3_mc): this and enable iff generating microcode.
        (anddi3_internal3_nomc): New pattern.
        (movti_string): Set cell_micro to always if TARGET_STRING.
        (stmsi8): Set cell_micro to always.
        (stmsi7): Likewise.
        (stmsi6): Likewise.
        (stmsi5): Likewise.
        (stmsi4): Likewise.
        (stmsi3): Likewise.
        (stmsi8_power): Likewise.
        (stmsi7_power): Likewise.
        (stmsi6_power): Likewise.
        (stmsi5_power): Likewise.
        (stmsi4_power): Likewise.
        (stmsi3_power): Likewise.
        (movsi_update2): Enable iff generating microcode.
        (movhi_update3): Likewise.
        (lmw): Set cell_micro to always.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@141094 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 25a8c88..bbf7cd5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,72 @@
+2008-10-13  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+            Kaushal Kantawala <Kaushal_Kantawala@playstation.sony.com>
+            Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+            Grace Cao  <grace_cao@playstation.sony.com>
+
+       * doc/invoke.texi (-mgen-cell-microcode): Document.
+       (-mwarn-cell-microcode): Document.
+       * cfglayout.c (locator_location): Export.
+       * rtl.h (locator_location): Define prototype.
+       * config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): New predicate.
+       * rs6000/rs6000-protos.h (rs6000_final_prescan_insn): Define prototype.
+       * config/rs6000/rs6000.opt (mgen-cell-microcode): New option.
+       (mwarn-cell-microcode): New option.
+       * rs6000/rs6000.c (rs6000_cell_dont_microcode): Delete unused variable.
+       (rs6000_override_options): Set rs6000_gen_cell_microcode if tuning for
+       cell and not already set.
+       Turn off string instructions if not generating cell microcode.
+       (rs6000_final_prescan_insn): New function that warns about microcoded
+       instructions.
+       * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Define.
+       * config/rs6000/rs6000.md
+       Replace cc_reg_not_cr0_operand with cc_reg_not_micro_cr0_operand if
+       the instruction would have been microcoded on the Cell.
+       Set cell_micro to always on unnamed patterns for the string instructions.
+       (cell_micro): Update definition, remove load/store conditional microcoded.
+       (sign_extend:DI): Define new pattern for non microcoded version.
+       (sign_extend:SI): Likewise.
+       (compare (div:P)): Set cell_micro to not.
+       (andsi3): Define as an expand.
+       (andsi3_mc): New pattern.
+       (andsi3_nomc): New pattern.
+       (andsi3_internal0_nomc): New pattern.
+       (andsi3_internal2): Rename to ...
+       (andsi3_internal2_mc): this and enable iff generating microcode.
+       (andsi3_internal3): Rename to ...
+       (andsi3_internal3_mc): this and enable iff generating microcode.
+       (andsi3_internal4): Enable iif generating microcode.
+       (andsi3_internal5): Rename to ..
+       (andsi3_internal5_mc): this and enable iff generating microcode.
+       (andsi3_internal5_nomc): New pattern.
+       (extzvdi_internal1): Enable iff generating microcode.
+       (extzvdi_internal2): Likewise.
+       (rotlsi3_internal7): Set cell_micro to always if non immediate form.
+       (anddi3): Change to expand.
+       (anddi3_mc): Rename from anddi3.
+       (anddi3_no_mc): New pattern.
+       (anddi3_internal2): Rename to ..
+       (anddi3_internal2_mc): this and enable iff generating microcode.
+       (anddi3_internal2_nomc): New pattern.
+       (anddi3_internal3): Rename to ..
+       (anddi3_internal3_mc): this and enable iff generating microcode.
+       (anddi3_internal3_nomc): New pattern.
+       (movti_string): Set cell_micro to always if TARGET_STRING.
+       (stmsi8): Set cell_micro to always.
+       (stmsi7): Likewise.
+       (stmsi6): Likewise.
+       (stmsi5): Likewise.
+       (stmsi4): Likewise.
+       (stmsi3): Likewise.
+       (stmsi8_power): Likewise.
+       (stmsi7_power): Likewise.
+       (stmsi6_power): Likewise.
+       (stmsi5_power): Likewise.
+       (stmsi4_power): Likewise.
+       (stmsi3_power): Likewise.
+       (movsi_update2): Enable iff generating microcode.
+       (movhi_update3): Likewise.
+       (lmw): Set cell_micro to always.
+
 2008-10-13  Richard Sandiford  <rdsandiford@googlemail.com>
 
        * config/s390/s390.md (UNSPEC_POOL_OFFSET): New constant.

diff --git a/gcc/cfglayout.c b/gcc/cfglayout.c
index 05e355d..27eb029 100644 (file)
--- a/gcc/cfglayout.c
+++ b/gcc/cfglayout.c
@@ -495,7 +495,7 @@ insn_scope (const_rtx insn)
 }
 
 /* Return line number of the statement specified by the locator.  */
-static location_t
+location_t
 locator_location (int loc)
 {
   int max = VEC_length (int, locations_locators_locs);

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 90ab081..a04a7d8 100644 (file)
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -104,6 +104,14 @@
                     || REGNO (op) > LAST_VIRTUAL_REGISTER
                     || CR_REGNO_NOT_CR0_P (REGNO (op))")))
 
+;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
+(define_predicate "cc_reg_not_micro_cr0_operand"
+   (and (match_operand 0 "register_operand")
+       (match_test "GET_CODE (op) != REG
+                    || REGNO (op) > LAST_VIRTUAL_REGISTER
+                    || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op)))
+                    || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))")))
+
 ;; Return 1 if op is a constant integer valid for D field
 ;; or non-special register register.
 (define_predicate "reg_or_short_operand"

diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 13e7bec..0c5b111 100644 (file)
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -181,5 +181,7 @@ extern void rs6000_cpu_cpp_builtins (struct cpp_reader *);
 char *output_call (rtx, rtx *, int, int);
 #endif
 
+void rs6000_final_prescan_insn (rtx, rtx *operand, int num_operands);
+
 extern bool rs6000_hard_regno_mode_ok_p[][FIRST_PSEUDO_REGISTER];
 #endif  /* rs6000-protos.h */

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 49828de..05f4e26 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -143,8 +143,6 @@ struct rs6000_cpu_select rs6000_select[3] =
   { (const char *)0,   "-mtune=",              1,      0 },
 };
 
-static GTY(()) bool rs6000_cell_dont_microcode;
-
 /* Always emit branch hint bits.  */
 static GTY(()) bool rs6000_always_hint;
 
@@ -1609,9 +1607,16 @@ rs6000_override_options (const char *default_cpu)
        error ("Spe not supported in this target");
     }
 
+  /* Disable cell micro code if we are optimizing for the cell
+     and not optimizing for size.  */
+  if (rs6000_gen_cell_microcode == -1)
+    rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
+                                  && !optimize_size);
+
   /* If we are optimizing big endian systems for space, use the load/store
-     multiple and string instructions.  */
-  if (BYTES_BIG_ENDIAN && optimize_size)
+     multiple and string instructions unless we are not generating
+     Cell microcode.  */
+  if (BYTES_BIG_ENDIAN && optimize_size && !rs6000_gen_cell_microcode)
     target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
 
   /* Don't allow -mmultiple or -mstring on little endian systems
@@ -22794,4 +22799,31 @@ rs6000_stack_protect_fail (void)
         : default_external_stack_protect_fail ();
 }
 
+void
+rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
+                          int num_operands ATTRIBUTE_UNUSED)
+{
+  if (rs6000_warn_cell_microcode)
+    {
+      const char *temp;
+      int insn_code_number = recog_memoized (insn);
+      location_t location = locator_location (INSN_LOCATOR (insn));
+
+      /* Punt on insns we cannot recognize.  */
+      if (insn_code_number < 0)
+       return;
+
+      temp = get_insn_template (insn_code_number, insn);
+
+      if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
+       warning_at (location, OPT_mwarn_cell_microcode,
+                   "emitting microcode insn %s\t[%s] #%d",
+                   temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn)); 
+      else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
+       warning_at (location, OPT_mwarn_cell_microcode,
+                   "emitting conditional microcode insn %s\t[%s] #%d",
+                   temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
+    }
+}
+
 #include "gt-rs6000.h"

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index de212cd..5874f36 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1905,7 +1905,8 @@ do {                                                              \
 /* Define this if some processing needs to be done immediately before
    emitting code for an insn.  */
 
-/* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
+#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
+  rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
 
 /* Specify the machine mode that this machine uses
    for the index in the tablejump instruction.  */

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3078cb3..4a49a5b 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -143,19 +143,11 @@
 
 
 ;; If this instruction is microcoded on the CELL processor
-; The default for load and stores is conditional
-; The default for load extended and the recorded instructions is always microcoded
+; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
 (define_attr "cell_micro" "not,conditional,always"
-  (if_then_else (ior (ior (eq_attr "type" "load")
-                          (eq_attr "type" "store"))
-                     (ior (eq_attr "type" "fpload")
-                          (eq_attr "type" "fpstore")))
-               (const_string "conditional")
-                (if_then_else (ior (eq_attr "type" "load_ext")
-                                  (ior (eq_attr "type" "compare")
-                                       (eq_attr "type" "delayed_compare")))
+ (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
                              (const_string "always")
-                              (const_string "not"))))
+                              (const_string "not")))
 
 
 (automata_option "ndfa")
@@ -259,7 +251,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:DI 2 ""))]
@@ -285,7 +277,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -318,7 +310,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:DI 2 ""))]
@@ -344,7 +336,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -366,13 +358,20 @@
 (define_insn ""
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
        (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
-  "TARGET_POWERPC64"
+  "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
   "@
    lha%U1%X1 %0,%1
    extsh %0,%1"
   [(set_attr "type" "load_ext,exts")])
 
 (define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+       (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
+  "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
+  "extsh %0,%1"
+  [(set_attr "type" "exts")])
+
+(define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
                    (const_int 0)))
@@ -385,7 +384,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:DI 2 ""))]
@@ -411,7 +410,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -433,13 +432,20 @@
 (define_insn ""
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
        (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
-  "TARGET_POWERPC64"
+  "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
   "@
    lwa%U1%X1 %0,%1
    extsw %0,%1"
   [(set_attr "type" "load_ext,exts")])
 
 (define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+       (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
+  "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
+  "extsw %0,%1"
+  [(set_attr "type" "exts")])
+
+(define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
                    (const_int 0)))
@@ -452,7 +458,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:DI 2 ""))]
@@ -478,7 +484,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -519,7 +525,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:SI 2 ""))]
@@ -545,7 +551,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
@@ -593,7 +599,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:SI 2 ""))]
@@ -619,7 +625,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
@@ -686,7 +692,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:HI 2 ""))]
@@ -712,7 +718,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:HI 0 "gpc_reg_operand" "")
@@ -760,7 +766,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:HI 2 ""))]
@@ -786,7 +792,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:HI 0 "gpc_reg_operand" "")
@@ -855,7 +861,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:SI 2 ""))]
@@ -881,7 +887,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
@@ -903,13 +909,20 @@
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
-  ""
+  "rs6000_gen_cell_microcode"
   "@
    lha%U1%X1 %0,%1
    {exts|extsh} %0,%1"
   [(set_attr "type" "load_ext,exts")])
 
 (define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+        (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
+  "!rs6000_gen_cell_microcode"
+  "{exts|extsh} %0,%1"
+  [(set_attr "type" "exts")])
+
+(define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
                    (const_int 0)))
@@ -922,7 +935,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:SI 2 ""))]
@@ -1479,7 +1492,7 @@
 })
 \f
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
@@ -1662,7 +1675,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:P 2 ""))]
@@ -1688,7 +1701,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
                    (const_int 0)))
    (set (match_operand:P 0 "gpc_reg_operand" "")
@@ -2343,7 +2356,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
                             (match_operand:SI 2 "gpc_reg_operand" ""))
                    (const_int 0)))
@@ -2403,7 +2416,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
                             (match_operand:SI 2 "gpc_reg_operand" ""))
                    (const_int 0)))
@@ -2595,7 +2608,8 @@
    {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
    #"
   [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
+   (set_attr "length" "8,12")
+   (set_attr "cell_micro" "not")])
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
@@ -2624,7 +2638,8 @@
    {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
    #"
   [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
+   (set_attr "length" "8,12")
+   (set_attr "cell_micro" "not")])
 
 (define_split
   [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
@@ -2818,12 +2833,21 @@
 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
 ;; those rotate-and-mask operations.  Thus, the AND insns come first.
 
-(define_insn "andsi3"
+(define_expand "andsi3"
+  [(parallel
+    [(set (match_operand:SI 0 "gpc_reg_operand" "")
+         (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
+                 (match_operand:SI 2 "and_operand" "")))
+     (clobber (match_scratch:CC 3 ""))])]
+  ""
+  "")
+
+(define_insn "andsi3_mc"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
        (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
                (match_operand:SI 2 "and_operand" "?r,T,K,L")))
    (clobber (match_scratch:CC 3 "=X,X,x,x"))]
-  ""
+  "rs6000_gen_cell_microcode"
   "@
    and %0,%1,%2
    {rlinm|rlwinm} %0,%1,0,%m2,%M2
@@ -2831,18 +2855,38 @@
    {andiu.|andis.} %0,%1,%u2"
   [(set_attr "type" "*,*,compare,compare")])
 
+(define_insn "andsi3_nomc"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+       (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+               (match_operand:SI 2 "and_operand" "?r,T")))
+   (clobber (match_scratch:CC 3 "=X,X"))]
+  "!rs6000_gen_cell_microcode"
+  "@
+   and %0,%1,%2
+   {rlinm|rlwinm} %0,%1,0,%m2,%M2")
+
+(define_insn "andsi3_internal0_nomc"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+        (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+                (match_operand:SI 2 "and_operand" "?r,T")))]
+  "!rs6000_gen_cell_microcode"
+  "@
+   and %0,%1,%2
+   {rlinm|rlwinm} %0,%1,0,%m2,%M2")
+
+
 ;; Note to set cr's other than cr0 we do the and immediate and then
 ;; the test again -- this avoids a mfcr which on the higher end
 ;; machines causes an execution serialization
 
-(define_insn "*andsi3_internal2"
+(define_insn "*andsi3_internal2_mc"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
    (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
-  "TARGET_32BIT"
+  "TARGET_32BIT && rs6000_gen_cell_microcode"
   "@
    and. %3,%1,%2
    {andil.|andi.} %3,%1,%b2
@@ -2855,14 +2899,14 @@
   [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
    (set_attr "length" "4,4,4,4,8,8,8,8")])
 
-(define_insn "*andsi3_internal3"
+(define_insn "*andsi3_internal3_mc"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
    (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && rs6000_gen_cell_microcode"
   "@
    #
    {andil.|andi.} %3,%1,%b2
@@ -2876,7 +2920,7 @@
    (set_attr "length" "8,4,4,4,8,8,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
                             (match_operand:GPR 2 "and_operand" ""))
                    (const_int 0)))
@@ -2921,7 +2965,7 @@
        (and:SI (match_dup 1)
                (match_dup 2)))
    (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
-  "TARGET_32BIT"
+  "TARGET_32BIT && rs6000_gen_cell_microcode"
   "@
    and. %0,%1,%2
    {andil.|andi.} %0,%1,%b2
@@ -2934,7 +2978,7 @@
   [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
    (set_attr "length" "4,4,4,4,8,8,8,8")])
 
-(define_insn "*andsi3_internal5"
+(define_insn "*andsi3_internal5_mc"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
@@ -2943,7 +2987,7 @@
        (and:SI (match_dup 1)
                (match_dup 2)))
    (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && rs6000_gen_cell_microcode"
   "@
    #
    {andil.|andi.} %0,%1,%b2
@@ -2956,8 +3000,22 @@
   [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
    (set_attr "length" "8,4,4,4,8,8,8,8")])
 
+(define_insn "*andsi3_internal5_nomc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y,??y,??y,?y")
+        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
+                            (match_operand:SI 2 "and_operand" "r,r,K,L,T"))
+                    (const_int 0)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
+        (and:SI (match_dup 1)
+                (match_dup 2)))
+   (clobber (match_scratch:CC 4 "=X,X,x,x,X"))]
+  "TARGET_64BIT && !rs6000_gen_cell_microcode"
+  "#"
+  [(set_attr "type" "compare")
+   (set_attr "length" "8,8,8,8,8")])
+
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
                            (match_operand:SI 2 "and_operand" ""))
                    (const_int 0)))
@@ -3088,7 +3146,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:SI 4 "boolean_operator"
         [(match_operand:SI 1 "gpc_reg_operand" "")
          (match_operand:SI 2 "gpc_reg_operand" "")])
@@ -3117,7 +3175,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:SI 4 "boolean_operator"
         [(match_operand:SI 1 "gpc_reg_operand" "")
          (match_operand:SI 2 "gpc_reg_operand" "")])
@@ -3176,7 +3234,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:SI 4 "boolean_operator"
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
          (match_operand:SI 2 "gpc_reg_operand" "")])
@@ -3205,7 +3263,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:SI 4 "boolean_operator"
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
          (match_operand:SI 2 "gpc_reg_operand" "")])
@@ -3242,7 +3300,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:SI 4 "boolean_operator"
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
          (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
@@ -3271,7 +3329,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:SI 4 "boolean_operator"
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
          (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
@@ -3778,7 +3836,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
                         (match_operand:SI 2 "const_int_operand" "")
                         (match_operand:SI 3 "const_int_operand" ""))
@@ -3829,7 +3887,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
                         (match_operand:SI 2 "const_int_operand" "")
                         (match_operand:SI 3 "const_int_operand" ""))
@@ -3870,7 +3928,7 @@
                         (match_operand:SI 3 "const_int_operand" "i"))
                    (const_int 0)))
    (clobber (match_scratch:DI 4 "=r"))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && rs6000_gen_cell_microcode"
   "*
 {
   int start = INTVAL (operands[3]) & 63;
@@ -3893,7 +3951,7 @@
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r")
        (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && rs6000_gen_cell_microcode"
   "*
 {
   int start = INTVAL (operands[3]) & 63;
@@ -3934,7 +3992,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
                    (const_int 0)))
@@ -3964,7 +4022,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
                    (const_int 0)))
@@ -4007,7 +4065,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (and:SI
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
                                (match_operand:SI 2 "reg_or_cint_operand" ""))
@@ -4043,7 +4101,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (and:SI
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
                                (match_operand:SI 2 "reg_or_cint_operand" ""))
@@ -4066,7 +4124,11 @@
          (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
   ""
-  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
+  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
+  [(set (attr "cell_micro")
+     (if_then_else (match_operand:SI 2 "const_int_operand" "")
+       (const_string "not")
+       (const_string "always")))])
 
 (define_insn "*rotlsi3_internal8"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -4086,7 +4148,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:SI
                     (subreg:QI
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -4122,7 +4184,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:SI
                     (subreg:QI
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -4169,7 +4231,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:SI
                     (subreg:HI
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -4205,7 +4267,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:SI
                     (subreg:HI
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -4408,7 +4470,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
                            (match_operand:SI 2 "const_int_operand" ""))
@@ -4441,7 +4503,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
                            (match_operand:SI 2 "const_int_operand" ""))
@@ -4653,7 +4715,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
                              (match_operand:SI 2 "const_int_operand" ""))
@@ -4686,7 +4748,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
                              (match_operand:SI 2 "const_int_operand" ""))
@@ -4728,7 +4790,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (zero_extend:SI
          (subreg:QI
@@ -4764,7 +4826,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (zero_extend:SI
          (subreg:QI
@@ -4807,7 +4869,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (zero_extend:SI
          (subreg:HI
@@ -4843,7 +4905,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (zero_extend:SI
          (subreg:HI
@@ -4971,7 +5033,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
                    (const_int 0)))
@@ -5035,7 +5097,7 @@
    (set_attr "length" "4,4,8,8")])
 \f
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
                    (const_int 0)))
@@ -6683,7 +6745,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
                             (match_operand:DI 2 "gpc_reg_operand" ""))
                    (const_int 0)))
@@ -6747,7 +6809,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
                               (match_operand:DI 2 "reg_or_cint_operand" ""))
                    (const_int 0)))
@@ -6777,7 +6839,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
                               (match_operand:DI 2 "reg_or_cint_operand" ""))
                    (const_int 0)))
@@ -6820,7 +6882,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (and:DI
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
                                (match_operand:DI 2 "reg_or_cint_operand" ""))
@@ -6856,7 +6918,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (and:DI
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
                                (match_operand:DI 2 "reg_or_cint_operand" ""))
@@ -6902,7 +6964,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:DI
                     (subreg:QI
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
@@ -6938,7 +7000,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:DI
                     (subreg:QI
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
@@ -6984,7 +7046,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:DI
                     (subreg:HI
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
@@ -7020,7 +7082,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:DI
                     (subreg:HI
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
@@ -7066,7 +7128,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:DI
                     (subreg:SI
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
@@ -7102,7 +7164,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (zero_extend:DI
                     (subreg:SI
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
@@ -7230,7 +7292,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
                            (match_operand:SI 2 "const_int_operand" ""))
@@ -7264,7 +7326,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
                            (match_operand:SI 2 "const_int_operand" ""))
@@ -7306,7 +7368,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
                            (match_operand:SI 2 "const_int_operand" ""))
@@ -7340,7 +7402,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
                            (match_operand:SI 2 "const_int_operand" ""))
@@ -7402,7 +7464,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
                    (const_int 0)))
@@ -7432,7 +7494,7 @@
    (set_attr "length" "4,4,8,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
                    (const_int 0)))
@@ -7540,12 +7602,21 @@
                    (const_int 0)))]
   "")
 
-(define_insn "anddi3"
+(define_expand "anddi3"
+  [(parallel
+    [(set (match_operand:DI 0 "gpc_reg_operand" "")
+         (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
+                 (match_operand:DI 2 "and64_2_operand" "")))
+     (clobber (match_scratch:CC 3 ""))])]
+  "TARGET_POWERPC64"
+  "")
+
+(define_insn "anddi3_mc"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
        (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
                (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
    (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
-  "TARGET_POWERPC64"
+  "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
   "@
    and %0,%1,%2
    rldic%B2 %0,%1,0,%S2
@@ -7556,6 +7627,19 @@
   [(set_attr "type" "*,*,*,compare,compare,*")
    (set_attr "length" "4,4,4,4,4,8")])
 
+(define_insn "anddi3_nomc"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
+       (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
+               (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
+   (clobber (match_scratch:CC 3 "=X,X,X,X"))]
+  "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
+  "@
+   and %0,%1,%2
+   rldic%B2 %0,%1,0,%S2
+   rlwinm %0,%1,0,%m2,%M2
+   #"
+  [(set_attr "length" "4,4,4,8")])
+
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
        (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
@@ -7577,14 +7661,14 @@
   build_mask64_2_operands (operands[2], &operands[4]);
 })
 
-(define_insn "*anddi3_internal2"
+(define_insn "*anddi3_internal2_mc"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
                            (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
                    (const_int 0)))
    (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
    (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && rs6000_gen_cell_microcode"
   "@
    and. %3,%1,%2
    rldic%B2. %3,%1,0,%S2
@@ -7601,6 +7685,18 @@
   [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
    (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
 
+(define_insn "*anddi3_internal2_nomc"
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y,?y,??y,??y,?y")
+       (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
+                           (match_operand:DI 2 "and64_2_operand" "t,r,S,K,J,t"))
+                   (const_int 0)))
+   (clobber (match_scratch:DI 3 "=r,r,r,r,r,r"))
+   (clobber (match_scratch:CC 4 "=X,X,X,x,x,X"))]
+  "TARGET_64BIT && !rs6000_gen_cell_microcode"
+  "#"
+  [(set_attr "type" "delayed_compare,compare,compare,compare,compare,compare")
+   (set_attr "length" "8,8,8,8,8,12")])
+
 (define_split
   [(set (match_operand:CC 0 "cc_reg_operand" "")
         (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
@@ -7627,7 +7723,7 @@
   build_mask64_2_operands (operands[2], &operands[5]);
 }")
 
-(define_insn "*anddi3_internal3"
+(define_insn "*anddi3_internal3_mc"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
                            (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
@@ -7635,7 +7731,7 @@
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
        (and:DI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
-  "TARGET_64BIT"
+  "TARGET_64BIT && rs6000_gen_cell_microcode"
   "@
    and. %0,%1,%2
    rldic%B2. %0,%1,0,%S2
@@ -7652,8 +7748,20 @@
   [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
    (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
 
+(define_insn "*anddi3_internal3_nomc"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y,?y,??y,??y,?y")
+       (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
+                           (match_operand:DI 2 "and64_2_operand" "t,r,S,K,J,t"))
+                   (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
+       (and:DI (match_dup 1) (match_dup 2)))
+   (clobber (match_scratch:CC 4 "=X,X,X,x,x,X"))]
+  "TARGET_64BIT  && !rs6000_gen_cell_microcode"
+  "#"
+  [(set_attr "type" "delayed_compare,compare,compare,compare,compare,compare")
+   (set_attr "length" "8,8,8,8,8,12")])
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
                            (match_operand:DI 2 "and64_2_operand" ""))
                    (const_int 0)))
@@ -7793,7 +7901,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:DI 4 "boolean_operator"
         [(match_operand:DI 1 "gpc_reg_operand" "")
          (match_operand:DI 2 "gpc_reg_operand" "")])
@@ -7822,7 +7930,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:DI 4 "boolean_operator"
         [(match_operand:DI 1 "gpc_reg_operand" "")
          (match_operand:DI 2 "gpc_reg_operand" "")])
@@ -7893,7 +8001,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:DI 4 "boolean_operator"
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
          (match_operand:DI 2 "gpc_reg_operand" "")])
@@ -7922,7 +8030,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:DI 4 "boolean_operator"
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
          (match_operand:DI 2 "gpc_reg_operand" "")])
@@ -7959,7 +8067,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:DI 4 "boolean_operator"
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
          (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
@@ -7988,7 +8096,7 @@
    (set_attr "length" "4,8")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operator:DI 4 "boolean_operator"
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
          (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
@@ -8129,7 +8237,7 @@
    (set_attr "length" "4,4,8")])
 
 (define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
                    (const_int 0)))
    (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
@@ -9160,7 +9268,10 @@
       return \"#\";
     }
 }"
-  [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
+  [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
+   (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
+                                         (const_string "always")
+                                         (const_string "conditional")))])
 
 (define_insn "*movti_ppc64"
   [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
@@ -9419,7 +9530,8 @@
          (match_operand:SI 10 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi7"
   [(match_parallel 0 "store_multiple_operation"
@@ -9440,7 +9552,8 @@
          (match_operand:SI 9 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi6"
   [(match_parallel 0 "store_multiple_operation"
@@ -9459,7 +9572,8 @@
          (match_operand:SI 8 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi5"
   [(match_parallel 0 "store_multiple_operation"
@@ -9476,7 +9590,8 @@
          (match_operand:SI 7 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi4"
   [(match_parallel 0 "store_multiple_operation"
@@ -9491,7 +9606,8 @@
          (match_operand:SI 6 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi3"
   [(match_parallel 0 "store_multiple_operation"
@@ -9504,7 +9620,8 @@
          (match_operand:SI 5 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi8_power"
   [(match_parallel 0 "store_multiple_operation"
@@ -9527,7 +9644,8 @@
          (match_operand:SI 10 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi7_power"
   [(match_parallel 0 "store_multiple_operation"
@@ -9548,7 +9666,8 @@
          (match_operand:SI 9 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi6_power"
   [(match_parallel 0 "store_multiple_operation"
@@ -9567,7 +9686,8 @@
          (match_operand:SI 8 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi5_power"
   [(match_parallel 0 "store_multiple_operation"
@@ -9584,7 +9704,8 @@
          (match_operand:SI 7 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi4_power"
   [(match_parallel 0 "store_multiple_operation"
@@ -9599,7 +9720,8 @@
          (match_operand:SI 6 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*stmsi3_power"
   [(match_parallel 0 "store_multiple_operation"
@@ -9612,7 +9734,8 @@
          (match_operand:SI 5 "gpc_reg_operand" "r"))])]
   "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
   "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store_ux")])
+  [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")])
 \f
 (define_expand "setmemsi"
   [(parallel [(set (match_operand:BLK 0 "" "")
@@ -9694,6 +9817,7 @@
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")
    (set_attr "length" "8")])
 
 (define_insn ""
@@ -9718,6 +9842,7 @@
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")
    (set_attr "length" "8")])
 
 ;; Move up to 24 bytes at a time.  The fixed registers are needed because the
@@ -9757,6 +9882,7 @@
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")
    (set_attr "length" "8")])
 
 (define_insn ""
@@ -9778,6 +9904,7 @@
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")
    (set_attr "length" "8")])
 
 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
@@ -9813,6 +9940,7 @@
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")
    (set_attr "length" "8")])
 
 (define_insn ""
@@ -9832,6 +9960,7 @@
    && REGNO (operands[4]) == 5"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")
    (set_attr "length" "8")])
 
 ;; Move up to 8 bytes at a time.
@@ -9856,6 +9985,7 @@
    && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")
    (set_attr "length" "8")])
 
 (define_insn ""
@@ -9869,6 +9999,7 @@
    && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")
    (set_attr "length" "8")])
 
 ;; Move up to 4 bytes at a time.
@@ -9893,6 +10024,7 @@
    && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")
    (set_attr "length" "8")])
 
 (define_insn ""
@@ -9906,6 +10038,7 @@
    && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "store_ux")
+   (set_attr "cell_micro" "always")
    (set_attr "length" "8")])
 \f
 ;; Define insns that do load or store with update.  Some of these we can
@@ -9960,7 +10093,7 @@
                          (match_operand:DI 2 "gpc_reg_operand" "r")))))
    (set (match_operand:DI 0 "gpc_reg_operand" "=b")
        (plus:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64"
+  "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
   "lwaux %3,%0,%2"
   [(set_attr "type" "load_ext_ux")])
 
@@ -10008,7 +10141,7 @@
                          (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
    (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
        (plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_UPDATE"
+  "TARGET_UPDATE && rs6000_gen_cell_microcode"
   "@
    lhaux %3,%0,%2
    lhau %3,%2(%0)"
@@ -12208,7 +12341,7 @@
    (set_attr "length" "8,16")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
                                       [(match_operand 2 "cc_reg_operand" "")
@@ -12618,7 +12751,7 @@
    (set_attr "length" "8,12")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (plus:DI (lshiftrt:DI
                   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
@@ -12697,7 +12830,7 @@
    (set_attr "length" "8,12")])
 
 (define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (plus:DI (lshiftrt:DI
                   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
@@ -13405,7 +13538,7 @@
    (set_attr "length" "12,12,16,16")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (geu:P (match_operand:P 1 "gpc_reg_operand" "")
                (match_operand:P 2 "reg_or_neg_short_operand" ""))
@@ -13695,7 +13828,7 @@
    (set_attr "length" "12,16")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
                         (const_int 0))
@@ -13761,7 +13894,7 @@
    (set_attr "length" "12,16")])
 
 (define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
        (compare:CC
         (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
                         (const_int 0))
@@ -14562,7 +14695,8 @@
                                 (match_operand:SI 2 "memory_operand" "m"))])]
   "TARGET_MULTIPLE"
   "{lm|lmw} %1,%2"
-  [(set_attr "type" "load_ux")])
+  [(set_attr "type" "load_ux")
+   (set_attr "cell_micro" "always")])
 
 (define_insn "*return_internal_<mode>"
   [(return)

diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index a7fb83a..0dc67b7 100644 (file)
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -233,6 +233,14 @@ mlongcall
 Target Report Var(rs6000_default_long_calls)
 Avoid all range limits on call instructions
 
+mgen-cell-microcode
+Target Report Var(rs6000_gen_cell_microcode) Init(-1)
+Generate Cell microcode
+
+mwarn-cell-microcode
+Target Var(rs6000_warn_cell_microcode) Init(0) Warning
+Emitting warning when a Cell microcode is emitted
+
 mwarn-altivec-long
 Target Var(rs6000_warn_altivec_long) Init(1)
 Warn about deprecated 'vector long ...' AltiVec type usage

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d17ef60..c05ced4 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -735,6 +735,7 @@ See RS/6000 and PowerPC Options.
 -mspe -mno-spe @gol
 -mspe=yes  -mspe=no @gol
 -mpaired @gol
+-mgen-cell-microcode -mwarn-cell-microcode @gol
 -mvrsave -mno-vrsave @gol
 -mmulhw -mno-mulhw @gol
 -mdlmzb -mno-dlmzb @gol
@@ -13490,6 +13491,15 @@ enhancements.
 @opindex mno-vrsave
 Generate VRSAVE instructions when generating AltiVec code.
 
+@item -mgen-cell-microcode
+@opindex mgen-cell-microcode
+Generate Cell microcode instructions
+
+@item -mwarn-cell-microcode
+@opindex mwarn-cell-microcode
+Warning when a Cell microcode instruction is going to emitted.  An example
+of a Cell microcode instruction is a variable shift.
+
 @item -msecure-plt
 @opindex msecure-plt
 Generate code that allows ld and ld.so to build executables and shared

diff --git a/gcc/rtl.h b/gcc/rtl.h
index 118025a..5bd7905 100644 (file)
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -1637,6 +1637,7 @@ extern rtx prev_cc0_setter (rtx);
 /* In cfglayout.c  */
 extern int insn_line (const_rtx);
 extern const char * insn_file (const_rtx);
+extern location_t locator_location (int);
 extern int locator_line (int);
 extern const char * locator_file (int);
 extern bool locator_eq (int, int);