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spu: Implement vec_permv16qi.
authorrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>
Fri, 14 Oct 2011 03:18:14 +0000 (03:18 +0000)
committerrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>
Fri, 14 Oct 2011 03:18:14 +0000 (03:18 +0000)
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179954 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/spu/spu.md

index 2f0dfe0..9e34eca 100644 (file)
@@ -2,6 +2,8 @@
 
        * config/rs6000/altivec.md (vec_permv16qi): New pattern.
 
+       * config/rs6000/spu.md (vec_permv16qi): New pattern.
+
 2011-10-13  Jakub Jelinek  <jakub@redhat.com>
 
        * config/i386/sse.md (vec_set<mode>): Change V_128 iterator mode
index 676d54e..00cfaa4 100644 (file)
@@ -4395,6 +4395,18 @@ selb\t%0,%4,%0,%3"
   "shufb\t%0,%1,%2,%3"
   [(set_attr "type" "shuf")])
 
+(define_expand "vec_permv16qi"
+  [(set (match_operand:V16QI 0 "spu_reg_operand" "")
+       (unspec:V16QI
+         [(match_operand:V16QI 1 "spu_reg_operand" "")
+          (match_operand:V16QI 2 "spu_reg_operand" "")
+          (match_operand:V16QI 3 "spu_reg_operand" "")]
+         UNSPEC_SHUFB))]
+  ""
+  {
+    operands[3] = gen_lowpart (TImode, operands[3]);
+  })
+
 (define_insn "nop"
   [(unspec_volatile [(const_int 0)] UNSPECV_NOP)]
   ""