2009-09-03 Daniel Gutson <dgutson@codesourcery.com>

	* config/arm/arm.md (UNSPEC_RBIT): New constant.
	(rbitsi2): New insn.
	(ctzsi2): New expand.
	* config/arm/arm.h (CTZ_DEFINED_VALUE_AT_ZERO): New macro.

	testsuite/
	* gcc.target/arm/ctz.c: New test case.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@151402 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3cbcff3..a3a0f8b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2009-09-03  Daniel Gutson  <dgutson@codesourcery.com>
+
+       * config/arm/arm.md (UNSPEC_RBIT): New constant.
+       (rbitsi2): New insn.
+       (ctzsi2): New expand.
+       * config/arm/arm.h (CTZ_DEFINED_VALUE_AT_ZERO): New macro.
+
+       testsuite/
+       * gcc.target/arm/ctz.c: New test case.
+
 2009-09-03  Martin Jambor  <mjambor@suse.cz>
 
        * tree-sra.c (duplicate_expr_for_different_base): Removed.

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index ae32da5..215c9fb 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2368,6 +2368,7 @@ extern int making_const_table;
 
 /* The arm5 clz instruction returns 32.  */
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
+#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
 \f
 #undef  ASM_APP_OFF
 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 09a1b08..fd00c70 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -100,6 +100,7 @@
    (UNSPEC_GOTSYM_OFF 24) ; The offset of the start of the the GOT from a
                          ; a given symbolic address.
    (UNSPEC_THUMB1_CASESI 25) ; A Thumb1 compressed dispatch-table call.
+   (UNSPEC_RBIT 26)       ; rbit operation.
   ]
 )
 
@@ -10955,6 +10956,26 @@
   [(set_attr "predicable" "yes")
    (set_attr "insn" "clz")])
 
+(define_insn "rbitsi2"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+       (unspec:SI [(match_operand:SI 1 "s_register_operand" "r")] UNSPEC_RBIT))]
+  "TARGET_32BIT && arm_arch_thumb2"
+  "rbit%?\\t%0, %1"
+  [(set_attr "predicable" "yes")
+   (set_attr "insn" "clz")])
+
+(define_expand "ctzsi2"
+ [(set (match_operand:SI           0 "s_register_operand" "")
+       (ctz:SI (match_operand:SI  1 "s_register_operand" "")))]
+  "TARGET_32BIT && arm_arch_thumb2"
+  "
+   rtx tmp = gen_reg_rtx (SImode); 
+   emit_insn (gen_rbitsi2 (tmp, operands[1]));
+   emit_insn (gen_clzsi2 (operands[0], tmp));
+   DONE;
+  "
+)
+
 ;; V5E instructions.
 
 (define_insn "prefetch"

diff --git a/gcc/testsuite/gcc.target/arm/ctz.c b/gcc/testsuite/gcc.target/arm/ctz.c
new file mode 100644 (file)
index 0000000..63e9d02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/ctz.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O2 -march=armv6t2" } */
+
+unsigned int functest(unsigned int x)
+{
+       return __builtin_ctz(x);
+}
+
+/* { dg-final { scan-assembler "rbit" } } */
+/* { dg-final { scan-assembler "clz" } } */
+/* { dg-final { scan-assembler-not "rsb" } } */