operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
- return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
+ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
}")
(define_insn ""
int start = INTVAL (operands[2]) & 31;
int size = INTVAL (operands[1]) & 31;
- operands[4] = gen_rtx (CONST_INT, VOIDmode, (shift - start - size) & 31);
+ operands[4] = gen_rtx (CONST_INT, VOIDmode, shift - start - size);
operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
- return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
+ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
}")
(define_insn ""
int start = INTVAL (operands[2]) & 31;
int size = INTVAL (operands[1]) & 31;
- operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31);
+ operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - shift - start - size);
operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
- return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
+ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
}")
(define_insn ""
int start = INTVAL (operands[2]) & 31;
int size = INTVAL (operands[1]) & 31;
- operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31);
+ operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - shift - start - size);
operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
- return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
+ return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
}")
(define_insn ""
/* Align extract field with insert field */
operands[5] = gen_rtx (CONST_INT, VOIDmode,
- (extract_start + extract_size - insert_start - insert_size) & 31);
+ extract_start + extract_size - insert_start - insert_size);
operands[1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size - 1);
- return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\";
+ return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
}")
(define_insn ""
int size = INTVAL (operands[1]) & 63;
operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - start - size);
- operands[1] = gen_rtx (CONST_INT, VOIDmode, start);
- return \"rldimi %0,%3,%2,%1\";
+ return \"rldimi %0,%3,%H2,%H1\";
}")
(define_expand "extzv"
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_cint_operand" "ri")))]
"TARGET_POWERPC64"
- "rld%I2cl %0,%1,%h2,0")
+ "rld%I2cl %0,%1,%H2,0")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(const_int 0)))
(clobber (match_scratch:DI 3 "=r"))]
"TARGET_POWERPC64"
- "rld%I2cl. %3,%1,%h2,0"
+ "rld%I2cl. %3,%1,%H2,0"
[(set_attr "type" "delayed_compare")])
(define_insn ""
(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(rotate:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
- "rld%I2cl. %0,%1,%h2,0"
+ "rld%I2cl. %0,%1,%H2,0"
[(set_attr "type" "delayed_compare")])
(define_expand "ashldi3"
(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"TARGET_POWERPC64"
- "sld%I2 %0,%1,%2"
+ "sld%I2 %0,%1,%H2"
[(set_attr "length" "8")])
(define_insn ""
(const_int 0)))
(clobber (match_scratch:DI 3 "=r"))]
"TARGET_POWERPC64"
- "sld%I2. %3,%1,%2"
+ "sld%I2. %3,%1,%H2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(ashift:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
- "sld%I2. %0,%1,%2"
+ "sld%I2. %0,%1,%H2"
[(set_attr "type" "delayed_compare")])
(define_expand "lshrdi3"
(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"TARGET_POWERPC64"
- "srd%I2 %0,%1,%2")
+ "srd%I2 %0,%1,%H2")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(const_int 0)))
(clobber (match_scratch:DI 3 "=r"))]
"TARGET_POWERPC64"
- "srd%I2. %3,%1,%2"
+ "srd%I2. %3,%1,%H2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(lshiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC64"
- "srd%I2. %0,%1,%2"
+ "srd%I2. %0,%1,%H2"
[(set_attr "type" "delayed_compare")])
(define_expand "ashrdi3"