const int dmul; /* cost of DFmode multiplication (and fmadd). */
const int sdiv; /* cost of SFmode division (fdivs). */
const int ddiv; /* cost of DFmode division (fdiv). */
+ const int cache_line_size; /* cache block in bytes. */
+ const int l1_cache_lines; /* number of lines in L1 cache. */
+ const int simultaneous_prefetches; /* number of parallel prefetch
+ operations. */
};
const struct processor_costs *rs6000_cost;
COSTS_N_INSNS (1), /* dmul */
COSTS_N_INSNS (1), /* sdiv */
COSTS_N_INSNS (1), /* ddiv */
+ 32,
+ 0,
+ 0,
};
/* Instruction size costs on 64bit processors. */
COSTS_N_INSNS (1), /* dmul */
COSTS_N_INSNS (1), /* sdiv */
COSTS_N_INSNS (1), /* ddiv */
+ 128,
+ 0,
+ 0,
};
/* Instruction costs on RIOS1 processors. */
COSTS_N_INSNS (2), /* dmul */
COSTS_N_INSNS (19), /* sdiv */
COSTS_N_INSNS (19), /* ddiv */
+ 32,
+ 1024, /* cache lines */
+ 0, /* streams */
};
/* Instruction costs on RIOS2 processors. */
COSTS_N_INSNS (2), /* dmul */
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (17), /* ddiv */
+ 32,
+ 1024, /* cache lines */
+ 0, /* streams */
};
/* Instruction costs on RS64A processors. */
COSTS_N_INSNS (4), /* dmul */
COSTS_N_INSNS (31), /* sdiv */
COSTS_N_INSNS (31), /* ddiv */
+ 128,
+ 1024, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on MPCCORE processors. */
COSTS_N_INSNS (5), /* dmul */
COSTS_N_INSNS (10), /* sdiv */
COSTS_N_INSNS (17), /* ddiv */
+ 128,
+ 512, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC403 processors. */
COSTS_N_INSNS (11), /* dmul */
COSTS_N_INSNS (11), /* sdiv */
COSTS_N_INSNS (11), /* ddiv */
+ 32,
+ 128, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC405 processors. */
COSTS_N_INSNS (11), /* dmul */
COSTS_N_INSNS (11), /* sdiv */
COSTS_N_INSNS (11), /* ddiv */
+ 32,
+ 512, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC440 processors. */
COSTS_N_INSNS (5), /* dmul */
COSTS_N_INSNS (19), /* sdiv */
COSTS_N_INSNS (33), /* ddiv */
+ 32,
+ 1024, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC601 processors. */
COSTS_N_INSNS (5), /* dmul */
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (31), /* ddiv */
+ 32,
+ 1024, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC603 processors. */
COSTS_N_INSNS (4), /* dmul */
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (33), /* ddiv */
+ 32,
+ 256, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC604 processors. */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (32), /* ddiv */
+ 32,
+ 512, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC604e processors. */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (32), /* ddiv */
+ 32,
+ 1024, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC620 processors. */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (18), /* sdiv */
COSTS_N_INSNS (32), /* ddiv */
+ 128,
+ 512, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC630 processors. */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (21), /* ddiv */
+ 128,
+ 512, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on Cell processor. */
COSTS_N_INSNS (10/2), /* dmul */
COSTS_N_INSNS (74/2), /* sdiv */
COSTS_N_INSNS (74/2), /* ddiv */
+ 128,
+ 256, /* cache lines */
+ 6, /* streams */
};
/* Instruction costs on PPC750 and PPC7400 processors. */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (31), /* ddiv */
+ 32,
+ 1024, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC7450 processors. */
COSTS_N_INSNS (5), /* dmul */
COSTS_N_INSNS (21), /* sdiv */
COSTS_N_INSNS (35), /* ddiv */
+ 32,
+ 1024, /* cache lines */
+ 1, /* streams */
};
/* Instruction costs on PPC8540 processors. */
COSTS_N_INSNS (4), /* dmul */
COSTS_N_INSNS (29), /* sdiv */
COSTS_N_INSNS (29), /* ddiv */
+ 32,
+ 1024, /* cache lines */
+ 1, /* prefetch streams /*/
};
/* Instruction costs on POWER4 and POWER5 processors. */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (17), /* sdiv */
COSTS_N_INSNS (17), /* ddiv */
+ 128,
+ 256, /* cache lines */
+ 8, /* prefetch streams /*/
};
/* Instruction costs on POWER6 processors. */
COSTS_N_INSNS (3), /* dmul */
COSTS_N_INSNS (13), /* sdiv */
COSTS_N_INSNS (16), /* ddiv */
+ 128,
+ 512, /* cache lines */
+ 16, /* prefetch streams */
};
\f
default:
gcc_unreachable ();
}
+
+ if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
+ set_param_value ("simultaneous-prefetches",
+ rs6000_cost->simultaneous_prefetches);
+ if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
+ set_param_value ("l1-cache-size", rs6000_cost->l1_cache_lines);
+ if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
+ set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
}
/* Implement targetm.vectorize.builtin_mask_for_load. */