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* pa.md: Disparage copies between general and floating-point registers
authordanglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 17 Jan 2006 00:24:11 +0000 (00:24 +0000)
committerdanglin <danglin@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 17 Jan 2006 00:24:11 +0000 (00:24 +0000)
in 32-bit move patterns.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@109788 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/pa/pa.md

index c1775ce..bc7f001 100644 (file)
@@ -1,3 +1,8 @@
+2006-01-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+       * pa.md: Disparage copies between general and floating-point registers
+       in 32-bit move patterns.
+
 2006-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR testsuite/25741
index b51feb0..b8131a8 100644 (file)
 
 (define_insn ""
   [(set (match_operand:SI 0 "move_dest_operand"
-                         "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,r,f")
+                         "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,!r,!f")
        (match_operand:SI 1 "move_src_operand"
-                         "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,f,r"))]
+                         "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,!f,!r"))]
   "(register_operand (operands[0], SImode)
     || reg_or_0_operand (operands[1], SImode))
    && !TARGET_SOFT_FLOAT
 
 (define_insn ""
   [(set (match_operand:DF 0 "move_dest_operand"
-                         "=f,*r,Q,?o,?Q,f,*r,*r,r,f")
+                         "=f,*r,Q,?o,?Q,f,*r,*r,!r,!f")
        (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
-                         "fG,*rG,f,*r,*r,RQ,o,RQ,f,r"))]
+                         "fG,*rG,f,*r,*r,RQ,o,RQ,!f,!r"))]
   "(register_operand (operands[0], DFmode)
     || reg_or_0_operand (operands[1], DFmode))
    && !(GET_CODE (operands[1]) == CONST_DOUBLE
 
 (define_insn ""
   [(set (match_operand:DF 0 "move_dest_operand"
-                         "=r,?o,?Q,r,r,r,f")
+                         "=r,?o,?Q,r,r,!r,!f")
        (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
-                         "rG,r,r,o,RQ,f,r"))]
+                         "rG,r,r,o,RQ,!f,!r"))]
   "(register_operand (operands[0], DFmode)
     || reg_or_0_operand (operands[1], DFmode))
    && !TARGET_64BIT
 
 (define_insn ""
   [(set (match_operand:DI 0 "move_dest_operand"
-                         "=r,o,Q,r,r,r,*f,*f,T,r,f")
+                         "=r,o,Q,r,r,r,*f,*f,T,!r,!f")
        (match_operand:DI 1 "general_operand"
-                         "rM,r,r,o*R,Q,i,*fM,RT,*f,f,r"))]
+                         "rM,r,r,o*R,Q,i,*fM,RT,*f,!f,!r"))]
   "(register_operand (operands[0], DImode)
     || reg_or_0_operand (operands[1], DImode))
    && !TARGET_64BIT
 
 (define_insn ""
   [(set (match_operand:SF 0 "move_dest_operand"
-                         "=f,!*r,f,*r,Q,Q,r,f")
+                         "=f,!*r,f,*r,Q,Q,!r,!f")
        (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
-                         "fG,!*rG,RQ,RQ,f,*rG,f,r"))]
+                         "fG,!*rG,RQ,RQ,f,*rG,!f,!r"))]
   "(register_operand (operands[0], SFmode)
     || reg_or_0_operand (operands[1], SFmode))
    && !TARGET_SOFT_FLOAT