X-Git-Url: http://git.sourceforge.jp/view?p=pf3gnuchains%2Fgcc-fork.git;a=blobdiff_plain;f=gcc%2Fregs.h;h=ee074b9ed1bed325dfa4f22da85d2739327170fd;hp=3857c829dc1dbc489c6f5d611eeb0f6d528d876d;hb=0ab5481f30050ed8a84fb6f77fdf48f0fc0678c4;hpb=63f236087f033781e482c61b8d159595cb371d4f diff --git a/gcc/regs.h b/gcc/regs.h index 3857c829dc1..ee074b9ed1b 100644 --- a/gcc/regs.h +++ b/gcc/regs.h @@ -1,47 +1,38 @@ /* Define per-register tables for data flow info and register allocation. Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, - 1999, 2000 Free Software Foundation, Inc. + 1999, 2000, 2003, 2004 Free Software Foundation, Inc. -This file is part of GNU CC. +This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2, or (at your option) any later +version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ +along with GCC; see the file COPYING. If not, write to the Free +Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA +02110-1301, USA. */ +#ifndef GCC_REGS_H +#define GCC_REGS_H #include "varray.h" +#include "obstack.h" +#include "hard-reg-set.h" +#include "basic-block.h" #define REG_BYTES(R) mode_size[(int) GET_MODE (R)] -/* Get the number of consecutive hard regs required to hold the REG or - SUBREG rtx R. - When something may be an explicit hard reg, REG_SIZE is the only - valid way to get this value. You cannot get it from the regno. - - A target may override this definition, the case where you would do - this is where there are registers which are smaller than WORD_SIZE - such as the SFmode registers on sparc64. */ - -#ifndef REG_SIZE -#define REG_SIZE(R) \ - ((mode_size[(int) GET_MODE (R)] + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -#endif - /* When you only have the mode of a pseudo register before it has a hard register chosen for it, this reports the size of each hard register - a pseudo in such a mode would get allocated to. Like REG_SIZE, a - target may override this. */ + a pseudo in such a mode would get allocated to. A target may + override this. */ #ifndef REGMODE_NATURAL_SIZE #define REGMODE_NATURAL_SIZE(MODE) UNITS_PER_WORD @@ -60,7 +51,6 @@ typedef struct reg_info_def { /* fields set by reg_scan */ int first_uid; /* UID of first insn to use (REG n) */ int last_uid; /* UID of last insn to use (REG n) */ - int last_note_uid; /* UID of last note to use (REG n) */ /* fields set by reg_scan & flow_analysis */ int sets; /* # of times (REG n) is set */ @@ -71,26 +61,48 @@ typedef struct reg_info_def int deaths; /* # of times (REG n) dies */ int live_length; /* # of instructions (REG n) is live */ int calls_crossed; /* # of calls (REG n) is live across */ + int throw_calls_crossed; /* # of calls that may throw (REG n) is live across */ int basic_block; /* # of basic blocks (REG n) is used in */ - char changes_mode; /* whether (SUBREG (REG n)) exists and - is illegal. */ } reg_info; -extern varray_type reg_n_info; +typedef reg_info *reg_info_p; + +DEF_VEC_P(reg_info_p); +DEF_VEC_ALLOC_P(reg_info_p,heap); + +extern VEC(reg_info_p,heap) *reg_n_info; /* Indexed by n, gives number of times (REG n) is used or set. */ -#define REG_N_REFS(N) (VARRAY_REG (reg_n_info, N)->refs) +#define REG_N_REFS(N) (VEC_index (reg_info_p, reg_n_info, N)->refs) /* Estimate frequency of references to register N. */ -#define REG_FREQ(N) (VARRAY_REG (reg_n_info, N)->freq) +#define REG_FREQ(N) (VEC_index (reg_info_p, reg_n_info, N)->freq) + +/* The weights for each insn varries from 0 to REG_FREQ_BASE. + This constant does not need to be high, as in infrequently executed + regions we want to count instructions equivalently to optimize for + size instead of speed. */ +#define REG_FREQ_MAX 1000 + +/* Compute register frequency from the BB frequency. When optimizing for size, + or profile driven feedback is available and the function is never executed, + frequency is always equivalent. Otherwise rescale the basic block + frequency. */ +#define REG_FREQ_FROM_BB(bb) (optimize_size \ + || (flag_branch_probabilities \ + && !ENTRY_BLOCK_PTR->count) \ + ? REG_FREQ_MAX \ + : ((bb)->frequency * REG_FREQ_MAX / BB_FREQ_MAX)\ + ? ((bb)->frequency * REG_FREQ_MAX / BB_FREQ_MAX)\ + : 1) /* Indexed by n, gives number of times (REG n) is set. ??? both regscan and flow allocate space for this. We should settle on just copy. */ -#define REG_N_SETS(N) (VARRAY_REG (reg_n_info, N)->sets) +#define REG_N_SETS(N) (VEC_index (reg_info_p, reg_n_info, N)->sets) /* Indexed by N, gives number of insns in which register N dies. Note that if register N is live around loops, it can die @@ -98,14 +110,7 @@ extern varray_type reg_n_info; So this is only a reliable indicator of how many regions of life there are for registers that are contained in one basic block. */ -#define REG_N_DEATHS(N) (VARRAY_REG (reg_n_info, N)->deaths) - -/* Indexed by N; says whether a pseudo register N was ever used - within a SUBREG that changes the mode of the reg in some way - that is illegal for a given class (usually floating-point) - of registers. */ - -#define REG_CHANGES_MODE(N) (VARRAY_REG (reg_n_info, N)->changes_mode) +#define REG_N_DEATHS(N) (VEC_index (reg_info_p, reg_n_info, N)->deaths) /* Get the number of consecutive words required to hold pseudo-reg N. */ @@ -124,7 +129,14 @@ extern varray_type reg_n_info; /* Indexed by N, gives number of CALL_INSNS across which (REG n) is live. */ -#define REG_N_CALLS_CROSSED(N) (VARRAY_REG (reg_n_info, N)->calls_crossed) +#define REG_N_CALLS_CROSSED(N) \ + (VEC_index (reg_info_p, reg_n_info, N)->calls_crossed) + +/* Indexed by N, gives number of CALL_INSNS that may throw, across which + (REG n) is live. */ + +#define REG_N_THROWING_CALLS_CROSSED(N) \ + (VEC_index (reg_info_p, reg_n_info, N)->throw_calls_crossed) /* Total number of instructions at which (REG n) is live. The larger this is, the less priority (REG n) gets for @@ -141,7 +153,8 @@ extern varray_type reg_n_info; is not required. global.c makes an allocno for this but does not try to assign a hard register to it. */ -#define REG_LIVE_LENGTH(N) (VARRAY_REG (reg_n_info, N)->live_length) +#define REG_LIVE_LENGTH(N) \ + (VEC_index (reg_info_p, reg_n_info, N)->live_length) /* Vector of substitutions of register numbers, used to map pseudo regs into hardware regs. @@ -152,14 +165,17 @@ extern varray_type reg_n_info; extern short *reg_renumber; -/* Vector indexed by hardware reg - saying whether that reg is ever used. */ +/* Vector indexed by hardware reg saying whether that reg is ever used. */ extern char regs_ever_live[FIRST_PSEUDO_REGISTER]; -/* Vector indexed by hardware reg giving its name. */ +/* Like regs_ever_live, but saying whether reg is set by asm statements. */ + +extern char regs_asm_clobbered[FIRST_PSEUDO_REGISTER]; + +/* Vector indexed by machine mode saying whether there are regs of that mode. */ -extern const char * reg_names[FIRST_PSEUDO_REGISTER]; +extern bool have_regs_of_mode [MAX_MACHINE_MODE]; /* For each hard register, the widest mode object that it can contain. This will be a MODE_INT mode if the register can hold integers. Otherwise @@ -173,7 +189,7 @@ extern enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; It is sometimes adjusted for subsequent changes during loop, but not adjusted by cse even if cse invalidates it. */ -#define REGNO_FIRST_UID(N) (VARRAY_REG (reg_n_info, N)->first_uid) +#define REGNO_FIRST_UID(N) (VEC_index (reg_info_p, reg_n_info, N)->first_uid) /* Vector indexed by regno; gives uid of last insn using that reg. This is computed by reg_scan for use by cse and loop. @@ -181,11 +197,7 @@ extern enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; but not adjusted by cse even if cse invalidates it. This is harmless since cse won't scan through a loop end. */ -#define REGNO_LAST_UID(N) (VARRAY_REG (reg_n_info, N)->last_uid) - -/* Similar, but includes insns that mention the reg in their notes. */ - -#define REGNO_LAST_NOTE_UID(N) (VARRAY_REG (reg_n_info, N)->last_note_uid) +#define REGNO_LAST_UID(N) (VEC_index (reg_info_p, reg_n_info, N)->last_uid) /* List made of EXPR_LIST rtx's which gives pairs of pseudo registers that have to go in the same hard reg. */ @@ -213,14 +225,19 @@ extern int caller_save_needed; /* Select a register mode required for caller save of hard regno REGNO. */ #ifndef HARD_REGNO_CALLER_SAVE_MODE #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ - choose_hard_reg_mode (REGNO, NREGS) + choose_hard_reg_mode (REGNO, NREGS, false) #endif -/* Registers that get partially clobbered by a call in a given mode. +/* Registers that get partially clobbered by a call in a given mode. These must not be call used registers. */ #ifndef HARD_REGNO_CALL_PART_CLOBBERED #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) 0 #endif /* Allocate reg_n_info tables */ -extern void allocate_reg_info PARAMS ((size_t, int, int)); +extern void allocate_reg_info (size_t, int, int); + +/* Specify number of hard registers given machine mode occupy. */ +extern unsigned char hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE]; + +#endif /* GCC_REGS_H */